Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 16 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 17 | #include <device/pci_ops.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 18 | #include <soc/pci_devs.h> |
| 19 | #include <soc/ramstage.h> |
| 20 | #include <soc/sata.h> |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 21 | #include <console/console.h> |
| 22 | #include <delay.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | |
| 27 | #include "chip.h" |
| 28 | |
| 29 | typedef struct soc_intel_baytrail_config config_t; |
| 30 | |
| 31 | static inline void sir_write(struct device *dev, int idx, u32 value) |
| 32 | { |
| 33 | pci_write_config32(dev, SATA_SIRI, idx); |
| 34 | pci_write_config32(dev, SATA_SIRD, value); |
| 35 | } |
| 36 | |
| 37 | static void sata_init(struct device *dev) |
| 38 | { |
| 39 | config_t *config = dev->chip_info; |
| 40 | u32 reg32; |
| 41 | u16 reg16; |
| 42 | u8 reg8; |
| 43 | |
| 44 | printk(BIOS_DEBUG, "SATA: Initializing...\n"); |
| 45 | |
| 46 | if (config == NULL) { |
| 47 | printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); |
| 48 | return; |
| 49 | } |
| 50 | |
| 51 | if (!config->sata_ahci) { |
| 52 | /* Set legacy or native decoding mode */ |
| 53 | if (config->ide_legacy_combined) { |
| 54 | reg8 = pci_read_config8(dev, 0x09); |
| 55 | reg8 &= ~0x5; |
| 56 | pci_write_config8(dev, 0x09, reg8); |
| 57 | } else { |
| 58 | reg8 = pci_read_config8(dev, 0x09); |
| 59 | reg8 |= 0x5; |
| 60 | pci_write_config8(dev, 0x09, reg8); |
| 61 | } |
| 62 | |
| 63 | /* Set capabilities pointer */ |
| 64 | pci_write_config8(dev, 0x34, 0x70); |
| 65 | reg16 = pci_read_config16(dev, 0x70); |
| 66 | reg16 &= ~0xFF00; |
| 67 | pci_write_config16(dev, 0x70, reg16); |
| 68 | } |
| 69 | |
| 70 | /* Primary timing - decode enable */ |
| 71 | reg16 = pci_read_config16(dev, 0x40); |
| 72 | reg16 |= 1 << 15; |
| 73 | pci_write_config16(dev, 0x40, reg16); |
| 74 | |
| 75 | /* Secondary timing - decode enable */ |
| 76 | reg16 = pci_read_config16(dev, 0x42); |
| 77 | reg16 |= 1 << 15; |
| 78 | pci_write_config16(dev, 0x42, reg16); |
| 79 | |
| 80 | /* Port mapping enables */ |
| 81 | reg16 = pci_read_config16(dev, 0x90); |
| 82 | reg16 |= (config->sata_port_map ^ 0x3) << 8; |
| 83 | pci_write_config16(dev, 0x90, reg16); |
| 84 | |
| 85 | /* Port control enables */ |
| 86 | reg16 = pci_read_config16(dev, 0x92); |
| 87 | reg16 &= ~0x003f; |
| 88 | reg16 |= config->sata_port_map; |
| 89 | pci_write_config16(dev, 0x92, reg16); |
| 90 | |
| 91 | if (config->sata_ahci) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 92 | u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 93 | |
| 94 | /* Enable CR memory space decoding */ |
| 95 | reg16 = pci_read_config16(dev, 0x04); |
| 96 | reg16 |= 0x2; |
| 97 | pci_write_config16(dev, 0x04, reg16); |
| 98 | |
| 99 | /* Set capability register */ |
| 100 | reg32 = read32(abar + 0x00); |
| 101 | reg32 |= 0x0c046000; // set PSC+SSC+SALP+SSS+SAM |
| 102 | reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits |
| 103 | reg32 |= (0x3 << 20); // Gen3 SATA |
| 104 | write32(abar + 0x00, reg32); |
| 105 | |
| 106 | /* Ports enabled */ |
| 107 | reg32 = read32(abar + 0x0c); |
| 108 | reg32 &= (u32)(~0x3f); |
| 109 | reg32 |= config->sata_port_map; |
| 110 | write32(abar + 0xc, reg32); |
| 111 | /* Two extra reads to latch */ |
| 112 | read32(abar + 0x0c); |
| 113 | read32(abar + 0x0c); |
| 114 | |
| 115 | /* Set cap2 - Support devslp */ |
| 116 | reg32 = (1 << 5) | (1 << 4) | (1 << 3); |
| 117 | write32(abar + 0x24, reg32); |
| 118 | |
| 119 | /* Set PxCMD registers */ |
| 120 | reg32 = read32(abar + 0x118); |
| 121 | reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | |
| 122 | (1 << 19) | (1 << 18) | (1 << 1)); |
| 123 | reg32 |= 2; |
| 124 | write32(abar + 0x118, reg32); |
| 125 | |
| 126 | reg32 = read32(abar + 0x198); |
| 127 | reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | |
| 128 | (1 << 19) | (1 << 18) | (1 << 1)); |
| 129 | reg32 |= 2; |
| 130 | write32(abar + 0x198, reg32); |
| 131 | |
| 132 | /* Clear reset features */ |
| 133 | write32(abar + 0xc8, 0); |
| 134 | |
| 135 | /* Enable interrupts */ |
| 136 | reg8 = read8(abar + 0x04); |
| 137 | reg8 |= 0x02; |
| 138 | write8(abar + 0x04, reg8); |
| 139 | |
| 140 | } else { |
| 141 | /* TODO(shawnn): Configure IDE SATA speed regs */ |
| 142 | } |
| 143 | |
| 144 | /* 1.4 us delay after configuring port / enable bits */ |
| 145 | udelay(2); |
| 146 | |
| 147 | /* Enable clock for ports */ |
| 148 | reg32 = pci_read_config32(dev, 0x94); |
| 149 | reg32 |= 0x3f << 24; |
| 150 | pci_write_config32(dev, 0x94, reg32); |
| 151 | reg32 &= (config->sata_port_map ^ 0x3) << 24; |
| 152 | pci_write_config32(dev, 0x94, reg32); |
| 153 | |
| 154 | /* Lock SataGc register */ |
| 155 | reg32 = (0x1 << 31) | (0x7 << 12); |
| 156 | pci_write_config32(dev, 0x98, reg32); |
| 157 | } |
| 158 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 159 | static void sata_enable(struct device *dev) |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 160 | { |
| 161 | config_t *config = dev->chip_info; |
| 162 | u8 reg8; |
| 163 | u16 reg16; |
| 164 | u32 reg32; |
| 165 | |
| 166 | southcluster_enable_dev(dev); |
| 167 | if (!config) |
| 168 | return; |
| 169 | |
| 170 | /* Port mapping -- mask off SPD + SMS + SC bits, then re-set */ |
| 171 | reg16 = pci_read_config16(dev, 0x90); |
| 172 | reg16 &= ~0x03e0; |
| 173 | reg16 |= (config->sata_port_map ^ 0x3) << 8; |
Elyes HAOUAS | 4a83f1c | 2016-08-25 21:07:59 +0200 | [diff] [blame] | 174 | if (config->sata_ahci) |
Shawn Nematbakhsh | 1dbd0e2 | 2013-10-28 16:15:02 -0700 | [diff] [blame] | 175 | reg16 |= 0x60; |
| 176 | pci_write_config16(dev, 0x90, reg16); |
| 177 | |
| 178 | /* Set reg 0x94 before starting configuration */ |
| 179 | reg32 = pci_read_config32(dev, 0x94); |
| 180 | reg32 &= (u32)(~0x1ff); |
| 181 | reg32 |= 0x183; |
| 182 | pci_write_config32(dev, 0x94, reg32); |
| 183 | |
| 184 | /* Set ORM bit */ |
| 185 | reg16 = pci_read_config16(dev, 0x92); |
| 186 | reg16 |= (1 << 15); |
| 187 | pci_write_config16(dev, 0x92, reg16); |
| 188 | |
| 189 | /* R_PCH_SATA_TM2 - Undocumented in EDS, set according to ref. code */ |
| 190 | reg32 = pci_read_config32(dev, 0x98); |
| 191 | reg32 &= (u32)~(0x1f80 | (1 << 6) | (1 << 5)); |
| 192 | reg32 |= (1 << 29) | (1 << 25) | (1 << 23) | (1 << 22) | |
| 193 | (1 << 20) | (1 << 19) | (1 << 18) | (1 << 9) | (1 << 5); |
| 194 | pci_write_config32(dev, 0x98, reg32); |
| 195 | |
| 196 | /* CMD reg - set bus master enable (BME) */ |
| 197 | reg8 = pci_read_config8(dev, 0x04); |
| 198 | reg8 |= (1 << 2); |
| 199 | pci_write_config8(dev, 0x04, reg8); |
| 200 | |
| 201 | /* "Test mode registers" */ |
| 202 | sir_write(dev, 0x70, 0x00288301); |
| 203 | sir_write(dev, 0x54, 0x00000300); |
| 204 | sir_write(dev, 0x58, 0x50000000); |
| 205 | /* "OOB Detection Margin */ |
| 206 | sir_write(dev, 0x6c, 0x130C0603); |
| 207 | /* "Gasket Control" */ |
| 208 | sir_write(dev, 0xf4, 0); |
| 209 | |
| 210 | /* PCS - Enable requested SATA ports */ |
| 211 | reg8 = pci_read_config8(dev, 0x92); |
| 212 | reg8 &= ~0x03; |
| 213 | reg8 |= config->sata_port_map; |
| 214 | pci_write_config8(dev, 0x92, reg8); |
| 215 | } |
| 216 | |
| 217 | static struct device_operations sata_ops = { |
| 218 | .read_resources = pci_dev_read_resources, |
| 219 | .set_resources = pci_dev_set_resources, |
| 220 | .enable_resources = pci_dev_enable_resources, |
| 221 | .init = sata_init, |
| 222 | .enable = sata_enable, |
| 223 | .scan_bus = NULL, |
| 224 | .ops_pci = &soc_pci_ops, |
| 225 | }; |
| 226 | |
| 227 | static const unsigned short pci_device_ids[] = { |
| 228 | IDE1_DEVID, IDE2_DEVID, /* IDE */ |
| 229 | AHCI1_DEVID, AHCI2_DEVID, /* AHCI */ |
| 230 | 0, |
| 231 | }; |
| 232 | |
| 233 | static const struct pci_driver baytrail_sata __pci_driver = { |
| 234 | .ops = &sata_ops, |
| 235 | .vendor = PCI_VENDOR_ID_INTEL, |
| 236 | .devices = pci_device_ids, |
| 237 | }; |