Angel Pons | 16f6aa8 | 2020-04-05 15:47:21 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 2 | |
Tim Wawrzynczak | 6d20d0c | 2020-05-13 17:00:33 -0600 | [diff] [blame] | 3 | #include <console/console.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <fsp/api.h> |
| 7 | #include <fsp/util.h> |
| 8 | #include <intelblocks/acpi.h> |
| 9 | #include <intelblocks/cfg.h> |
| 10 | #include <intelblocks/itss.h> |
Caveh Jalali | 7eaac6c | 2020-07-24 21:57:10 -0700 | [diff] [blame] | 11 | #include <intelblocks/pcie_rp.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 12 | #include <intelblocks/xdci.h> |
| 13 | #include <romstage_handoff.h> |
| 14 | #include <soc/intel/common/vbt.h> |
| 15 | #include <soc/itss.h> |
| 16 | #include <soc/pci_devs.h> |
| 17 | #include <soc/ramstage.h> |
| 18 | #include <soc/soc_chip.h> |
| 19 | |
Caveh Jalali | 7eaac6c | 2020-07-24 21:57:10 -0700 | [diff] [blame] | 20 | static const struct pcie_rp_group pch_lp_rp_groups[] = { |
| 21 | { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, |
| 22 | { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, |
| 23 | { 0 } |
| 24 | }; |
| 25 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 26 | #if CONFIG(HAVE_ACPI_TABLES) |
| 27 | const char *soc_acpi_name(const struct device *dev) |
| 28 | { |
| 29 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 30 | return "PCI0"; |
| 31 | |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 32 | if (dev->path.type == DEVICE_PATH_USB) { |
| 33 | switch (dev->path.usb.port_type) { |
| 34 | case 0: |
| 35 | /* Root Hub */ |
| 36 | return "RHUB"; |
| 37 | case 2: |
| 38 | /* USB2 ports */ |
| 39 | switch (dev->path.usb.port_id) { |
| 40 | case 0: return "HS01"; |
| 41 | case 1: return "HS02"; |
| 42 | case 2: return "HS03"; |
| 43 | case 3: return "HS04"; |
| 44 | case 4: return "HS05"; |
| 45 | case 5: return "HS06"; |
| 46 | case 6: return "HS07"; |
| 47 | case 7: return "HS08"; |
| 48 | case 8: return "HS09"; |
| 49 | case 9: return "HS10"; |
| 50 | } |
| 51 | break; |
| 52 | case 3: |
| 53 | /* USB3 ports */ |
| 54 | switch (dev->path.usb.port_id) { |
| 55 | case 0: return "SS01"; |
| 56 | case 1: return "SS02"; |
| 57 | case 2: return "SS03"; |
| 58 | case 3: return "SS04"; |
| 59 | } |
| 60 | break; |
| 61 | } |
| 62 | return NULL; |
| 63 | } |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 64 | if (dev->path.type != DEVICE_PATH_PCI) |
| 65 | return NULL; |
| 66 | |
| 67 | switch (dev->path.pci.devfn) { |
Duncan Laurie | 32585de | 2020-05-18 13:21:44 -0700 | [diff] [blame] | 68 | case SA_DEVFN_ROOT: return "MCHC"; |
Duncan Laurie | 32585de | 2020-05-18 13:21:44 -0700 | [diff] [blame] | 69 | case SA_DEVFN_TCSS_XDCI: return "TXDC"; |
Duncan Laurie | 32585de | 2020-05-18 13:21:44 -0700 | [diff] [blame] | 70 | case SA_DEVFN_TBT0: return "TRP0"; |
| 71 | case SA_DEVFN_TBT1: return "TRP1"; |
| 72 | case SA_DEVFN_TBT2: return "TRP2"; |
| 73 | case SA_DEVFN_TBT3: return "TRP3"; |
Tim Wawrzynczak | 4b74814 | 2020-06-29 12:34:55 -0600 | [diff] [blame] | 74 | case SA_DEVFN_IPU: return "IPU0"; |
Duncan Laurie | 32585de | 2020-05-18 13:21:44 -0700 | [diff] [blame] | 75 | case PCH_DEVFN_ISH: return "ISHB"; |
| 76 | case PCH_DEVFN_XHCI: return "XHCI"; |
| 77 | case PCH_DEVFN_I2C0: return "I2C0"; |
| 78 | case PCH_DEVFN_I2C1: return "I2C1"; |
| 79 | case PCH_DEVFN_I2C2: return "I2C2"; |
| 80 | case PCH_DEVFN_I2C3: return "I2C3"; |
| 81 | case PCH_DEVFN_I2C4: return "I2C4"; |
| 82 | case PCH_DEVFN_I2C5: return "I2C5"; |
| 83 | case PCH_DEVFN_SATA: return "SATA"; |
| 84 | case PCH_DEVFN_PCIE1: return "RP01"; |
| 85 | case PCH_DEVFN_PCIE2: return "RP02"; |
| 86 | case PCH_DEVFN_PCIE3: return "RP03"; |
| 87 | case PCH_DEVFN_PCIE4: return "RP04"; |
| 88 | case PCH_DEVFN_PCIE5: return "RP05"; |
| 89 | case PCH_DEVFN_PCIE6: return "RP06"; |
| 90 | case PCH_DEVFN_PCIE7: return "RP07"; |
| 91 | case PCH_DEVFN_PCIE8: return "RP08"; |
| 92 | case PCH_DEVFN_PCIE9: return "RP09"; |
| 93 | case PCH_DEVFN_PCIE10: return "RP10"; |
| 94 | case PCH_DEVFN_PCIE11: return "RP11"; |
| 95 | case PCH_DEVFN_PCIE12: return "RP12"; |
| 96 | case PCH_DEVFN_PMC: return "PMC"; |
| 97 | case PCH_DEVFN_UART0: return "UAR0"; |
| 98 | case PCH_DEVFN_UART1: return "UAR1"; |
| 99 | case PCH_DEVFN_UART2: return "UAR2"; |
| 100 | case PCH_DEVFN_GSPI0: return "SPI0"; |
| 101 | case PCH_DEVFN_GSPI1: return "SPI1"; |
| 102 | case PCH_DEVFN_GSPI2: return "SPI2"; |
| 103 | case PCH_DEVFN_GSPI3: return "SPI3"; |
Duncan Laurie | 32585de | 2020-05-18 13:21:44 -0700 | [diff] [blame] | 104 | case PCH_DEVFN_HDA: return "HDAS"; |
| 105 | case PCH_DEVFN_SMBUS: return "SBUS"; |
| 106 | case PCH_DEVFN_GBE: return "GLAN"; |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 107 | } |
| 108 | |
| 109 | return NULL; |
| 110 | } |
| 111 | #endif |
| 112 | |
| 113 | /* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ |
| 114 | static void soc_fill_gpio_pm_configuration(void) |
| 115 | { |
| 116 | uint8_t value[TOTAL_GPIO_COMM]; |
| 117 | const config_t *config = config_of_soc(); |
| 118 | |
| 119 | if (config->gpio_override_pm) |
| 120 | memcpy(value, config->gpio_pm, sizeof(uint8_t) * |
| 121 | TOTAL_GPIO_COMM); |
| 122 | else |
| 123 | memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * |
| 124 | TOTAL_GPIO_COMM); |
| 125 | |
| 126 | gpio_pm_configure(value, TOTAL_GPIO_COMM); |
| 127 | } |
| 128 | |
| 129 | void soc_init_pre_device(void *chip_info) |
| 130 | { |
| 131 | /* Snapshot the current GPIO IRQ polarities. FSP is setting a |
| 132 | * default policy that doesn't honor boards' requirements. */ |
| 133 | itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 134 | |
| 135 | /* Perform silicon specific init. */ |
| 136 | fsp_silicon_init(romstage_handoff_is_resume()); |
| 137 | |
| 138 | /* Display FIRMWARE_VERSION_INFO_HOB */ |
| 139 | fsp_display_fvi_version_hob(); |
| 140 | |
| 141 | /* Restore GPIO IRQ polarities back to previous settings. */ |
| 142 | itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 143 | |
| 144 | soc_fill_gpio_pm_configuration(); |
Caveh Jalali | 7eaac6c | 2020-07-24 21:57:10 -0700 | [diff] [blame] | 145 | |
| 146 | /* Swap enabled PCI ports in device tree if needed. */ |
| 147 | pcie_rp_update_devicetree(pch_lp_rp_groups); |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 148 | } |
| 149 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 150 | static struct device_operations pci_domain_ops = { |
| 151 | .read_resources = &pci_domain_read_resources, |
| 152 | .set_resources = &pci_domain_set_resources, |
| 153 | .scan_bus = &pci_domain_scan_bus, |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 154 | #if CONFIG(HAVE_ACPI_TABLES) |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 155 | .acpi_name = &soc_acpi_name, |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 156 | #endif |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 157 | }; |
| 158 | |
| 159 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 160 | .read_resources = noop_read_resources, |
| 161 | .set_resources = noop_set_resources, |
Karthikeyan Ramasubramanian | 0e971e1 | 2020-01-09 11:32:16 -0700 | [diff] [blame] | 162 | #if CONFIG(HAVE_ACPI_TABLES) |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 163 | .acpi_fill_ssdt = generate_cpu_entries, |
Karthikeyan Ramasubramanian | 0e971e1 | 2020-01-09 11:32:16 -0700 | [diff] [blame] | 164 | #endif |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 165 | }; |
| 166 | |
| 167 | static void soc_enable(struct device *dev) |
| 168 | { |
Tim Wawrzynczak | 6d20d0c | 2020-05-13 17:00:33 -0600 | [diff] [blame] | 169 | /* |
| 170 | * Set the operations if it is a special bus type or a hidden PCI |
| 171 | * device. |
| 172 | */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 173 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 174 | dev->ops = &pci_domain_ops; |
| 175 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 176 | dev->ops = &cpu_bus_ops; |
Tim Wawrzynczak | 6d20d0c | 2020-05-13 17:00:33 -0600 | [diff] [blame] | 177 | else if (dev->path.type == DEVICE_PATH_PCI && |
| 178 | dev->path.pci.devfn == PCH_DEVFN_PMC) |
| 179 | dev->ops = &pmc_ops; |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | struct chip_operations soc_intel_tigerlake_ops = { |
| 183 | CHIP_NAME("Intel Tigerlake") |
| 184 | .enable_dev = &soc_enable, |
| 185 | .init = &soc_init_pre_device, |
| 186 | }; |