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review.coreboot.org / coreboot / 979a071b0e3b5a3e578a25f1553a3a32f618d4b2 / . / src / soc / intel / alderlake / chip.c
blob: 794c3bae0f225309e9ba358bb56999717ba604d2 [file] [log] [blame]
Subrata Banik2871e0e2020-09-27 11:30:58 +0530[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <device/device.h>
4#include <device/pci.h>
5#include <fsp/api.h>
6#include <fsp/util.h>
7#include <intelblocks/acpi.h>
8#include <intelblocks/cfg.h>
9#include <intelblocks/itss.h>
10#include <intelblocks/pcie_rp.h>
11#include <intelblocks/xdci.h>
12#include <romstage_handoff.h>
13#include <soc/intel/common/vbt.h>
14#include <soc/itss.h>
15#include <soc/pci_devs.h>
16#include <soc/ramstage.h>
17#include <soc/soc_chip.h>
18
19static const struct pcie_rp_group pch_lp_rp_groups[] = {
20 { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
21 { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 },
22 { 0 }
23};
24
25#if CONFIG(HAVE_ACPI_TABLES)
26const char *soc_acpi_name(const struct device *dev)
27{
28 if (dev->path.type == DEVICE_PATH_DOMAIN)
29 return "PCI0";
30
31 if (dev->path.type == DEVICE_PATH_USB) {
32 switch (dev->path.usb.port_type) {
33 case 0:
34 /* Root Hub */
35 return "RHUB";
36 case 2:
37 /* USB2 ports */
38 switch (dev->path.usb.port_id) {
39 case 0: return "HS01";
40 case 1: return "HS02";
41 case 2: return "HS03";
42 case 3: return "HS04";
43 case 4: return "HS05";
44 case 5: return "HS06";
45 case 6: return "HS07";
46 case 7: return "HS08";
47 case 8: return "HS09";
48 case 9: return "HS10";
49 }
50 break;
51 case 3:
52 /* USB3 ports */
53 switch (dev->path.usb.port_id) {
54 case 0: return "SS01";
55 case 1: return "SS02";
56 case 2: return "SS03";
57 case 3: return "SS04";
58 }
59 break;
60 }
61 return NULL;
62 }
63 if (dev->path.type != DEVICE_PATH_PCI)
64 return NULL;
65
66 switch (dev->path.pci.devfn) {
67 case SA_DEVFN_ROOT: return "MCHC";
68 case SA_DEVFN_TCSS_XHCI: return "TXHC";
69 case SA_DEVFN_TCSS_XDCI: return "TXDC";
70 case SA_DEVFN_TCSS_DMA0: return "TDM0";
71 case SA_DEVFN_TCSS_DMA1: return "TDM1";
72 case SA_DEVFN_TBT0: return "TRP0";
73 case SA_DEVFN_TBT1: return "TRP1";
74 case SA_DEVFN_TBT2: return "TRP2";
75 case SA_DEVFN_TBT3: return "TRP3";
76 case SA_DEVFN_IPU: return "IPU0";
77 case PCH_DEVFN_ISH: return "ISHB";
78 case PCH_DEVFN_XHCI: return "XHCI";
79 case PCH_DEVFN_I2C0: return "I2C0";
80 case PCH_DEVFN_I2C1: return "I2C1";
81 case PCH_DEVFN_I2C2: return "I2C2";
82 case PCH_DEVFN_I2C3: return "I2C3";
83 case PCH_DEVFN_I2C4: return "I2C4";
84 case PCH_DEVFN_I2C5: return "I2C5";
85 case PCH_DEVFN_SATA: return "SATA";
86 case PCH_DEVFN_PCIE1: return "RP01";
87 case PCH_DEVFN_PCIE2: return "RP02";
88 case PCH_DEVFN_PCIE3: return "RP03";
89 case PCH_DEVFN_PCIE4: return "RP04";
90 case PCH_DEVFN_PCIE5: return "RP05";
91 case PCH_DEVFN_PCIE6: return "RP06";
92 case PCH_DEVFN_PCIE7: return "RP07";
93 case PCH_DEVFN_PCIE8: return "RP08";
94 case PCH_DEVFN_PCIE9: return "RP09";
95 case PCH_DEVFN_PCIE10: return "RP10";
96 case PCH_DEVFN_PCIE11: return "RP11";
97 case PCH_DEVFN_PCIE12: return "RP12";
98 case PCH_DEVFN_PMC: return "PMC";
99 case PCH_DEVFN_UART0: return "UAR0";
100 case PCH_DEVFN_UART1: return "UAR1";
101 case PCH_DEVFN_UART2: return "UAR2";
102 case PCH_DEVFN_GSPI0: return "SPI0";
103 case PCH_DEVFN_GSPI1: return "SPI1";
104 case PCH_DEVFN_GSPI2: return "SPI2";
105 case PCH_DEVFN_GSPI3: return "SPI3";
106 /* Keeping ACPI device name coherent with ec.asl */
107 case PCH_DEVFN_ESPI: return "LPCB";
108 case PCH_DEVFN_HDA: return "HDAS";
109 case PCH_DEVFN_SMBUS: return "SBUS";
110 case PCH_DEVFN_GBE: return "GLAN";
111 }
112
113 return NULL;
114}
115#endif
116
117/* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */
118static void soc_fill_gpio_pm_configuration(void)
119{
120 uint8_t value[TOTAL_GPIO_COMM];
121 const config_t *config = config_of_soc();
122
123 if (config->gpio_override_pm)
124 memcpy(value, config->gpio_pm, sizeof(uint8_t) *
125 TOTAL_GPIO_COMM);
126 else
127 memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
128 TOTAL_GPIO_COMM);
129
130 gpio_pm_configure(value, TOTAL_GPIO_COMM);
131}
132
133void soc_init_pre_device(void *chip_info)
134{
135 /* TODO: A bug has been filed, remove this W/A once FSP is updated */
136 /* Snapshot the current GPIO IRQ polarities. FSP is setting a
137 * default policy that doesn't honor boards' requirements. */
138 itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
139
140 /* Perform silicon specific init. */
141 fsp_silicon_init(romstage_handoff_is_resume());
142
143 /* Display FIRMWARE_VERSION_INFO_HOB */
144 fsp_display_fvi_version_hob();
145
146 /* Restore GPIO IRQ polarities back to previous settings. */
147 itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
148
149 soc_fill_gpio_pm_configuration();
150
151 /* Swap enabled PCI ports in device tree if needed. */
152 pcie_rp_update_devicetree(pch_lp_rp_groups);
153}
154
155static struct device_operations pci_domain_ops = {
156 .read_resources = &pci_domain_read_resources,
157 .set_resources = &pci_domain_set_resources,
158 .scan_bus = &pci_domain_scan_bus,
159#if CONFIG(HAVE_ACPI_TABLES)
160 .acpi_name = &soc_acpi_name,
161#endif
162};
163
164static struct device_operations cpu_bus_ops = {
165 .read_resources = noop_read_resources,
166 .set_resources = noop_set_resources,
167#if CONFIG(HAVE_ACPI_TABLES)
168 .acpi_fill_ssdt = generate_cpu_entries,
169#endif
170};
171
172static void soc_enable(struct device *dev)
173{
174 /*
175 * Set the operations if it is a special bus type or a hidden PCI
176 * device.
177 */
178 if (dev->path.type == DEVICE_PATH_DOMAIN)
179 dev->ops = &pci_domain_ops;
180 else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
181 dev->ops = &cpu_bus_ops;
182 else if (dev->path.type == DEVICE_PATH_PCI &&
183 dev->path.pci.devfn == PCH_DEVFN_PMC)
184 dev->ops = &pmc_ops;
185}
186
187struct chip_operations soc_intel_alderlake_ops = {
188 CHIP_NAME("Intel Alderlake")
189 .enable_dev = &soc_enable,
190 .init = &soc_init_pre_device,
191};