Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <acpi/acpi_ivrs.h> |
| 4 | #include <amdblocks/acpi.h> |
| 5 | #include <amdblocks/cpu.h> |
| 6 | #include <amdblocks/data_fabric.h> |
| 7 | #include <amdblocks/ioapic.h> |
Felix Held | 96fa6a2 | 2022-12-06 01:25:13 +0100 | [diff] [blame] | 8 | #include <arch/ioapic.h> |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 9 | #include <arch/mmio.h> |
| 10 | #include <console/console.h> |
| 11 | #include <cpu/amd/cpuid.h> |
| 12 | #include <cpu/amd/msr.h> |
| 13 | #include <device/device.h> |
| 14 | #include <device/pci_def.h> |
| 15 | #include <device/pci_ops.h> |
| 16 | #include <soc/acpi.h> |
| 17 | #include <soc/data_fabric.h> |
Felix Held | 96fa6a2 | 2022-12-06 01:25:13 +0100 | [diff] [blame] | 18 | #include <soc/iomap.h> |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 19 | #include <soc/pci_devs.h> |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 20 | |
| 21 | #define MAX_DEV_ID 0xFFFF |
| 22 | |
| 23 | unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) |
| 24 | { |
| 25 | ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
| 26 | memset(ivhd_ioapic, 0, sizeof(*ivhd_ioapic)); |
| 27 | |
| 28 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 29 | ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | |
| 30 | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | |
| 31 | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; |
Felix Held | 96fa6a2 | 2022-12-06 01:25:13 +0100 | [diff] [blame] | 32 | ivhd_ioapic->handle = get_ioapic_id(VIO_APIC_VADDR); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 33 | ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 34 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 35 | current += sizeof(ivrs_ivhd_special_t); |
| 36 | |
| 37 | ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
| 38 | memset(ivhd_ioapic, 0, sizeof(*ivhd_ioapic)); |
| 39 | |
| 40 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
Felix Held | 96fa6a2 | 2022-12-06 01:25:13 +0100 | [diff] [blame] | 41 | ivhd_ioapic->handle = get_ioapic_id((u8 *)GNB_IO_APIC_ADDR); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 42 | ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); |
| 43 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 44 | current += sizeof(ivrs_ivhd_special_t); |
| 45 | |
| 46 | return current; |
| 47 | } |
| 48 | |
| 49 | static unsigned long ivhd_describe_hpet(unsigned long current) |
| 50 | { |
| 51 | ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; |
| 52 | |
| 53 | ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 54 | ivhd_hpet->reserved = 0x0000; |
| 55 | ivhd_hpet->dte_setting = 0x00; |
| 56 | ivhd_hpet->handle = 0x00; |
| 57 | ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 58 | ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; |
| 59 | current += sizeof(ivrs_ivhd_special_t); |
| 60 | |
| 61 | return current; |
| 62 | } |
| 63 | |
| 64 | static unsigned long ivhd_describe_f0_device(unsigned long current, |
| 65 | uint16_t dev_id, uint8_t datasetting) |
| 66 | { |
Elyes Haouas | 68fc51f | 2022-07-16 09:48:27 +0200 | [diff] [blame] | 67 | ivrs_ivhd_f0_entry_t *ivhd_f0 = (ivrs_ivhd_f0_entry_t *)current; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 68 | |
| 69 | ivhd_f0->type = IVHD_DEV_VARIABLE; |
| 70 | ivhd_f0->dev_id = dev_id; |
| 71 | ivhd_f0->dte_setting = datasetting; |
| 72 | ivhd_f0->hardware_id[0] = 'A'; |
| 73 | ivhd_f0->hardware_id[1] = 'M'; |
| 74 | ivhd_f0->hardware_id[2] = 'D'; |
| 75 | ivhd_f0->hardware_id[3] = 'I'; |
| 76 | ivhd_f0->hardware_id[4] = '0'; |
| 77 | ivhd_f0->hardware_id[5] = '0'; |
| 78 | ivhd_f0->hardware_id[6] = '4'; |
| 79 | ivhd_f0->hardware_id[7] = '0'; |
| 80 | |
| 81 | memset(ivhd_f0->compatible_id, 0, sizeof(ivhd_f0->compatible_id)); |
| 82 | |
| 83 | ivhd_f0->uuid_format = 0; |
| 84 | ivhd_f0->uuid_length = 0; |
| 85 | |
| 86 | current += sizeof(ivrs_ivhd_f0_entry_t); |
| 87 | return current; |
| 88 | } |
| 89 | |
| 90 | static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, |
| 91 | uint16_t end_devid, uint8_t setting) |
| 92 | { |
| 93 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 94 | current = ALIGN_UP(current, 4); |
| 95 | ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 96 | |
| 97 | /* Create the start range IVHD entry */ |
| 98 | ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; |
| 99 | ivhd_range->dev_id = start_devid; |
| 100 | ivhd_range->dte_setting = setting; |
| 101 | current += sizeof(ivrs_ivhd_generic_t); |
| 102 | |
| 103 | /* Create the end range IVHD entry */ |
| 104 | ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 105 | ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; |
| 106 | ivhd_range->dev_id = end_devid; |
| 107 | ivhd_range->dte_setting = setting; |
| 108 | current += sizeof(ivrs_ivhd_generic_t); |
| 109 | |
| 110 | return current; |
| 111 | } |
| 112 | |
| 113 | static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *dev, |
| 114 | unsigned long *current, uint8_t type, uint8_t data) |
| 115 | { |
| 116 | if (type == IVHD_DEV_4_BYTE_SELECT) { |
| 117 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 118 | *current = ALIGN_UP(*current, 4); |
| 119 | ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; |
| 120 | |
| 121 | ivhd_entry->type = type; |
| 122 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 123 | ivhd_entry->dte_setting = data; |
| 124 | *current += sizeof(ivrs_ivhd_generic_t); |
| 125 | } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { |
| 126 | ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; |
| 127 | |
| 128 | ivhd_entry->type = type; |
| 129 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 130 | ivhd_entry->dte_setting = data; |
| 131 | ivhd_entry->reserved1 = 0; |
| 132 | ivhd_entry->reserved2 = 0; |
| 133 | ivhd_entry->source_dev_id = parent->path.pci.devfn | |
| 134 | (parent->bus->secondary << 8); |
| 135 | *current += sizeof(ivrs_ivhd_alias_t); |
| 136 | } |
| 137 | |
| 138 | return *current; |
| 139 | } |
| 140 | |
| 141 | static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, |
| 142 | unsigned long *current, uint16_t *ivhd_length) |
| 143 | { |
| 144 | unsigned int header_type, is_pcie; |
| 145 | unsigned long current_backup; |
| 146 | |
| 147 | header_type = dev->hdr_type & 0x7f; |
| 148 | is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
| 149 | |
| 150 | if (((header_type == PCI_HEADER_TYPE_NORMAL) || |
| 151 | (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { |
| 152 | /* Device or Bridge is PCIe */ |
| 153 | current_backup = *current; |
| 154 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_4_BYTE_SELECT, 0x0); |
| 155 | *ivhd_length += (*current - current_backup); |
| 156 | } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { |
| 157 | /* Device is legacy PCI or PCI-X */ |
| 158 | current_backup = *current; |
| 159 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); |
| 160 | *ivhd_length += (*current - current_backup); |
| 161 | } |
| 162 | } |
| 163 | |
| 164 | static void add_ivhd_device_entries(struct device *parent, struct device *dev, |
| 165 | unsigned int depth, int linknum, int8_t *root_level, |
| 166 | unsigned long *current, uint16_t *ivhd_length) |
| 167 | { |
| 168 | struct device *sibling; |
| 169 | struct bus *link; |
| 170 | |
| 171 | if (!root_level) |
| 172 | return; |
| 173 | |
| 174 | if (dev->path.type == DEVICE_PATH_PCI) { |
| 175 | if ((dev->bus->secondary == 0x0) && |
| 176 | (dev->path.pci.devfn == 0x0)) |
| 177 | *root_level = depth; |
| 178 | |
| 179 | if ((*root_level != -1) && (dev->enabled)) { |
| 180 | if (depth != *root_level) |
| 181 | ivrs_add_device_or_bridge(parent, dev, current, ivhd_length); |
| 182 | } |
| 183 | } |
| 184 | |
| 185 | for (link = dev->link_list; link; link = link->next) |
| 186 | for (sibling = link->children; sibling; sibling = |
| 187 | sibling->sibling) |
| 188 | add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, |
| 189 | current, ivhd_length); |
| 190 | } |
| 191 | |
| 192 | static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_t *ivrs) |
| 193 | { |
| 194 | acpi_ivrs_ivhd40_t *ivhd_40; |
| 195 | unsigned long current_backup; |
| 196 | int8_t root_level; |
| 197 | |
| 198 | /* |
| 199 | * These devices should be already found by previous function. |
| 200 | * Do not perform NULL checks. |
| 201 | */ |
| 202 | struct device *nb_dev = pcidev_on_root(0, 0); |
| 203 | struct device *iommu_dev = pcidev_on_root(0, 2); |
| 204 | |
| 205 | memset((void *)current, 0, sizeof(acpi_ivrs_ivhd40_t)); |
| 206 | ivhd_40 = (acpi_ivrs_ivhd40_t *)current; |
| 207 | |
| 208 | /* Enable EFR */ |
| 209 | ivhd_40->type = IVHD_BLOCK_TYPE_FULL__ACPI_HID; |
| 210 | /* For type 40h bits 6 and 7 are reserved */ |
| 211 | ivhd_40->flags = ivrs->ivhd.flags & 0x3f; |
| 212 | ivhd_40->length = sizeof(struct acpi_ivrs_ivhd_40); |
| 213 | /* BDF <bus>:00.2 */ |
| 214 | ivhd_40->device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 215 | ivhd_40->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); |
| 216 | ivhd_40->iommu_base_low = ivrs->ivhd.iommu_base_low; |
| 217 | ivhd_40->iommu_base_high = ivrs->ivhd.iommu_base_high; |
| 218 | ivhd_40->pci_segment_group = 0x0000; |
| 219 | ivhd_40->iommu_info = ivrs->ivhd.iommu_info; |
| 220 | /* For type 40h bits 31:28 and 12:0 are reserved */ |
| 221 | ivhd_40->iommu_attributes = ivrs->ivhd.iommu_feature_info & 0xfffe000; |
| 222 | |
| 223 | if (pci_read_config32(iommu_dev, ivhd_40->capability_offset) & EFR_FEATURE_SUP) { |
Arthur Heymans | 4c68487 | 2022-04-19 21:44:22 +0200 | [diff] [blame] | 224 | ivhd_40->efr_reg_image_low = read32p(ivhd_40->iommu_base_low + 0x30); |
| 225 | ivhd_40->efr_reg_image_high = read32p(ivhd_40->iommu_base_low + 0x34); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | current += sizeof(acpi_ivrs_ivhd40_t); |
| 229 | |
| 230 | /* Now repeat all the device entries from type 10h */ |
| 231 | current_backup = current; |
| 232 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), MAX_DEV_ID, 0); |
| 233 | ivhd_40->length += (current - current_backup); |
| 234 | root_level = -1; |
| 235 | add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, |
| 236 | ¤t, &ivhd_40->length); |
| 237 | |
| 238 | /* Describe HPET */ |
| 239 | current_backup = current; |
| 240 | current = ivhd_describe_hpet(current); |
| 241 | ivhd_40->length += (current - current_backup); |
| 242 | |
| 243 | /* Describe IOAPICs */ |
| 244 | current_backup = current; |
| 245 | current = acpi_fill_ivrs_ioapic(ivrs, current); |
| 246 | ivhd_40->length += (current - current_backup); |
| 247 | |
| 248 | /* Describe EMMC */ |
| 249 | current_backup = current; |
| 250 | current = ivhd_describe_f0_device(current, PCI_DEVFN(0x13, 1), |
| 251 | IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | |
| 252 | IVHD_DTE_SYS_MGT_TRANS | IVHD_DTE_NMI_PASS | |
| 253 | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS); |
| 254 | ivhd_40->length += (current - current_backup); |
| 255 | |
| 256 | return current; |
| 257 | } |
| 258 | |
| 259 | static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs) |
| 260 | { |
| 261 | acpi_ivrs_ivhd11_t *ivhd_11; |
| 262 | ivhd11_iommu_attr_t *ivhd11_attr_ptr; |
| 263 | unsigned long current_backup; |
| 264 | int8_t root_level; |
| 265 | |
| 266 | /* |
| 267 | * These devices should be already found by previous function. |
| 268 | * Do not perform NULL checks. |
| 269 | */ |
| 270 | struct device *nb_dev = pcidev_on_root(0, 0); |
| 271 | struct device *iommu_dev = pcidev_on_root(0, 2); |
| 272 | |
| 273 | /* |
| 274 | * In order to utilize all features, firmware should expose type 11h |
| 275 | * IVHD which supersedes the type 10h. |
| 276 | */ |
| 277 | memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); |
| 278 | ivhd_11 = (acpi_ivrs_ivhd11_t *)current; |
| 279 | |
| 280 | /* Enable EFR */ |
| 281 | ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; |
| 282 | /* For type 11h bits 6 and 7 are reserved */ |
| 283 | ivhd_11->flags = ivrs->ivhd.flags & 0x3f; |
| 284 | ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); |
| 285 | /* BDF <bus>:00.2 */ |
| 286 | ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 287 | ivhd_11->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); |
| 288 | ivhd_11->iommu_base_low = ivrs->ivhd.iommu_base_low; |
| 289 | ivhd_11->iommu_base_high = ivrs->ivhd.iommu_base_high; |
| 290 | ivhd_11->pci_segment_group = 0x0000; |
| 291 | ivhd_11->iommu_info = ivrs->ivhd.iommu_info; |
Elyes Haouas | 68fc51f | 2022-07-16 09:48:27 +0200 | [diff] [blame] | 292 | ivhd11_attr_ptr = (ivhd11_iommu_attr_t *)&ivrs->ivhd.iommu_feature_info; |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 293 | ivhd_11->iommu_attributes.perf_counters = ivhd11_attr_ptr->perf_counters; |
| 294 | ivhd_11->iommu_attributes.perf_counter_banks = ivhd11_attr_ptr->perf_counter_banks; |
| 295 | ivhd_11->iommu_attributes.msi_num_ppr = ivhd11_attr_ptr->msi_num_ppr; |
| 296 | |
| 297 | if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_FEATURE_SUP) { |
Arthur Heymans | 4c68487 | 2022-04-19 21:44:22 +0200 | [diff] [blame] | 298 | ivhd_11->efr_reg_image_low = read32p(ivhd_11->iommu_base_low + 0x30); |
| 299 | ivhd_11->efr_reg_image_high = read32p(ivhd_11->iommu_base_low + 0x34); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 300 | } |
| 301 | |
| 302 | current += sizeof(acpi_ivrs_ivhd11_t); |
| 303 | |
| 304 | /* Now repeat all the device entries from type 10h */ |
| 305 | current_backup = current; |
| 306 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), MAX_DEV_ID, 0); |
| 307 | ivhd_11->length += (current - current_backup); |
| 308 | root_level = -1; |
| 309 | add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, |
| 310 | ¤t, &ivhd_11->length); |
| 311 | |
| 312 | /* Describe HPET */ |
| 313 | current_backup = current; |
| 314 | current = ivhd_describe_hpet(current); |
| 315 | ivhd_11->length += (current - current_backup); |
| 316 | |
| 317 | /* Describe IOAPICs */ |
| 318 | current_backup = current; |
| 319 | current = acpi_fill_ivrs_ioapic(ivrs, current); |
| 320 | ivhd_11->length += (current - current_backup); |
| 321 | |
| 322 | return acpi_fill_ivrs40(current, ivrs); |
| 323 | } |
| 324 | |
| 325 | unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) |
| 326 | { |
| 327 | unsigned long current_backup; |
| 328 | uint64_t mmio_x30_value; |
| 329 | uint64_t mmio_x18_value; |
| 330 | uint64_t mmio_x4000_value; |
| 331 | uint32_t cap_offset_0; |
| 332 | uint32_t cap_offset_10; |
| 333 | int8_t root_level; |
| 334 | |
| 335 | struct device *iommu_dev; |
| 336 | struct device *nb_dev; |
| 337 | |
| 338 | nb_dev = pcidev_on_root(0, 0); |
| 339 | if (!nb_dev) { |
| 340 | printk(BIOS_WARNING, "%s: Northbridge device not present!\n", __func__); |
| 341 | printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); |
| 342 | |
| 343 | return (unsigned long)ivrs; |
| 344 | } |
| 345 | |
| 346 | iommu_dev = pcidev_on_root(0, 2); |
| 347 | if (!iommu_dev) { |
| 348 | printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); |
| 349 | |
| 350 | return (unsigned long)ivrs; |
| 351 | } |
| 352 | |
| 353 | if (ivrs != NULL) { |
| 354 | ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; |
| 355 | ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); |
| 356 | |
| 357 | /* BDF <bus>:00.2 */ |
| 358 | ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 359 | ivrs->ivhd.capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); |
| 360 | ivrs->ivhd.iommu_base_low = pci_read_config32(iommu_dev, 0x44) & 0xffffc000; |
| 361 | ivrs->ivhd.iommu_base_high = pci_read_config32(iommu_dev, 0x48); |
| 362 | |
| 363 | cap_offset_0 = pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset); |
| 364 | cap_offset_10 = pci_read_config32(iommu_dev, |
| 365 | ivrs->ivhd.capability_offset + 0x10); |
Arthur Heymans | 4c68487 | 2022-04-19 21:44:22 +0200 | [diff] [blame] | 366 | mmio_x18_value = read64p(ivrs->ivhd.iommu_base_low + 0x18); |
| 367 | mmio_x30_value = read64p(ivrs->ivhd.iommu_base_low + 0x30); |
| 368 | mmio_x4000_value = read64p(ivrs->ivhd.iommu_base_low + 0x4000); |
Jason Glenesk | f934fae | 2021-07-20 02:19:58 -0700 | [diff] [blame] | 369 | |
| 370 | ivrs->ivhd.flags |= ((mmio_x30_value & MMIO_EXT_FEATURE_PPR_SUP) ? |
| 371 | IVHD_FLAG_PPE_SUP : 0); |
| 372 | ivrs->ivhd.flags |= ((mmio_x30_value & MMIO_EXT_FEATURE_PRE_F_SUP) ? |
| 373 | IVHD_FLAG_PREF_SUP : 0); |
| 374 | ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_COHERENT) ? |
| 375 | IVHD_FLAG_COHERENT : 0); |
| 376 | ivrs->ivhd.flags |= ((cap_offset_0 & CAP_OFFSET_0_IOTLB_SP) ? |
| 377 | IVHD_FLAG_IOTLB_SUP : 0); |
| 378 | ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_ISOC) ? |
| 379 | IVHD_FLAG_ISOC : 0); |
| 380 | ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_RES_PASS_PW) ? |
| 381 | IVHD_FLAG_RES_PASS_PW : 0); |
| 382 | ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_PASS_PW) ? |
| 383 | IVHD_FLAG_PASS_PW : 0); |
| 384 | ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_CTRL_HT_TUN_EN) ? |
| 385 | IVHD_FLAG_HT_TUN_EN : 0); |
| 386 | |
| 387 | ivrs->ivhd.pci_segment_group = 0x0000; |
| 388 | |
| 389 | ivrs->ivhd.iommu_info = pci_read_config16(iommu_dev, |
| 390 | ivrs->ivhd.capability_offset + 0x10) & 0x1F; |
| 391 | ivrs->ivhd.iommu_info |= (pci_read_config16(iommu_dev, |
| 392 | ivrs->ivhd.capability_offset + 0xC) & 0x1F) << IOMMU_INFO_UNIT_ID_SHIFT; |
| 393 | |
| 394 | ivrs->ivhd.iommu_feature_info = 0; |
| 395 | ivrs->ivhd.iommu_feature_info |= (mmio_x30_value & MMIO_EXT_FEATURE_HATS_MASK) |
| 396 | << (IOMMU_FEATURE_HATS_SHIFT - MMIO_EXT_FEATURE_HATS_SHIFT); |
| 397 | |
| 398 | ivrs->ivhd.iommu_feature_info |= (mmio_x30_value & MMIO_EXT_FEATURE_GATS_MASK) |
| 399 | << (IOMMU_FEATURE_GATS_SHIFT - MMIO_EXT_FEATURE_GATS_SHIFT); |
| 400 | |
| 401 | ivrs->ivhd.iommu_feature_info |= (cap_offset_10 & CAP_OFFSET_10_MSI_NUM_PPR) |
| 402 | >> (CAP_OFFSET_10_MSI_NUM_PPR_SHIFT |
| 403 | - IOMMU_FEATURE_MSI_NUM_PPR_SHIFT); |
| 404 | |
| 405 | ivrs->ivhd.iommu_feature_info |= (mmio_x4000_value & |
| 406 | MMIO_CNT_CFG_N_COUNTER_BANKS) |
| 407 | << (IOMMU_FEATURE_PN_BANKS_SHIFT - MMIO_CNT_CFG_N_CNT_BANKS_SHIFT); |
| 408 | |
| 409 | ivrs->ivhd.iommu_feature_info |= (mmio_x4000_value & MMIO_CNT_CFG_N_COUNTER) |
| 410 | << (IOMMU_FEATURE_PN_COUNTERS_SHIFT - MMIO_CNT_CFG_N_COUNTER_SHIFT); |
| 411 | ivrs->ivhd.iommu_feature_info |= (mmio_x30_value & |
| 412 | MMIO_EXT_FEATURE_PAS_MAX_MASK) |
| 413 | >> (MMIO_EXT_FEATURE_PAS_MAX_SHIFT - IOMMU_FEATURE_PA_SMAX_SHIFT); |
| 414 | ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_HE_SUP) |
| 415 | ? IOMMU_FEATURE_HE_SUP : 0); |
| 416 | ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_GA_SUP) |
| 417 | ? IOMMU_FEATURE_GA_SUP : 0); |
| 418 | ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_IA_SUP) |
| 419 | ? IOMMU_FEATURE_IA_SUP : 0); |
| 420 | ivrs->ivhd.iommu_feature_info |= (mmio_x30_value & |
| 421 | MMIO_EXT_FEATURE_GLX_SUP_MASK) |
| 422 | >> (MMIO_EXT_FEATURE_GLX_SHIFT - IOMMU_FEATURE_GLX_SHIFT); |
| 423 | ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_GT_SUP) |
| 424 | ? IOMMU_FEATURE_GT_SUP : 0); |
| 425 | ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_NX_SUP) |
| 426 | ? IOMMU_FEATURE_NX_SUP : 0); |
| 427 | ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_EXT_FEATURE_XT_SUP) |
| 428 | ? IOMMU_FEATURE_XT_SUP : 0); |
| 429 | |
| 430 | /* Enable EFR if supported */ |
| 431 | ivrs->iv_info = pci_read_config32(iommu_dev, |
| 432 | ivrs->ivhd.capability_offset + 0x10) & 0x007fffe0; |
| 433 | if (pci_read_config32(iommu_dev, |
| 434 | ivrs->ivhd.capability_offset) & EFR_FEATURE_SUP) |
| 435 | ivrs->iv_info |= IVINFO_EFR_SUPPORTED; |
| 436 | |
| 437 | } else { |
| 438 | printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); |
| 439 | |
| 440 | return (unsigned long)ivrs; |
| 441 | } |
| 442 | |
| 443 | /* |
| 444 | * Add all possible PCI devices that can generate transactions |
| 445 | * processed by IOMMU. Start with device 00:01.0 |
| 446 | */ |
| 447 | current_backup = current; |
| 448 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), MAX_DEV_ID, 0); |
| 449 | ivrs->ivhd.length += (current - current_backup); |
| 450 | root_level = -1; |
| 451 | add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, |
| 452 | ¤t, &ivrs->ivhd.length); |
| 453 | |
| 454 | /* Describe HPET */ |
| 455 | current_backup = current; |
| 456 | current = ivhd_describe_hpet(current); |
| 457 | ivrs->ivhd.length += (current - current_backup); |
| 458 | |
| 459 | /* Describe IOAPICs */ |
| 460 | current_backup = current; |
| 461 | current = acpi_fill_ivrs_ioapic(ivrs, current); |
| 462 | ivrs->ivhd.length += (current - current_backup); |
| 463 | |
| 464 | /* If EFR is not supported, IVHD type 11h is reserved */ |
| 465 | if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) |
| 466 | return current; |
| 467 | |
| 468 | return acpi_fill_ivrs11(current, ivrs); |
| 469 | } |