Werner Zeh | 42b8835 | 2021-11-16 07:31:44 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <arch/mmio.h> |
| 4 | #include <device/pci.h> |
| 5 | #include <device/pci_def.h> |
| 6 | #include <device/pci_ids.h> |
| 7 | #include <device/pci_ops.h> |
| 8 | #include <types.h> |
| 9 | |
| 10 | #include "nc_fpga.h" |
| 11 | |
| 12 | static DEVTREE_CONST uint32_t fpga_bar = CONFIG_EARLY_PCI_MMIO_BASE; |
| 13 | static bool nc_fpga_present = false; |
| 14 | |
| 15 | int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) |
| 16 | { |
| 17 | pci_devfn_t pci_dev = PCI_DEV(bus, dev, 0); |
| 18 | uint32_t id = pci_s_read_config32(pci_dev, PCI_VENDOR_ID); |
| 19 | |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 20 | if (id != (0x4091 << 16 | PCI_VID_SIEMENS)) |
Werner Zeh | 42b8835 | 2021-11-16 07:31:44 +0100 | [diff] [blame] | 21 | return -1; |
| 22 | |
| 23 | /* Setup base address for BAR0. */ |
| 24 | pci_s_write_config32(pci_dev, PCI_BASE_ADDRESS_0, mmio_base); |
| 25 | /* Enable memory access for pci_dev. */ |
| 26 | u16 reg16 = pci_s_read_config16(pci_dev, PCI_COMMAND); |
| 27 | reg16 |= PCI_COMMAND_MEMORY; |
| 28 | pci_s_write_config16(pci_dev, PCI_COMMAND, reg16); |
| 29 | nc_fpga_present = true; |
| 30 | |
| 31 | return 0; |
| 32 | } |
| 33 | |
| 34 | void nc_fpga_remap(uint32_t new_mmio) |
| 35 | { |
| 36 | #if ENV_RAMSTAGE |
| 37 | fpga_bar = new_mmio; |
| 38 | #endif |
| 39 | } |
| 40 | |
| 41 | void nc_fpga_post(uint8_t value) |
| 42 | { |
Angel Pons | ccf8134 | 2022-08-15 14:26:36 +0200 | [diff] [blame] | 43 | /* The function pci_early_device_probe is called in bootblock and romstage. Make sure |
Werner Zeh | 42b8835 | 2021-11-16 07:31:44 +0100 | [diff] [blame] | 44 | that in these stages the initialization code was successful before the POST code |
| 45 | value is written to the register. */ |
| 46 | if ((ENV_BOOTBLOCK || ENV_ROMSTAGE) && nc_fpga_present == false) |
| 47 | return; |
Elyes Haouas | 0a7a269 | 2022-12-08 08:45:29 +0100 | [diff] [blame] | 48 | write32p(fpga_bar + NC_FPGA_POST_OFFSET, value); |
Werner Zeh | 42b8835 | 2021-11-16 07:31:44 +0100 | [diff] [blame] | 49 | } |