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Lee Leahy2ed7eb72016-01-01 18:08:48 -08001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2015-2016 Intel Corp.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15
16config SOC_INTEL_QUARK
17 bool
18 help
19 Intel Quark support
20
21if SOC_INTEL_QUARK
22
23config CPU_SPECIFIC_OPTIONS
24 def_bool y
25 select ARCH_BOOTBLOCK_X86_32
26 select ARCH_RAMSTAGE_X86_32
27 select ARCH_ROMSTAGE_X86_32
28 select ARCH_VERSTAGE_X86_32
29 select USE_MARCH_586
30
Lee Leahy9fd08952016-02-02 07:17:06 -080031#####
Lee Leahya7ba56e2016-02-07 10:42:14 -080032# Debug support
33# The following options provide debug support for the Quark coreboot
34# code. The SD LED is used as a binary marker to determine if a
35# specific point in the execution flow has been reached.
36#####
37
38config ENABLE_DEBUG_LED
39 bool
40 default n
41 help
42 Enable the use of the SD LED for early debugging before serial output
43 is available. Setting this LED indicates that control has reached the
44 desired check point.
45
46config ENABLE_DEBUG_LED_ESRAM
47 bool "SD LED indicates ESRAM initialized"
48 default n
49 select ENABLE_DEBUG_LED
50 help
51 Indicate that ESRAM has been successfully initialized.
52
53config ENABLE_DEBUG_LED_FINDFSP
54 bool "SD LED indicates fsp.bin file was found"
55 default n
56 select ENABLE_DEBUG_LED
57 help
58 Indicate that fsp.bin was found.
59
60config ENABLE_DEBUG_LED_TEMPRAMINIT
61 bool "SD LED indicates TempRamInit was successful"
62 default n
63 select ENABLE_DEBUG_LED
64 help
65 Indicate that TempRamInit was successful.
66
67#####
Lee Leahy9fd08952016-02-02 07:17:06 -080068# Flash layout
69# Specify the size of the coreboot file system in the read-only
70# (recovery) portion of the flash part.
71#####
72
73config CBFS_SIZE
74 hex
75 default 0x200000
76 help
77 Specify the size of the coreboot file system in the read-only (recovery)
78 portion of the flash part. On Quark systems the firmware image stores
79 more than just coreboot, including:
80 - The chipset microcode (RMU) binary file located at 0xFFF00000
81 - Intel Trusted Execution Engine firmware
82
83#####
Lee Leahya7ba56e2016-02-07 10:42:14 -080084# FSP binary
85# The following options control the FSP binary file placement in
86# the flash image and ESRAM. This file is required by the Quark
87# SoC code to boot coreboot and its payload.
88#####
89
90config ADD_FSP_RAW_BIN
91 bool "Add the Intel FSP binary to the flash image without relocation"
92 default n
93 depends on PLATFORM_USES_FSP1_1
94 help
95 Select this option to add an Intel FSP binary to
96 the resulting coreboot image.
97
98 Note: Without this binary, coreboot builds relying on the FSP
99 will not boot
100
101config FSP_FILE
102 string "Intel FSP binary path and filename"
103 default "3rdparty/blobs/soc/intel/quark/fsp.bin"
104 depends on PLATFORM_USES_FSP1_1
105 depends on ADD_FSP_RAW_BIN
106 help
107 The path and filename of the Intel FSP binary for this platform.
108
109config FSP_IMAGE_ID_STRING
110 string "8 byte platform string identifying the FSP platform"
111 default "QUK-FSP0"
112 depends on PLATFORM_USES_FSP1_1
113 help
114 8 ASCII character byte signature string that will help match the FSP
115 binary to a supported hardware configuration.
116
117config FSP_LOC
118 hex
119 default 0xfff80000
120 depends on PLATFORM_USES_FSP1_1
121 help
122 The location in CBFS that the FSP is located. This must match the
123 value that is set in the FSP binary. If the FSP needs to be moved,
124 rebase the FSP with Intel's BCT (tool).
125
126config FSP_ESRAM_LOC
127 hex
128 default 0x80000000
129 depends on PLATFORM_USES_FSP1_1
130 help
131 The location in ESRAM where a copy of the FSP binary is placed.
132
133#####
134# FSP PDAT binary
135# The following options control the FSP platform data binary
136# file placement in the flash image.
137#####
138
139config ADD_FSP_PDAT_FILE
140 bool "Should the PDAT binary be added to the flash image?"
141 default n
142 depends on PLATFORM_USES_FSP1_1
143 help
144 The PDAT file is required for the FSP 1.1 binary
145
146config FSP_PDAT_FILE
147 string
148 default "3rdparty/blobs/soc/intel/quark/pdat.bin"
149 depends on PLATFORM_USES_FSP1_1
150 depends on ADD_FSP_PDAT_FILE
151 help
152 The path and filename of the Intel Galileo platform-data-patch (PDAT)
153 binary. This binary file is generated by the platform-data-patch.py
154 script released with the Quark BSP and contains the Ethernet address.
155
156config FSP_PDAT_LOC
157 hex
158 default 0xfff10000
159 depends on PLATFORM_USES_FSP1_1
160 depends on ADD_FSP_PDAT_FILE
161 help
162 The location in CBFS that the PDAT is located. It must match the
163 PCD PcdPlatformDataBaseAddress of Quark SoC FSP.
164
165#####
Lee Leahy9fd08952016-02-02 07:17:06 -0800166# RMU binary
167# The following options control the Quark chipset microcode file
168# placement in the flash image. This file is required to bring
169# the Quark processor out of reset.
170#####
171
172config ADD_RMU_FILE
173 bool "Should the RMU binary be added to the flash image?"
174 default n
175 help
176 The RMU file is required to get the chip out of reset.
177
178config RMU_FILE
179 string
180 default "3rdparty/blobs/soc/intel/quark/rmu.bin"
181 depends on ADD_RMU_FILE
182 help
183 The path and filename of the Intel Quark RMU binary.
184
185config RMU_LOC
186 hex
187 default 0xfff00000
188 depends on ADD_RMU_FILE
189 help
190 The location in CBFS that the RMU is located. It must match the
191 strap-determined base address.
192
Lee Leahy2ed7eb72016-01-01 18:08:48 -0800193endif # SOC_INTEL_QUARK