Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 LiPPERT Embedded Computers GmbH |
| 5 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 6 | * |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
Uwe Hermann | 86c9b88 | 2008-11-19 13:42:14 +0000 | [diff] [blame^] | 22 | /* Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards. */ |
| 23 | |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 24 | #define ASSEMBLY 1 |
| 25 | |
| 26 | #include <stdlib.h> |
| 27 | #include <stdint.h> |
| 28 | #include <device/pci_def.h> |
| 29 | #include <arch/io.h> |
| 30 | #include <device/pnp_def.h> |
| 31 | #include <arch/hlt.h> |
| 32 | #include "pc80/serial.c" |
| 33 | #include "arch/i386/lib/console.c" |
| 34 | #include "ram/ramtest.c" |
| 35 | #include "cpu/x86/bist.h" |
| 36 | #include "cpu/x86/msr.h" |
| 37 | #include <cpu/amd/lxdef.h> |
| 38 | #include <cpu/amd/geode_post_code.h> |
| 39 | #include "southbridge/amd/cs5536/cs5536.h" |
| 40 | |
| 41 | #define POST_CODE(x) outb(x, 0x80) |
| 42 | |
| 43 | #include "southbridge/amd/cs5536/cs5536_early_smbus.c" |
| 44 | #include "southbridge/amd/cs5536/cs5536_early_setup.c" |
| 45 | #include "superio/ite/it8712f/it8712f_early_serial.c" |
| 46 | |
| 47 | #define ManualConf 1 /* No automatic strapped PLL config */ |
| 48 | #define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ |
| 49 | #define PLLMSRlo 0x00DE6001 |
| 50 | #define DIMM0 0xA0 |
| 51 | #define DIMM1 0xA2 |
| 52 | |
| 53 | static inline int spd_read_byte(unsigned int device, unsigned int address) |
| 54 | { |
Uwe Hermann | 86c9b88 | 2008-11-19 13:42:14 +0000 | [diff] [blame^] | 55 | if (device != DIMM0) |
| 56 | return 0xFF; /* No DIMM1, don't even try. */ |
| 57 | |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 58 | return smbus_read_byte(device, address); |
| 59 | } |
| 60 | |
| 61 | #include "northbridge/amd/lx/raminit.h" |
| 62 | #include "northbridge/amd/lx/pll_reset.c" |
| 63 | #include "northbridge/amd/lx/raminit.c" |
| 64 | #include "sdram/generic_sdram.c" |
| 65 | #include "cpu/amd/model_lx/cpureginit.c" |
| 66 | #include "cpu/amd/model_lx/syspreinit.c" |
| 67 | |
| 68 | static void msr_init(void) |
| 69 | { |
| 70 | msr_t msr; |
| 71 | |
| 72 | /* Setup access to the cache for under 1MB. */ |
| 73 | msr.hi = 0x24fffc02; |
| 74 | msr.lo = 0x1000A000; /* 0-A0000 write back */ |
| 75 | wrmsr(CPU_RCONF_DEFAULT, msr); |
| 76 | |
| 77 | msr.hi = 0x0; /* Write back */ |
| 78 | msr.lo = 0x0; |
| 79 | wrmsr(CPU_RCONF_A0_BF, msr); |
| 80 | wrmsr(CPU_RCONF_C0_DF, msr); |
| 81 | wrmsr(CPU_RCONF_E0_FF, msr); |
| 82 | |
| 83 | /* Setup access to the cache for under 640K. Note MC not setup yet. */ |
| 84 | msr.hi = 0x20000000; |
| 85 | msr.lo = 0xfff80; |
| 86 | wrmsr(MSR_GLIU0 + 0x20, msr); |
| 87 | |
| 88 | msr.hi = 0x20000000; |
| 89 | msr.lo = 0x80fffe0; |
| 90 | wrmsr(MSR_GLIU0 + 0x21, msr); |
| 91 | |
| 92 | msr.hi = 0x20000000; |
| 93 | msr.lo = 0xfff80; |
| 94 | wrmsr(MSR_GLIU1 + 0x20, msr); |
| 95 | |
| 96 | msr.hi = 0x20000000; |
| 97 | msr.lo = 0x80fffe0; |
| 98 | wrmsr(MSR_GLIU1 + 0x21, msr); |
| 99 | } |
| 100 | |
| 101 | static const u16 sio_init_table[] = { // hi=data, lo=index |
| 102 | 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) |
| 103 | 0x1E2C, // disable ATXPowerGood - will cause a reboot! |
| 104 | 0x0423, // don't delay POWerOK1/2 |
| 105 | 0x9072, // watchdog triggers POWOK, counts seconds |
| 106 | #if !USE_WATCHDOG_ON_BOOT |
| 107 | 0x0073, 0x0074, // disable watchdog by setting timeout to 0 |
| 108 | #endif |
| 109 | 0xBF25, 0x372A, 0xF326, // select GPIO function for most pins |
| 110 | 0xBF27, 0xFF28, 0x2529, // (GP36=FAN_CTL3, GP13=PWROK1) |
| 111 | 0x1E2C, // VIN6=enabled?, FAN4/5 enabled, VIN7=internal, VIN3=enabled |
| 112 | 0x46B8, 0x0CB9, // enable pullups |
| 113 | 0x36C0, // enable Simple-I/O for GP15,14,12,11= LIVE_LED, WD_ACTIVE, RS485_EN2,1 |
| 114 | 0xFFC3, // enable Simple-I/O for GP47-40 (GPIOs on Supervisory Connector) |
| 115 | 0x26C8, // config GP15,12,11 as output; GP14 as input |
| 116 | 0x2DF5, // map Hw Monitor Thermal Output to GP55 |
| 117 | 0x0DF8, // map GP LED Blinking 1 to GP15=LIVE_LED (deactivate Simple-I/O to use) |
| 118 | }; |
| 119 | |
| 120 | /* Early mainboard specific GPIO setup. */ |
| 121 | static void mb_gpio_init(void) |
| 122 | { |
| 123 | int i; |
| 124 | |
Uwe Hermann | 86c9b88 | 2008-11-19 13:42:14 +0000 | [diff] [blame^] | 125 | /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */ |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 126 | it8712f_enter_conf(); |
Uwe Hermann | 86c9b88 | 2008-11-19 13:42:14 +0000 | [diff] [blame^] | 127 | for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) { |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 128 | u16 val = sio_init_table[i]; |
Uwe Hermann | 86c9b88 | 2008-11-19 13:42:14 +0000 | [diff] [blame^] | 129 | outb((u8)val, SIO_INDEX); |
| 130 | outb(val >> 8, SIO_DATA); |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 131 | } |
| 132 | it8712f_exit_conf(); |
| 133 | } |
| 134 | |
| 135 | void cache_as_ram_main(void) |
| 136 | { |
| 137 | POST_CODE(0x01); |
| 138 | |
| 139 | static const struct mem_controller memctrl[] = { |
| 140 | {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} |
| 141 | }; |
| 142 | |
| 143 | SystemPreInit(); |
| 144 | msr_init(); |
| 145 | |
| 146 | cs5536_early_setup(); |
| 147 | |
Uwe Hermann | 86c9b88 | 2008-11-19 13:42:14 +0000 | [diff] [blame^] | 148 | /* |
| 149 | * Note: must do this AFTER the early_setup! It is counting on some |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 150 | * early MSR setup for CS5536. |
| 151 | */ |
Uwe Hermann | 86c9b88 | 2008-11-19 13:42:14 +0000 | [diff] [blame^] | 152 | it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 153 | mb_gpio_init(); |
| 154 | uart_init(); |
| 155 | console_init(); |
| 156 | |
| 157 | pll_reset(ManualConf); |
| 158 | |
| 159 | cpuRegInit(); |
| 160 | |
| 161 | sdram_initialize(1, memctrl); |
| 162 | |
| 163 | /* Check memory. */ |
| 164 | /* ram_check(0x00000000, 640 * 1024); */ |
| 165 | |
| 166 | /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ |
| 167 | return; |
| 168 | } |