Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| 3 | |
| 4 | #include <arch/ioapic.h> |
| 5 | #include <cbfs.h> |
| 6 | #include <console/console.h> |
| 7 | #include <cpu/x86/lapic.h> |
| 8 | #include <device/pci.h> |
| 9 | #include <fsp/api.h> |
| 10 | #include <soc/ramstage.h> |
| 11 | #include <soc/pm.h> |
| 12 | |
| 13 | /* C620 IOAPIC has 120 redirection entries */ |
| 14 | #define C620_IOAPIC_REDIR_ENTRIES 120 |
| 15 | |
| 16 | static void pci_domain_set_resources(struct device *dev) |
| 17 | { |
| 18 | assign_resources(dev->link_list); |
| 19 | } |
| 20 | |
| 21 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) |
| 22 | { |
| 23 | /* not implemented yet */ |
| 24 | } |
| 25 | |
| 26 | static struct device_operations pci_domain_ops = { |
| 27 | .read_resources = &pci_domain_read_resources, |
| 28 | .set_resources = &pci_domain_set_resources, |
| 29 | .scan_bus = &pci_domain_scan_bus, |
| 30 | }; |
| 31 | |
| 32 | static void init_cpus(struct device *dev) |
| 33 | { |
| 34 | /* not implemented yet */ |
| 35 | } |
| 36 | |
| 37 | static struct device_operations cpu_bus_ops = { |
| 38 | .read_resources = DEVICE_NOOP, |
| 39 | .set_resources = DEVICE_NOOP, |
| 40 | .enable_resources = DEVICE_NOOP, |
| 41 | .init = init_cpus, |
| 42 | .scan_bus = NULL, |
| 43 | }; |
| 44 | |
| 45 | static void chip_enable_dev(struct device *dev) |
| 46 | { |
| 47 | /* Set the operations if it is a special bus type */ |
| 48 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 49 | dev->ops = &pci_domain_ops; |
| 50 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 51 | dev->ops = &cpu_bus_ops; |
| 52 | } |
| 53 | } |
| 54 | |
| 55 | static void pch_enable_ioapic(const struct device *dev) |
| 56 | { |
| 57 | uint32_t reg32; |
| 58 | |
| 59 | set_ioapic_id((void *)IO_APIC_ADDR, 2); |
| 60 | |
| 61 | /* affirm full set of redirection table entries ("write once") */ |
| 62 | reg32 = io_apic_read((void *)IO_APIC_ADDR, 1); |
| 63 | |
| 64 | reg32 &= ~0x00ff0000; |
| 65 | reg32 |= (C620_IOAPIC_REDIR_ENTRIES - 1) << 16; |
| 66 | |
| 67 | io_apic_write((void *)IO_APIC_ADDR, 1, reg32); |
| 68 | |
| 69 | /* |
| 70 | * Select Boot Configuration register (0x03) and |
| 71 | * use Processor System Bus (0x01) to deliver interrupts. |
| 72 | */ |
| 73 | io_apic_write((void *)IO_APIC_ADDR, 3, 1); |
| 74 | } |
| 75 | |
| 76 | struct pci_operations soc_pci_ops = { |
| 77 | .set_subsystem = pci_dev_set_subsystem, |
| 78 | }; |
| 79 | |
| 80 | static void chip_final(void *data) |
| 81 | { |
| 82 | /* nothing implemented yet */ |
| 83 | } |
| 84 | |
| 85 | static void chip_init(void *data) |
| 86 | { |
| 87 | printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); |
| 88 | fsp_silicon_init(false); |
| 89 | pch_enable_ioapic(NULL); |
| 90 | setup_lapic(); |
| 91 | } |
| 92 | |
| 93 | struct chip_operations soc_intel_xeon_sp_cpx_ops = { |
| 94 | CHIP_NAME("Intel Cooperlake-SP") |
| 95 | .enable_dev = chip_enable_dev, |
| 96 | .init = chip_init, |
| 97 | .final = chip_final |
| 98 | }; |