blob: f447034029f53b1b0fc555398a9d908cda944a11 [file] [log] [blame]
Stefan Reinauer52db0b92012-12-07 17:15:04 -08001/*
2 * This file is part of the coreboot project.
3 *
Stefan Reinauer08dc3572013-05-14 16:57:50 -07004 * Copyright 2010 Google Inc.
Stefan Reinauer52db0b92012-12-07 17:15:04 -08005 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19 * MA 02110-1301 USA
20 */
21
David Hendricksbba80902013-03-14 15:24:57 -070022#include <arch/cache.h>
David Hendricks3d7344a2013-01-08 21:05:06 -080023#include <arch/hlt.h>
David Hendricks50c0a502013-01-31 17:05:50 -080024#include <arch/stages.h>
Gabe Black8b685392013-09-29 03:02:55 -070025#include <bootblock_common.h>
Hung-Te Linfe187922013-02-01 01:09:24 +080026#include <cbfs.h>
Hung-Te Linb868d402013-02-06 22:01:18 +080027#include <console/console.h>
Kyösti Mälkki5a5c8862014-01-26 14:41:54 +020028#include <smp/node.h>
David Hendricks50c0a502013-01-31 17:05:50 -080029
David Hendricks50c0a502013-01-31 17:05:50 -080030void main(void)
Stefan Reinauer52db0b92012-12-07 17:15:04 -080031{
Hung-Te Lin5f83f6c2013-02-04 14:38:03 +080032 const char *stage_name = "fallback/romstage";
33 void *entry;
David Hendricksbba80902013-03-14 15:24:57 -070034 uint32_t sctlr;
35
36 /* Globally disable MMU, caches, and branch prediction (these should
37 * be disabled by default on reset) */
38 sctlr = read_sctlr();
39 sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I);
40 write_sctlr(sctlr);
41
Gabe Black51edd542013-09-30 23:00:33 -070042 arm_invalidate_caches();
David Hendricksbba80902013-03-14 15:24:57 -070043
44 /*
David Hendricksf9be7562013-03-21 21:58:50 -070045 * Re-enable icache and branch prediction. MMU and dcache will be
46 * set up later.
David Hendricksbba80902013-03-14 15:24:57 -070047 */
48 sctlr = read_sctlr();
David Hendricksf9be7562013-03-21 21:58:50 -070049 sctlr |= SCTLR_Z | SCTLR_I;
David Hendricksbba80902013-03-14 15:24:57 -070050 write_sctlr(sctlr);
Stefan Reinauer52db0b92012-12-07 17:15:04 -080051
Gabe Black8b685392013-09-29 03:02:55 -070052 bootblock_cpu_init();
53 bootblock_mainboard_init();
David Hendricks3d7344a2013-01-08 21:05:06 -080054
Kyösti Mälkki21333f92014-02-14 10:04:31 +020055#if CONFIG_BOOTBLOCK_CONSOLE
Hung-Te Linb868d402013-02-06 22:01:18 +080056 console_init();
Stefan Reinauer919c8042013-05-16 10:57:15 -070057#endif
58
Hung-Te Lin5f83f6c2013-02-04 14:38:03 +080059 entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
Hung-Te Lin6fe0cab2013-01-22 18:57:56 +080060
Hung-Te Lin5f83f6c2013-02-04 14:38:03 +080061 if (entry) stage_exit(entry);
Stefan Reinauer52db0b92012-12-07 17:15:04 -080062 hlt();
63}