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Kyösti Mälkkie68f4ff2014-10-22 15:53:34 +03001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <stdint.h>
21#include <string.h>
22#include <cpu/x86/mtrr.h>
23#include <northbridge/amd/agesa/agesawrapper.h>
24#include <northbridge/amd/agesa/BiosCallOuts.h>
25#include "cpuRegisters.h"
26#include "cpuCacheInit.h"
27#include "cpuApicUtilities.h"
28#include "cpuEarlyInit.h"
29#include "cpuLateInit.h"
30#include "Dispatcher.h"
31#include "cpuCacheInit.h"
32#include "amdlib.h"
33#include "Filecode.h"
34#include "heapManager.h"
35#include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */
36
37#define FILECODE UNASSIGNED_FILE_FILECODE
38
39/* ACPI table pointers returned by AmdInitLate */
40VOID *DmiTable = NULL;
41VOID *AcpiPstate = NULL;
42VOID *AcpiSrat = NULL;
43VOID *AcpiSlit = NULL;
44
45VOID *AcpiWheaMce = NULL;
46VOID *AcpiWheaCmc = NULL;
47VOID *AcpiAlib = NULL;
48
49/* TODO: Function body should be in mainboard directory. */
Kyösti Mälkki34ad72c2014-10-21 13:43:46 +030050void OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly)
Kyösti Mälkkie68f4ff2014-10-22 15:53:34 +030051{
52}
53
Kyösti Mälkki34ad72c2014-10-21 13:43:46 +030054void OemCustomizeInitPost(AMD_POST_PARAMS *InitPost)
Kyösti Mälkkie68f4ff2014-10-22 15:53:34 +030055{
56#if IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
57 InitPost->MemConfig.UmaMode = UMA_AUTO;
58 InitPost->MemConfig.BottomIo = 0xE0;
59 InitPost->MemConfig.UmaSize = 0xE0-0xC0;
60#endif
61}
62
63#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
64AGESA_STATUS agesawrapper_amdinitcpuio(void)
65{
66 UINT32 PciData;
67 PCI_ADDR PciAddress;
68 AMD_CONFIG_PARAMS StdHeader;
69 UINT32 nodes;
70 UINT32 node;
71 UINT32 sblink;
72 UINT32 i;
73 UINT32 TOM;
74
75 /* get the number of coherent nodes in the system */
76 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
77 LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
78 nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0]
79
80 /* Find out the Link ID of Node0 that connects to the
81 * Southbridge (system IO hub). e.g. family10 MCM Processor,
82 * sbLink is Processor0 Link2, internal Node0 Link3
83 */
84 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
85 LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
86 sblink = (PciData >> 8) & 3; //assume ganged
87
88 /* Enable MMIO on AMD CPU Address Map Controller for all nodes */
89 for (node = 0; node < nodes; node++) {
90 /* clear all MMIO Mapped Base/Limit Registers */
91 for (i = 0; i < 8; i++) {
92 PciData = 0x00000000;
93 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i * 8);
94 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
95 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i * 8);
96 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
97 }
98
99 /* clear all IO Space Base/Limit Registers */
100 for (i = 0; i < 4; i++) {
101 PciData = 0x00000000;
102 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i * 8);
103 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
104 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i * 8);
105 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
106 }
107
108 /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
109 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84);
110 PciData = 0x00000B00;
111 PciData |= sblink << 4;
112 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
113 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80);
114 PciData = 0x00000A03;
115 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
116
117 /* Set TOM1-FFFFFFFF to Node0 sbLink. */
118 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C);
119 PciData = 0x00FFFF00;
120 PciData |= sblink << 4;
121 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
122 TOM = (UINT32) MsrRead(TOP_MEM);
123 PciData = (TOM >> 8) | 0x03;
124 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
125 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
126
127 /* Set MMCONF space to Node0 sbLink with NP set.
128 * default E0000000-EFFFFFFF
129 * Just have all mmio set to non-posted,
130 * coreboot not implemente the range by range setting yet.
131 */
132 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
133 PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1; //1MB each bus
134 PciData = (PciData >> 8) & 0xFFFFFF00;
135 PciData |= 0x80; //NP
136 PciData |= sblink << 4;
137 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
138 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8);
Kyösti Mälkki8548a482014-12-14 11:24:36 +0200139 PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03;
Kyösti Mälkkie68f4ff2014-10-22 15:53:34 +0300140 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
141
142 /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO */
143 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
144 PciData = 0x00FFF000;
145 PciData |= sblink << 4;
146 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
147 PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
148 PciData = 0x00000033;
149 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
150 }
151
152 return AGESA_SUCCESS;
153}
154
155AGESA_STATUS agesawrapper_amdinitmmio(void)
156{
157 UINT64 MsrReg;
158 AMD_CONFIG_PARAMS StdHeader;
159
160 /*
161 * Set the MMIO Configuration Base Address and Bus Range onto
162 * MMIO configuration base Address MSR register.
163 */
164 MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
165 LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
166
167 /*
168 * Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
169 */
170 LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
171 MsrReg = MsrReg | (1ULL << 46);
172 LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
173
174 /* Set ROM cache onto WP to decrease post time */
175 MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5;
176 LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
177 MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
178 LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
179
180 return AGESA_SUCCESS;
181}
182#endif
183
184AGESA_STATUS agesawrapper_amdinitreset(void)
185{
186 AGESA_STATUS status = AGESA_SUCCESS;
187 AMD_INTERFACE_PARAMS AmdParamStruct;
188 AMD_RESET_PARAMS AmdResetParams;
189
190 LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
191
192 LibAmdMemFill(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader));
193
194 AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
195 AmdParamStruct.AllocationMethod = ByHost;
196 AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
197 AmdParamStruct.NewStructPtr = &AmdResetParams;
198 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
199 AmdParamStruct.StdHeader.CalloutPtr = NULL;
200 AmdParamStruct.StdHeader.Func = 0;
201 AmdParamStruct.StdHeader.ImageBasePtr = 0;
202 status = AmdCreateStruct(&AmdParamStruct);
203 if (status != AGESA_SUCCESS) {
204 return status;
205 }
206 AmdResetParams.HtConfig.Depth = 0;
207
208 //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default
209 //but we need to call AmdCreateStruct to call HeapManagerInit, or the event log not work
210#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE)
211 status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
212#endif
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300213 AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
Kyösti Mälkkie68f4ff2014-10-22 15:53:34 +0300214 AmdReleaseStruct(&AmdParamStruct);
215
216 return status;
217}
218
219AGESA_STATUS agesawrapper_amdinitearly(void)
220{
221 AGESA_STATUS status;
222 AMD_INTERFACE_PARAMS AmdParamStruct;
223 AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
224 UINT32 TscRateInMhz;
225 CPU_SPECIFIC_SERVICES *FamilySpecificServices;
226
227 LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
228
229 AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
230 AmdParamStruct.AllocationMethod = PreMemHeap;
231 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
232 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
233 AmdParamStruct.StdHeader.Func = 0;
234 AmdParamStruct.StdHeader.ImageBasePtr = 0;
235 status = AmdCreateStruct(&AmdParamStruct);
236 if (status != AGESA_SUCCESS) {
237 return status;
238 }
239
240 AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr;
241
242 /* OEM Should Customize the defaults through this hook */
243 OemCustomizeInitEarly(AmdEarlyParamsPtr);
244
245 status = AmdInitEarly(AmdEarlyParamsPtr);
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300246 AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
Kyösti Mälkkie68f4ff2014-10-22 15:53:34 +0300247
248 GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices,
249 &AmdParamStruct.StdHeader);
250 FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
251 printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz);
252
253 AmdReleaseStruct(&AmdParamStruct);
254 return status;
255}
256
257AGESA_STATUS agesawrapper_amdinitpost(void)
258{
259 AGESA_STATUS status;
260 AMD_INTERFACE_PARAMS AmdParamStruct;
261 AMD_POST_PARAMS *PostParams;
262 UINT32 TscRateInMhz;
263 CPU_SPECIFIC_SERVICES *FamilySpecificServices;
264
265 LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
266
267 AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
268 AmdParamStruct.AllocationMethod = PreMemHeap;
269 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
270 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
271 AmdParamStruct.StdHeader.Func = 0;
272 AmdParamStruct.StdHeader.ImageBasePtr = 0;
273
274 status = AmdCreateStruct(&AmdParamStruct);
275 if (status != AGESA_SUCCESS) {
276 return status;
277 }
278 PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
279
280 /* OEM Should Customize the defaults through this hook */
281 OemCustomizeInitPost(PostParams);
282
283 status = AmdInitPost(PostParams);
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300284 AGESA_EVENTLOG(status, &PostParams->StdHeader);
Kyösti Mälkkie68f4ff2014-10-22 15:53:34 +0300285
286 AmdReleaseStruct(&AmdParamStruct);
287
288 /* Initialize heap space */
289 EmptyHeap();
290
291 GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices,
292 &AmdParamStruct.StdHeader);
293 FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
294 printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz);
295
296 return status;
297}
298
299AGESA_STATUS agesawrapper_amdinitenv(void)
300{
301 AGESA_STATUS status;
302 AMD_INTERFACE_PARAMS AmdParamStruct;
303 AMD_ENV_PARAMS *EnvParams;
304
305 LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
306
307 AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
308 AmdParamStruct.AllocationMethod = PostMemDram;
309 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
310 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
311 AmdParamStruct.StdHeader.Func = 0;
312 AmdParamStruct.StdHeader.ImageBasePtr = 0;
313
314 status = AmdCreateStruct(&AmdParamStruct);
315 if (status != AGESA_SUCCESS) {
316 return status;
317 }
318 EnvParams = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
319 status = AmdInitEnv(EnvParams);
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300320 AGESA_EVENTLOG(status, &EnvParams->StdHeader);
Kyösti Mälkkie68f4ff2014-10-22 15:53:34 +0300321
322 AmdReleaseStruct(&AmdParamStruct);
323 return status;
324}
325
326VOID *agesawrapper_getlateinitptr(int pick)
327{
328 switch (pick) {
329 case PICK_DMI:
330 return DmiTable;
331
332 case PICK_PSTATE:
333 return AcpiPstate;
334
335 case PICK_SRAT:
336 return AcpiSrat;
337
338 case PICK_SLIT:
339 return AcpiSlit;
340 case PICK_WHEA_MCE:
341 return AcpiWheaMce;
342 case PICK_WHEA_CMC:
343 return AcpiWheaCmc;
344 case PICK_ALIB:
345 return AcpiAlib;
346 default:
347 return NULL;
348 }
349
350 return NULL;
351}
352
353AGESA_STATUS agesawrapper_amdinitmid(void)
354{
355 AGESA_STATUS status;
356 AMD_INTERFACE_PARAMS AmdParamStruct;
357
Kyösti Mälkkie68f4ff2014-10-22 15:53:34 +0300358 LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
359
360 AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
361 AmdParamStruct.AllocationMethod = PostMemDram;
362 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
363 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
364 AmdParamStruct.StdHeader.Func = 0;
365 AmdParamStruct.StdHeader.ImageBasePtr = 0;
366
367 status = AmdCreateStruct(&AmdParamStruct);
368 if (status != AGESA_SUCCESS) {
369 return status;
370 }
371 status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300372 AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
Kyösti Mälkkie68f4ff2014-10-22 15:53:34 +0300373 AmdReleaseStruct(&AmdParamStruct);
374
375 return status;
376}
377
378AGESA_STATUS agesawrapper_amdinitlate(void)
379{
380 AGESA_STATUS status;
381 AMD_INTERFACE_PARAMS AmdParamStruct;
382 AMD_LATE_PARAMS *AmdLateParamsPtr;
383
384 LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
385
386 AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
387 AmdParamStruct.AllocationMethod = PostMemDram;
388 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
389 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
390 AmdParamStruct.StdHeader.Func = 0;
391 AmdParamStruct.StdHeader.ImageBasePtr = 0;
392
393 AmdCreateStruct(&AmdParamStruct);
394 AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
395
396 printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32) AmdLateParamsPtr);
397
398 status = AmdInitLate(AmdLateParamsPtr);
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300399 AGESA_EVENTLOG(status, &AmdLateParamsPtr->StdHeader);
Kyösti Mälkkie68f4ff2014-10-22 15:53:34 +0300400 ASSERT(status == AGESA_SUCCESS);
401
402 DmiTable = AmdLateParamsPtr->DmiTable;
403 AcpiPstate = AmdLateParamsPtr->AcpiPState;
404 AcpiSrat = AmdLateParamsPtr->AcpiSrat;
405 AcpiSlit = AmdLateParamsPtr->AcpiSlit;
406 AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
407 AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
408 AcpiAlib = AmdLateParamsPtr->AcpiAlib;
409
410 printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
411 " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
412 " Mce:%p\n Cmc:%p\n Alib:%p\n",
413 __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
414
415 /* Don't release the structure until coreboot has copied the ACPI tables.
416 * AmdReleaseStruct (&AmdLateParams);
417 */
418
419 return status;
420}
421
422/**
423 * @param[in] UINTN ApicIdOfCore,
424 * @param[in] AP_EXE_PARAMS *LaunchApParams
425 */
426AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr)
427{
428 AGESA_STATUS status;
429 AMD_LATE_PARAMS AmdLateParams;
430
431 LibAmdMemFill(&AmdLateParams, 0, sizeof(AMD_LATE_PARAMS), &(AmdLateParams.StdHeader));
432
433 AmdLateParams.StdHeader.AltImageBasePtr = 0;
434 AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
435 AmdLateParams.StdHeader.Func = 0;
436 AmdLateParams.StdHeader.ImageBasePtr = 0;
437 AmdLateParams.StdHeader.HeapStatus = HEAP_TEMP_MEM;
438
439 printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t) Data);
440 status = AmdLateRunApTask((AP_EXE_PARAMS *) ConfigPtr);
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300441 AGESA_EVENTLOG(status, &AmdLateParams.StdHeader);
Kyösti Mälkkie68f4ff2014-10-22 15:53:34 +0300442 ASSERT((status == AGESA_SUCCESS) || (status == AGESA_UNSUPPORTED));
443
444 return status;
445}