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Kyösti Mälkki923302a2014-10-19 17:54:44 +03001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <stdint.h>
21#include <string.h>
22#include <cpu/x86/mtrr.h>
23#include <northbridge/amd/agesa/agesawrapper.h>
24#include <northbridge/amd/agesa/BiosCallOuts.h>
25#include "cpuRegisters.h"
26#include "cpuCacheInit.h"
27#include "cpuApicUtilities.h"
28#include "cpuEarlyInit.h"
29#include "cpuLateInit.h"
30#include "Dispatcher.h"
31#include "cpuCacheInit.h"
32#include "amdlib.h"
33#include "Filecode.h"
34#include <arch/io.h>
35
36#include <southbridge/amd/cimx/sb900/gpio_oem.h>
37
38#define FILECODE UNASSIGNED_FILE_FILECODE
39
40/* ACPI table pointers returned by AmdInitLate */
41VOID *DmiTable = NULL;
42VOID *AcpiPstate = NULL;
43VOID *AcpiSrat = NULL;
44VOID *AcpiSlit = NULL;
45
46VOID *AcpiWheaMce = NULL;
47VOID *AcpiWheaCmc = NULL;
48VOID *AcpiAlib = NULL;
49
Kyösti Mälkki923302a2014-10-19 17:54:44 +030050UINT32 ReadAmdSbPmr(IN UINT8 IndexValue, OUT UINT8 * DataValue);
51UINT32 WriteAmdSbPmr(IN UINT8 IndexValue, IN UINT8 DataValue);
52
53VOID ClearSBSmiAndWake(IN UINT16 PmBase);
54
55VOID ClearAllSmiEnableInPmio(VOID);
56
57/* Read SB Power Management Area */
58UINT32 ReadAmdSbPmr(IN UINT8 IndexValue, OUT UINT8 * DataValue)
59{
60 WriteIo8(SB_PM_INDEX_PORT, IndexValue);
61 *DataValue = ReadIo8(SB_PM_DATA_PORT);
62 return 0;
63}
64
65/* Write ATI SB Power Management Area */
66UINT32 WriteAmdSbPmr(IN UINT8 IndexValue, IN UINT8 DataValue)
67{
68 WriteIo8(SB_PM_INDEX_PORT, IndexValue);
69 WriteIo8(SB_PM_DATA_PORT, DataValue);
70 return 0;
71}
72
73/* Clear any SMI status or wake status left over from boot. */
74VOID ClearSBSmiAndWake(IN UINT16 PmBase)
75{
76 UINT16 Pm1Sts;
77 UINT32 Pm1Cnt;
78 UINT32 Gpe0Sts;
79
80 /* Read the ACPI registers */
81 Pm1Sts = ReadIo16(PmBase + R_SB_ACPI_PM1_STATUS);
82 Pm1Cnt = ReadIo32(PmBase + R_SB_ACPI_PM1_STATUS);
83 Gpe0Sts = ReadIo32(PmBase + R_SB_ACPI_EVENT_STATUS);
84
85 /* Clear any SMI or wake state from the boot */
86 Pm1Sts &= B_PWR_BTN_STATUS + B_WAKEUP_STATUS;
87 Pm1Cnt &= ~(B_SCI_EN);
88
89 /* Write back */
90 WriteIo16(PmBase + R_SB_ACPI_PM1_STATUS, Pm1Sts);
91 WriteIo32(PmBase + R_SB_ACPI_PM_CONTROL, Pm1Cnt);
92 WriteIo32(PmBase + R_SB_ACPI_EVENT_STATUS, Gpe0Sts);
93}
94
95/* Clear all SMI enable bit in PMIO register */
96VOID ClearAllSmiEnableInPmio(VOID)
97{
98 UINT32 AcpiMmioAddr;
99 UINT32 SmiMmioAddr;
100 UINT8 Data8 = 0;
101 UINT16 Data16 = 0;
102
103 /* Get SB900 MMIO Base (AcpiMmioAddr) */
104 ReadAmdSbPmr(SB_PMIOA_REG24 + 3, &Data8);
105 Data16 = Data8 << 8;
106 ReadAmdSbPmr(SB_PMIOA_REG24 + 2, &Data8);
107 Data16 |= Data8;
108 AcpiMmioAddr = (UINT32) Data16 << 16;
109 SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
110
111 Mmio32(SmiMmioAddr, 0xA0) = 0x0;
112 Mmio32(SmiMmioAddr, 0xA4) = 0x0;
113 Mmio32(SmiMmioAddr, 0xA8) = 0x0;
114 Mmio32(SmiMmioAddr, 0xAC) = 0x0;
115 Mmio32(SmiMmioAddr, 0xB0) = 0x0;
116 Mmio32(SmiMmioAddr, 0xB4) = 0x0;
117 Mmio32(SmiMmioAddr, 0xB8) = 0x0;
118 Mmio32(SmiMmioAddr, 0xBC) = 0x0;
119 Mmio32(SmiMmioAddr, 0xC0) = 0x0;
120 Mmio32(SmiMmioAddr, 0xC4) = 0x0;
121}
122
123AGESA_STATUS agesawrapper_amdinitcpuio(VOID)
124{
125 UINT64 MsrReg;
126 UINT32 PciData;
127 PCI_ADDR PciAddress;
128 AMD_CONFIG_PARAMS StdHeader;
129
130 /* Enable MMIO on AMD CPU Address Map Controller */
131
132 /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
133 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
134 PciData = 0x00000B00;
135 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
136 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
137 PciData = 0x00000A03;
138 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
139
140 /* Set TOM-DFFFFFFF to Node0 Link0. */
141 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
142 PciData = 0x00DFFF00;
143 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
144 LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
145 MsrReg = (MsrReg >> 8) | 3;
146 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
147 PciData = (UINT32) MsrReg;
148 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
149 /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
150 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xBC);
151 PciData = 0x00FFFF00 | 0x80;
152 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
153 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xB8);
Kyösti Mälkki8548a482014-12-14 11:24:36 +0200154 PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 03;
Kyösti Mälkki923302a2014-10-19 17:54:44 +0300155 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
156 /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
157 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
158//- PciData = 0x0000F000;
159 PciData = 0x00FFF000;
160 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
161 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
162 PciData = 0x00000013;
163 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
164
165 return AGESA_SUCCESS;
166}
167
168AGESA_STATUS agesawrapper_amdinitmmio(VOID)
169{
170 UINT64 MsrReg;
171 UINT32 PciData;
172 PCI_ADDR PciAddress;
173 AMD_CONFIG_PARAMS StdHeader;
174
175 /*
176 Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
177 Address MSR register.
178 */
179 MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
180 LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
181
182 /*
183 Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
184 */
185 LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
186 MsrReg = MsrReg | 0x0000400000000000ull;
187 LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
188
Kyösti Mälkki923302a2014-10-19 17:54:44 +0300189 /* Enable Non-Post Memory in CPU */
190 PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x3FF80);
191 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4);
192 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
193
194 PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03);
195 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA0);
196 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
197
198 /* Enable memory access */
199 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
200 LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
201
202 PciData |= BIT1;
203 PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
204 LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
205
206 /* Set ROM cache onto WP to decrease post time */
207 MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
208 LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
209 MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
210 LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
211
212 /* Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI */
213//- ClearSBSmiAndWake (SB_ACPI_BASE_ADDRESS);
214//- ClearAllSmiEnableInPmio ();
215
216 return AGESA_SUCCESS;
217}
218
219AGESA_STATUS agesawrapper_amdinitreset(VOID)
220{
221 AGESA_STATUS status;
222 AMD_INTERFACE_PARAMS AmdParamStruct;
223 AMD_RESET_PARAMS AmdResetParams;
224
225 LibAmdMemFill(&AmdParamStruct,
226 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
227
228 LibAmdMemFill(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader));
229
230 AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
231 AmdParamStruct.AllocationMethod = ByHost;
232 AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
233 AmdParamStruct.NewStructPtr = &AmdResetParams;
234 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
235 AmdParamStruct.StdHeader.CalloutPtr = NULL;
236 AmdParamStruct.StdHeader.Func = 0;
237 AmdParamStruct.StdHeader.ImageBasePtr = 0;
238 AmdCreateStruct(&AmdParamStruct);
239 AmdResetParams.HtConfig.Depth = 0;
240
241 status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300242 AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
Kyösti Mälkki923302a2014-10-19 17:54:44 +0300243 AmdReleaseStruct(&AmdParamStruct);
244 return status;
245}
246
247AGESA_STATUS agesawrapper_amdinitearly(VOID)
248{
249 AGESA_STATUS status;
250 AMD_INTERFACE_PARAMS AmdParamStruct;
251 AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
252
253 LibAmdMemFill(&AmdParamStruct,
254 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
255
256 AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
257 AmdParamStruct.AllocationMethod = PreMemHeap;
258 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
259 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
260 AmdParamStruct.StdHeader.Func = 0;
261 AmdParamStruct.StdHeader.ImageBasePtr = 0;
262 AmdCreateStruct(&AmdParamStruct);
263
264 AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr;
265 OemCustomizeInitEarly(AmdEarlyParamsPtr);
266
267 status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300268 AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
Kyösti Mälkki923302a2014-10-19 17:54:44 +0300269 AmdReleaseStruct(&AmdParamStruct);
270
271 return status;
272}
273
274AGESA_STATUS agesawrapper_amdinitpost(VOID)
275{
276 AGESA_STATUS status;
277 AMD_INTERFACE_PARAMS AmdParamStruct;
278
279 LibAmdMemFill(&AmdParamStruct,
280 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
281
282 AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
283 AmdParamStruct.AllocationMethod = PreMemHeap;
284 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
285 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
286 AmdParamStruct.StdHeader.Func = 0;
287 AmdParamStruct.StdHeader.ImageBasePtr = 0;
288
289 AmdCreateStruct(&AmdParamStruct);
290 status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr);
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300291 AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
Kyösti Mälkki923302a2014-10-19 17:54:44 +0300292 AmdReleaseStruct(&AmdParamStruct);
293
294 /* Initialize heap space */
295 EmptyHeap();
296
297 return status;
298}
299
300AGESA_STATUS agesawrapper_amdinitenv(VOID)
301{
302 AGESA_STATUS status;
303 AMD_INTERFACE_PARAMS AmdParamStruct;
304
305 LibAmdMemFill(&AmdParamStruct,
306 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
307
308 AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
309 AmdParamStruct.AllocationMethod = PostMemDram;
310 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
311 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
312 AmdParamStruct.StdHeader.Func = 0;
313 AmdParamStruct.StdHeader.ImageBasePtr = 0;
314 AmdCreateStruct(&AmdParamStruct);
315 status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr);
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300316 AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
Kyösti Mälkki923302a2014-10-19 17:54:44 +0300317 AmdReleaseStruct(&AmdParamStruct);
318
319 return status;
320}
321
322VOID *agesawrapper_getlateinitptr(int pick)
323{
324 switch (pick) {
325 case PICK_DMI:
326 return DmiTable;
327
328 case PICK_PSTATE:
329 return AcpiPstate;
330
331 case PICK_SRAT:
332 return AcpiSrat;
333
334 case PICK_SLIT:
335 return AcpiSlit;
336 case PICK_WHEA_MCE:
337 return AcpiWheaMce;
338 case PICK_WHEA_CMC:
339 return AcpiWheaCmc;
340 case PICK_ALIB:
341 return AcpiAlib;
342 default:
343 return NULL;
344 }
345}
346
347AGESA_STATUS agesawrapper_amdinitmid(VOID)
348{
349 AGESA_STATUS status;
350 AMD_INTERFACE_PARAMS AmdParamStruct;
351
Kyösti Mälkki923302a2014-10-19 17:54:44 +0300352 LibAmdMemFill(&AmdParamStruct,
353 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
354
355 AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
356 AmdParamStruct.AllocationMethod = PostMemDram;
357 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
358 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
359 AmdParamStruct.StdHeader.Func = 0;
360 AmdParamStruct.StdHeader.ImageBasePtr = 0;
361
362 AmdCreateStruct(&AmdParamStruct);
363
364 status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300365 AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
Kyösti Mälkki923302a2014-10-19 17:54:44 +0300366 AmdReleaseStruct(&AmdParamStruct);
367
368 return status;
369}
370
371AGESA_STATUS agesawrapper_amdinitlate(VOID)
372{
373 AGESA_STATUS status;
374 AMD_LATE_PARAMS AmdLateParams;
375
376 LibAmdMemFill(&AmdLateParams, 0, sizeof(AMD_LATE_PARAMS), &(AmdLateParams.StdHeader));
377
378 AmdLateParams.StdHeader.AltImageBasePtr = 0;
379 AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
380 AmdLateParams.StdHeader.Func = 0;
381 AmdLateParams.StdHeader.ImageBasePtr = 0;
382
383 status = AmdInitLate(&AmdLateParams);
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300384 AGESA_EVENTLOG(status, &AmdLateParams.StdHeader);
Kyösti Mälkki923302a2014-10-19 17:54:44 +0300385 ASSERT(status == AGESA_SUCCESS);
386
387 DmiTable = AmdLateParams.DmiTable;
388 AcpiPstate = AmdLateParams.AcpiPState;
389 AcpiSrat = AmdLateParams.AcpiSrat;
390 AcpiSlit = AmdLateParams.AcpiSlit;
391
392 AcpiWheaMce = AmdLateParams.AcpiWheaMce;
393 AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
394 AcpiAlib = AmdLateParams.AcpiAlib;
395
396 return status;
397}
398
399AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr)
400{
401 AGESA_STATUS status;
402 AP_EXE_PARAMS ApExeParams;
403
404 LibAmdMemFill(&ApExeParams, 0, sizeof(AP_EXE_PARAMS), &(ApExeParams.StdHeader));
405
406 ApExeParams.StdHeader.AltImageBasePtr = 0;
407 ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
408 ApExeParams.StdHeader.Func = 0;
409 ApExeParams.StdHeader.ImageBasePtr = 0;
410
411 status = AmdLateRunApTask(&ApExeParams);
Kyösti Mälkki1aa35c62014-10-21 14:19:04 +0300412 AGESA_EVENTLOG(status, &ApExeParams.StdHeader);
Kyösti Mälkki923302a2014-10-19 17:54:44 +0300413 ASSERT(status == AGESA_SUCCESS);
414
415 return status;
416}