Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 1 | #ifndef PCI_DEF_H |
| 2 | #define PCI_DEF_H |
| 3 | |
| 4 | /* |
| 5 | * Under PCI, each device has 256 bytes of configuration address space, |
| 6 | * of which the first 64 bytes are standardized as follows: |
| 7 | */ |
| 8 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
| 9 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
| 10 | #define PCI_COMMAND 0x04 /* 16 bits */ |
| 11 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
| 12 | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
| 13 | #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ |
| 14 | #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ |
| 15 | #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ |
| 16 | #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ |
| 17 | #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ |
| 18 | #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ |
| 19 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
| 20 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
Lee Leahy | e0dae99 | 2015-01-15 15:02:55 -0800 | [diff] [blame] | 21 | #define PCI_COMMAND_INT_DISABLE 0x400 /* Interrupt disable */ |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 22 | |
| 23 | #define PCI_STATUS 0x06 /* 16 bits */ |
| 24 | #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ |
| 25 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ |
| 26 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ |
| 27 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ |
| 28 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
| 29 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 30 | #define PCI_STATUS_DEVSEL_FAST 0x000 |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 31 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
| 32 | #define PCI_STATUS_DEVSEL_SLOW 0x400 |
| 33 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
| 34 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
| 35 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
| 36 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
| 37 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
| 38 | |
| 39 | #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 |
| 40 | revision */ |
| 41 | #define PCI_REVISION_ID 0x08 /* Revision ID */ |
| 42 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
| 43 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
| 44 | |
| 45 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
| 46 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
| 47 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
| 48 | #define PCI_HEADER_TYPE_NORMAL 0 |
| 49 | #define PCI_HEADER_TYPE_BRIDGE 1 |
| 50 | #define PCI_HEADER_TYPE_CARDBUS 2 |
| 51 | |
| 52 | #define PCI_BIST 0x0f /* 8 bits */ |
| 53 | #define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
| 54 | #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
| 55 | #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
| 56 | |
| 57 | /* |
| 58 | * Base addresses specify locations in memory or I/O space. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 59 | * Decoded size can be determined by writing a value of |
| 60 | * 0xffffffff to the register, and reading it back. Only |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 61 | * 1 bits are decoded. |
| 62 | */ |
| 63 | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
| 64 | #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ |
| 65 | #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ |
| 66 | #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ |
| 67 | #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ |
| 68 | #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ |
| 69 | #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ |
| 70 | #define PCI_BASE_ADDRESS_SPACE_IO 0x01 |
| 71 | #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 |
Eric Biederman | 992cd00 | 2004-10-14 21:10:23 +0000 | [diff] [blame] | 72 | #define PCI_BASE_ADDRESS_MEM_LIMIT_MASK 0x06 |
| 73 | #define PCI_BASE_ADDRESS_MEM_LIMIT_32 0x00 /* 32 bit address */ |
| 74 | #define PCI_BASE_ADDRESS_MEM_LIMIT_1M 0x02 /* Below 1M [obsolete] */ |
| 75 | #define PCI_BASE_ADDRESS_MEM_LIMIT_64 0x04 /* 64 bit address */ |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 76 | #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ |
Eric Biederman | 992cd00 | 2004-10-14 21:10:23 +0000 | [diff] [blame] | 77 | #define PCI_BASE_ADDRESS_MEM_ATTR_MASK 0x0f |
| 78 | #define PCI_BASE_ADDRESS_IO_ATTR_MASK 0x03 |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 79 | /* bit 1 is reserved if address_space = 1 */ |
| 80 | |
| 81 | /* Header type 0 (normal devices) */ |
| 82 | #define PCI_CARDBUS_CIS 0x28 |
| 83 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 84 | #define PCI_SUBSYSTEM_ID 0x2e |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 85 | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
| 86 | #define PCI_ROM_ADDRESS_ENABLE 0x01 |
| 87 | #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) |
| 88 | |
| 89 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
| 90 | |
| 91 | /* 0x35-0x3b are reserved */ |
| 92 | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
| 93 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
| 94 | #define PCI_MIN_GNT 0x3e /* 8 bits */ |
| 95 | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
| 96 | |
| 97 | /* Header type 1 (PCI-to-PCI bridges) */ |
| 98 | #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ |
| 99 | #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ |
| 100 | #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ |
| 101 | #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ |
| 102 | #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ |
| 103 | #define PCI_IO_LIMIT 0x1d |
| 104 | #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ |
| 105 | #define PCI_IO_RANGE_TYPE_16 0x00 |
| 106 | #define PCI_IO_RANGE_TYPE_32 0x01 |
| 107 | #define PCI_IO_RANGE_MASK ~0x0f |
| 108 | #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ |
| 109 | #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ |
| 110 | #define PCI_MEMORY_LIMIT 0x22 |
| 111 | #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f |
| 112 | #define PCI_MEMORY_RANGE_MASK ~0x0f |
| 113 | #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ |
| 114 | #define PCI_PREF_MEMORY_LIMIT 0x26 |
| 115 | #define PCI_PREF_RANGE_TYPE_MASK 0x0f |
| 116 | #define PCI_PREF_RANGE_TYPE_32 0x00 |
| 117 | #define PCI_PREF_RANGE_TYPE_64 0x01 |
| 118 | #define PCI_PREF_RANGE_MASK ~0x0f |
| 119 | #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ |
| 120 | #define PCI_PREF_LIMIT_UPPER32 0x2c |
| 121 | #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ |
| 122 | #define PCI_IO_LIMIT_UPPER16 0x32 |
| 123 | /* 0x34 same as for htype 0 */ |
| 124 | /* 0x35-0x3b is reserved */ |
| 125 | #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ |
| 126 | /* 0x3c-0x3d are same as for htype 0 */ |
| 127 | #define PCI_BRIDGE_CONTROL 0x3e |
| 128 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ |
| 129 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ |
| 130 | #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ |
| 131 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ |
| 132 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ |
| 133 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ |
| 134 | #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ |
| 135 | |
| 136 | /* Header type 2 (CardBus bridges) */ |
| 137 | #define PCI_CB_CAPABILITY_LIST 0x14 |
| 138 | /* 0x15 reserved */ |
| 139 | #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ |
| 140 | #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ |
| 141 | #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ |
| 142 | #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ |
| 143 | #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ |
| 144 | #define PCI_CB_MEMORY_BASE_0 0x1c |
| 145 | #define PCI_CB_MEMORY_LIMIT_0 0x20 |
| 146 | #define PCI_CB_MEMORY_BASE_1 0x24 |
| 147 | #define PCI_CB_MEMORY_LIMIT_1 0x28 |
| 148 | #define PCI_CB_IO_BASE_0 0x2c |
| 149 | #define PCI_CB_IO_BASE_0_HI 0x2e |
| 150 | #define PCI_CB_IO_LIMIT_0 0x30 |
| 151 | #define PCI_CB_IO_LIMIT_0_HI 0x32 |
| 152 | #define PCI_CB_IO_BASE_1 0x34 |
| 153 | #define PCI_CB_IO_BASE_1_HI 0x36 |
| 154 | #define PCI_CB_IO_LIMIT_1 0x38 |
| 155 | #define PCI_CB_IO_LIMIT_1_HI 0x3a |
| 156 | #define PCI_CB_IO_RANGE_MASK ~0x03 |
| 157 | /* 0x3c-0x3d are same as for htype 0 */ |
| 158 | #define PCI_CB_BRIDGE_CONTROL 0x3e |
| 159 | #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ |
| 160 | #define PCI_CB_BRIDGE_CTL_SERR 0x02 |
| 161 | #define PCI_CB_BRIDGE_CTL_ISA 0x04 |
| 162 | #define PCI_CB_BRIDGE_CTL_VGA 0x08 |
| 163 | #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 |
| 164 | #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ |
| 165 | #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ |
| 166 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ |
| 167 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 |
| 168 | #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 |
| 169 | #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 |
| 170 | #define PCI_CB_SUBSYSTEM_ID 0x42 |
| 171 | #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ |
| 172 | /* 0x48-0x7f reserved */ |
| 173 | |
| 174 | /* Capability lists */ |
| 175 | |
| 176 | #define PCI_CAP_LIST_ID 0 /* Capability ID */ |
| 177 | #define PCI_CAP_ID_PM 0x01 /* Power Management */ |
| 178 | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ |
| 179 | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ |
| 180 | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 181 | #define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */ |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 182 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
Eric Biederman | 5cd8173 | 2004-03-11 15:01:31 +0000 | [diff] [blame] | 183 | #define PCI_CAP_ID_PCIX 0x07 /* PCIX */ |
| 184 | #define PCI_CAP_ID_HT 0x08 /* Hypertransport */ |
Kyösti Mälkki | cb141bc | 2014-02-07 19:24:23 +0200 | [diff] [blame] | 185 | #define PCI_CAP_ID_EHCI_DEBUG 0x0A /* EHCI debug port */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 186 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
Eric Biederman | 5cd8173 | 2004-03-11 15:01:31 +0000 | [diff] [blame] | 187 | #define PCI_CAP_ID_PCIE 0x10 /* PCI Express */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 188 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 189 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
| 190 | #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
Eric Biederman | 860ad37 | 2003-07-21 23:30:29 +0000 | [diff] [blame] | 191 | |
| 192 | /* Hypertransport Registers */ |
| 193 | #define PCI_HT_CAP_SIZEOF 4 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 194 | #define PCI_HT_CAP_HOST_CTRL 4 /* Host link control */ |
Eric Biederman | 860ad37 | 2003-07-21 23:30:29 +0000 | [diff] [blame] | 195 | #define PCI_HT_CAP_HOST_WIDTH 6 /* width value & capability */ |
| 196 | #define PCI_HT_CAP_HOST_FREQ 0x09 /* Host frequency */ |
| 197 | #define PCI_HT_CAP_HOST_FREQ_CAP 0x0a /* Host Frequency capability */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 198 | #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ |
| 199 | #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ |
Eric Biederman | 860ad37 | 2003-07-21 23:30:29 +0000 | [diff] [blame] | 200 | #define PCI_HT_CAP_SLAVE_WIDTH0 6 /* width value & capability */ |
| 201 | #define PCI_HT_CAP_SLAVE_WIDTH1 0x0a /* width value & capability to */ |
| 202 | #define PCI_HT_CAP_SLAVE_FREQ0 0x0d /* Slave frequency from */ |
| 203 | #define PCI_HT_CAP_SLAVE_FREQ1 0x011 /* Slave frequency to */ |
| 204 | #define PCI_HT_CAP_SLAVE_FREQ_CAP0 0x0e /* Frequency capability from */ |
| 205 | #define PCI_HT_CAP_SLAVE_FREQ_CAP1 0x12 /* Frequency capability to */ |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 206 | #define PCI_HT_CAP_SLAVE_LINK_ENUM 0x14 /* Link Enumeration Scratchpad */ |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 207 | |
| 208 | /* Power Management Registers */ |
| 209 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 210 | #define PCI_PM_PMC 2 /* PM Capabilities Register */ |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 211 | #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ |
| 212 | #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 213 | #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxiliary power support */ |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 214 | #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ |
| 215 | #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ |
| 216 | #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ |
| 217 | #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ |
| 218 | #define PCI_PM_CTRL 4 /* PM control and status register */ |
| 219 | #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ |
| 220 | #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ |
| 221 | #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ |
| 222 | #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ |
| 223 | #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ |
| 224 | #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ |
| 225 | #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ |
| 226 | #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ |
| 227 | #define PCI_PM_DATA_REGISTER 7 /* (??) */ |
| 228 | #define PCI_PM_SIZEOF 8 |
| 229 | |
| 230 | /* AGP registers */ |
| 231 | |
| 232 | #define PCI_AGP_VERSION 2 /* BCD version number */ |
| 233 | #define PCI_AGP_RFU 3 /* Rest of capability flags */ |
| 234 | #define PCI_AGP_STATUS 4 /* Status register */ |
| 235 | #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ |
| 236 | #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ |
| 237 | #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ |
| 238 | #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ |
| 239 | #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ |
| 240 | #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ |
| 241 | #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ |
| 242 | #define PCI_AGP_COMMAND 8 /* Control register */ |
| 243 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
| 244 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
| 245 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
| 246 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ |
| 247 | #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ |
| 248 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ |
| 249 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ |
| 250 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ |
| 251 | #define PCI_AGP_SIZEOF 12 |
| 252 | |
| 253 | /* Slot Identification */ |
| 254 | |
| 255 | #define PCI_SID_ESR 2 /* Expansion Slot Register */ |
| 256 | #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ |
| 257 | #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ |
| 258 | #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ |
| 259 | |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 260 | /* Message Signaled Interrupts registers */ |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 261 | |
| 262 | #define PCI_MSI_FLAGS 2 /* Various flags */ |
| 263 | #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ |
| 264 | #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ |
| 265 | #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ |
| 266 | #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ |
| 267 | #define PCI_MSI_RFU 3 /* Rest of capability flags */ |
| 268 | #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ |
| 269 | #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ |
| 270 | #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ |
| 271 | #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 272 | #define PCI_MSI_MASK_BIT 16 /* Mask bits register */ |
| 273 | |
| 274 | /* CompactPCI Hotswap Register */ |
| 275 | |
| 276 | #define PCI_CHSWP_CSR 2 /* Control and Status Register */ |
| 277 | #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ |
| 278 | #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ |
| 279 | #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ |
| 280 | #define PCI_CHSWP_LOO 0x08 /* LED On / Off */ |
| 281 | #define PCI_CHSWP_PI 0x30 /* Programming Interface */ |
| 282 | #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ |
| 283 | #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ |
| 284 | |
| 285 | /* PCI-X registers */ |
| 286 | |
| 287 | #define PCI_X_CMD 2 /* Modes & Features */ |
| 288 | #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ |
| 289 | #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ |
| 290 | #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ |
| 291 | #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ |
| 292 | #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ |
| 293 | #define PCI_X_STATUS 4 /* PCI-X capabilities */ |
| 294 | #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ |
| 295 | #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ |
| 296 | #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */ |
| 297 | #define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */ |
| 298 | #define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */ |
| 299 | #define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */ |
| 300 | #define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */ |
| 301 | #define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */ |
| 302 | #define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ |
| 303 | #define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ |
| 304 | #define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ |
| 305 | #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ |
| 306 | #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ |
| 307 | |
| 308 | /* PCI-X bridge registers */ |
| 309 | #define PCI_X_SEC_STATUS 2 /* Secondary status */ |
| 310 | #define PCI_X_SSTATUS_64BIT 0x0001 /* The bus behind the bridge is 64bits wide */ |
| 311 | #define PCI_X_SSTATUS_133MHZ 0x0002 /* The bus behind the bridge is 133Mhz Capable */ |
| 312 | #define PCI_X_SSTATUS_SPL_DISC 0x0004 /* Split Completion Discarded */ |
| 313 | #define PCI_X_SSTATUS_UNX_SPL 0x0008 /* Unexpected Split Completion */ |
| 314 | #define PCI_X_SSTATUS_SPL_OVR 0x0010 /* Split Completion Overrun */ |
| 315 | #define PCI_X_SSTATUS_SPL_DLY 0x0020 /* Split Completion Delayed */ |
| 316 | #define PCI_X_SSTATUS_MFREQ(x) (((x) & 0x03c0) >> 6) /* PCI-X mode and frequency */ |
| 317 | #define PCI_X_SSTATUS_CONVENTIONAL_PCI 0x0 |
| 318 | #define PCI_X_SSTATUS_MODE1_66MHZ 0x1 |
| 319 | #define PCI_X_SSTATUS_MODE1_100MHZ 0x2 |
| 320 | #define PCI_X_SSTATUS_MODE1_133MHZ 0x3 |
| 321 | #define PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ 0x9 |
| 322 | #define PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ 0xa |
| 323 | #define PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ 0xb |
| 324 | #define PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ 0xd |
| 325 | #define PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ 0xe |
| 326 | #define PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ 0xf |
| 327 | #define PCI_X_SSTATUS_VERSION(x) (((x) >> 12) & 3) /* Version */ |
| 328 | #define PCI_X_SSTATUS_266MHZ 0x4000 /* The bus behind the bridge is 266Mhz Capable */ |
| 329 | #define PCI_X_SSTAUTS_533MHZ 0x8000 /* The bus behind the bridge is 533Mhz Capable */ |
| 330 | |
| 331 | /* PCI Express capability registers */ |
| 332 | |
| 333 | #define PCI_EXP_FLAGS 2 /* Capabilities register */ |
| 334 | #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ |
| 335 | #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ |
| 336 | #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ |
| 337 | #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ |
| 338 | #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ |
| 339 | #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ |
| 340 | #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ |
| 341 | #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ |
| 342 | #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ |
| 343 | #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ |
| 344 | #define PCI_EXP_DEVCAP 4 /* Device capabilities */ |
| 345 | #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ |
| 346 | #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ |
| 347 | #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ |
| 348 | #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ |
| 349 | #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ |
| 350 | #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ |
| 351 | #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ |
| 352 | #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ |
Stefan Reinauer | 4855f56 | 2009-04-21 23:01:10 +0000 | [diff] [blame] | 353 | #define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 354 | #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ |
| 355 | #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ |
| 356 | #define PCI_EXP_DEVCTL 8 /* Device Control */ |
| 357 | #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ |
| 358 | #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ |
| 359 | #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ |
| 360 | #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ |
| 361 | #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ |
| 362 | #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ |
| 363 | #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ |
| 364 | #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ |
| 365 | #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ |
| 366 | #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ |
| 367 | #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ |
| 368 | #define PCI_EXP_DEVSTA 10 /* Device Status */ |
| 369 | #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ |
| 370 | #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ |
| 371 | #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ |
| 372 | #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */ |
| 373 | #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ |
| 374 | #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ |
| 375 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 376 | #define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ |
| 377 | #define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ |
| 378 | #define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ |
Kane Chen | 18cb134 | 2014-10-01 11:13:54 +0800 | [diff] [blame] | 379 | #define PCI_EXP_CLK_PM 0x40000 /* Clock Power Management */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 380 | #define PCI_EXP_LNKCTL 16 /* Link Control */ |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 381 | #define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ |
| 382 | #define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ |
Kane Chen | 18cb134 | 2014-10-01 11:13:54 +0800 | [diff] [blame] | 383 | #define PCI_EXP_EN_CLK_PM 0x100 /* Enable Clock Power Management */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 384 | #define PCI_EXP_LNKSTA 18 /* Link Status */ |
Duncan Laurie | 90dcdd4 | 2011-10-25 14:15:11 -0700 | [diff] [blame] | 385 | #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ |
| 386 | #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 387 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
| 388 | #define PCI_EXP_SLTCTL 24 /* Slot Control */ |
| 389 | #define PCI_EXP_SLTSTA 26 /* Slot Status */ |
| 390 | #define PCI_EXP_RTCTL 28 /* Root Control */ |
| 391 | #define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */ |
| 392 | #define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */ |
| 393 | #define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */ |
| 394 | #define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */ |
| 395 | #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ |
| 396 | #define PCI_EXP_RTCAP 30 /* Root Capabilities */ |
| 397 | #define PCI_EXP_RTSTA 32 /* Root Status */ |
| 398 | |
| 399 | /* Extended Capabilities (PCI-X 2.0 and Express) */ |
| 400 | #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) |
| 401 | #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) |
| 402 | #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) |
| 403 | |
| 404 | #define PCI_EXT_CAP_ID_ERR 1 |
| 405 | #define PCI_EXT_CAP_ID_VC 2 |
| 406 | #define PCI_EXT_CAP_ID_DSN 3 |
| 407 | #define PCI_EXT_CAP_ID_PWR 4 |
| 408 | |
Kenji Chen | 31c6e63 | 2014-10-04 01:14:44 +0800 | [diff] [blame] | 409 | /* Extended Capability lists*/ |
| 410 | #define PCIE_EXT_CAP_OFFSET 0x100 |
| 411 | #define PCIE_EXT_CAP_AER_ID 0x0001 |
| 412 | #define PCIE_EXT_CAP_L1SS_ID 0x001E |
| 413 | #define PCIE_EXT_CAP_LTR_ID 0x0018 |
| 414 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 415 | /* Advanced Error Reporting */ |
| 416 | #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ |
| 417 | #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ |
| 418 | #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ |
| 419 | #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ |
| 420 | #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ |
| 421 | #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ |
| 422 | #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ |
| 423 | #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ |
| 424 | #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ |
| 425 | #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ |
| 426 | #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ |
| 427 | #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ |
| 428 | #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ |
| 429 | /* Same bits as above */ |
| 430 | #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ |
| 431 | /* Same bits as above */ |
| 432 | #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ |
| 433 | #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ |
| 434 | #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ |
| 435 | #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ |
| 436 | #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ |
| 437 | #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ |
| 438 | #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ |
| 439 | /* Same bits as above */ |
| 440 | #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ |
| 441 | #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ |
| 442 | #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ |
| 443 | #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ |
| 444 | #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ |
| 445 | #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ |
| 446 | #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ |
| 447 | #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ |
| 448 | #define PCI_ERR_ROOT_STATUS 48 |
| 449 | #define PCI_ERR_ROOT_COR_SRC 52 |
| 450 | #define PCI_ERR_ROOT_SRC 54 |
| 451 | |
| 452 | /* Virtual Channel */ |
| 453 | #define PCI_VC_PORT_REG1 4 |
| 454 | #define PCI_VC_PORT_REG2 8 |
| 455 | #define PCI_VC_PORT_CTRL 12 |
| 456 | #define PCI_VC_PORT_STATUS 14 |
| 457 | #define PCI_VC_RES_CAP 16 |
| 458 | #define PCI_VC_RES_CTRL 20 |
| 459 | #define PCI_VC_RES_STATUS 26 |
| 460 | |
| 461 | /* Power Budgeting */ |
| 462 | #define PCI_PWR_DSR 4 /* Data Select Register */ |
| 463 | #define PCI_PWR_DATA 8 /* Data Register */ |
| 464 | #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ |
| 465 | #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ |
| 466 | #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ |
| 467 | #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ |
| 468 | #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ |
| 469 | #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ |
| 470 | #define PCI_PWR_CAP 12 /* Capability */ |
| 471 | #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ |
| 472 | |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 473 | |
| 474 | /* |
| 475 | * The PCI interface treats multi-function devices as independent |
| 476 | * devices. The slot/function address of each device is encoded |
| 477 | * in a single byte as follows: |
| 478 | * |
| 479 | * 7:3 = slot |
| 480 | * 2:0 = function |
| 481 | */ |
Lee Leahy | ae3fd34 | 2017-03-07 12:55:23 -0800 | [diff] [blame] | 482 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 483 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
| 484 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 485 | |
Kyösti Mälkki | c73acdb | 2013-06-15 17:16:56 +0300 | [diff] [blame] | 486 | /* Translation from PCI_DEV() to devicetree bus and path.pci.devfn. */ |
| 487 | #define PCI_DEV2DEVFN(sdev) (((sdev)>>12) & 0xff) |
| 488 | #define PCI_DEV2SEGBUS(sdev) (((sdev)>>20) & 0xfff) |
| 489 | |
Eric Biederman | a05b6dd | 2003-05-21 16:14:51 +0000 | [diff] [blame] | 490 | #endif /* PCI_DEF_H */ |