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review.coreboot.org / coreboot / 0df0e14fb5b613e76ff022359c55d5df5633b40f / . / src / vendorcode / amd / agesa / f14 / Include / PlatformInstall.h
blob: 31a311b8659969608b88d397620c685f370ff5d6 [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
14 * @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $
15 */
16/*
17 *****************************************************************************
18 *
19 * Copyright (c) 2011, Advanced Micro Devices, Inc.
20 * All rights reserved.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 *
44 * ***************************************************************************
45 *
46 */
47
48/*****************************************************************************
49 *
50 * Start processing the user options: First, set default settings
51 *
52 ****************************************************************************/
53
54/* Available options for image builds.
55 *
56 * As part of the image build for each image, define the options below to select the
57 * AGESA entry points included in that image. Turn these on in your option c file, not
58 * here.
59 */
60// #define AGESA_ENTRY_INIT_RESET TRUE
61// #define AGESA_ENTRY_INIT_RECOVERY TRUE
62// #define AGESA_ENTRY_INIT_EARLY TRUE
63// #define AGESA_ENTRY_INIT_POST TRUE
64// #define AGESA_ENTRY_INIT_ENV TRUE
65// #define AGESA_ENTRY_INIT_MID TRUE
66// #define AGESA_ENTRY_INIT_LATE TRUE
67// #define AGESA_ENTRY_INIT_S3SAVE TRUE
68// #define AGESA_ENTRY_INIT_RESUME TRUE
69// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
70// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
71
72/* Defaults for private/internal build control settings */
73/* Available options for image builds.
74 *
75 * As part of the image build for each image, define the options below to select the
76 * AGESA entry points included in that image.
77 */
78
79VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
80 //ModuleHeaderSignature
81 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
82 '0000',
83 //ModuleIdentifier[8]
84 AGESA_ID,
85 //ModuleVersion[12]
86 AGESA_VERSION_STRING,
87 //ModuleDispatcher
88 NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
89 //NextBlock
90 NULL
91};
92
93/* Process user desired AGESA entry points */
94#ifndef AGESA_ENTRY_INIT_RESET
95 #define AGESA_ENTRY_INIT_RESET FALSE
96#endif
97
98#ifndef AGESA_ENTRY_INIT_RECOVERY
99 #define AGESA_ENTRY_INIT_RECOVERY FALSE
100#endif
101
102#ifndef AGESA_ENTRY_INIT_EARLY
103 #define AGESA_ENTRY_INIT_EARLY FALSE
104#endif
105
106#ifndef AGESA_ENTRY_INIT_POST
107 #define AGESA_ENTRY_INIT_POST FALSE
108#endif
109
110#ifndef AGESA_ENTRY_INIT_ENV
111 #define AGESA_ENTRY_INIT_ENV FALSE
112#endif
113
114#ifndef AGESA_ENTRY_INIT_MID
115 #define AGESA_ENTRY_INIT_MID FALSE
116#endif
117
118#ifndef AGESA_ENTRY_INIT_LATE
119 #define AGESA_ENTRY_INIT_LATE FALSE
120#endif
121
122#ifndef AGESA_ENTRY_INIT_S3SAVE
123 #define AGESA_ENTRY_INIT_S3SAVE FALSE
124#endif
125
126#ifndef AGESA_ENTRY_INIT_RESUME
127 #define AGESA_ENTRY_INIT_RESUME FALSE
128#endif
129
130#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
131 #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
132#endif
133
134#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
135 #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
136#endif
137
138/* Default the late AP entry point to off. It can be enabled
139 by any family that may need the late AP functionality, or
140 by any feature code that may need it. The IBVs no longer
141 have control over this entry point. */
142#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
143 #undef AGESA_ENTRY_LATE_RUN_AP_TASK
144#endif
145#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE
146
147
148
149/* Process solution defined socket / family installations
150 *
151 * As part of the release package for each image, define the options below to select the
152 * AGESA processor support included in that image.
153 */
154
155/* Default sockets to off */
156#define OPTION_G34_SOCKET_SUPPORT FALSE
157#define OPTION_C32_SOCKET_SUPPORT FALSE
158#define OPTION_S1G3_SOCKET_SUPPORT FALSE
159#define OPTION_S1G4_SOCKET_SUPPORT FALSE
160#define OPTION_ASB2_SOCKET_SUPPORT FALSE
161#define OPTION_FS1_SOCKET_SUPPORT FALSE
162#define OPTION_FM1_SOCKET_SUPPORT FALSE
163#define OPTION_FP1_SOCKET_SUPPORT FALSE
164#define OPTION_FT1_SOCKET_SUPPORT FALSE
165#define OPTION_AM3_SOCKET_SUPPORT FALSE
166
167/* Default families to off */
168#define OPTION_FAMILY10H FALSE
169#define OPTION_FAMILY12H FALSE
170#define OPTION_FAMILY14H FALSE
171#define OPTION_FAMILY15H FALSE
172
173
174/* Enable the appropriate socket support */
175#ifdef INSTALL_G34_SOCKET_SUPPORT
176 #if INSTALL_G34_SOCKET_SUPPORT == TRUE
177 #undef OPTION_G34_SOCKET_SUPPORT
178 #define OPTION_G34_SOCKET_SUPPORT TRUE
179 #endif
180#endif
181
182#ifdef INSTALL_C32_SOCKET_SUPPORT
183 #if INSTALL_C32_SOCKET_SUPPORT == TRUE
184 #undef OPTION_C32_SOCKET_SUPPORT
185 #define OPTION_C32_SOCKET_SUPPORT TRUE
186 #endif
187#endif
188
189#ifdef INSTALL_S1G3_SOCKET_SUPPORT
190 #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE
191 #undef OPTION_S1G3_SOCKET_SUPPORT
192 #define OPTION_S1G3_SOCKET_SUPPORT TRUE
193 #endif
194#endif
195
196#ifdef INSTALL_S1G4_SOCKET_SUPPORT
197 #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE
198 #undef OPTION_S1G4_SOCKET_SUPPORT
199 #define OPTION_S1G4_SOCKET_SUPPORT TRUE
200 #endif
201#endif
202
203#ifdef INSTALL_ASB2_SOCKET_SUPPORT
204 #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE
205 #undef OPTION_ASB2_SOCKET_SUPPORT
206 #define OPTION_ASB2_SOCKET_SUPPORT TRUE
207 #endif
208#endif
209
210#ifdef INSTALL_FS1_SOCKET_SUPPORT
211 #if INSTALL_FS1_SOCKET_SUPPORT == TRUE
212 #undef OPTION_FS1_SOCKET_SUPPORT
213 #define OPTION_FS1_SOCKET_SUPPORT TRUE
214 #endif
215#endif
216
217#ifdef INSTALL_FM1_SOCKET_SUPPORT
218 #if INSTALL_FM1_SOCKET_SUPPORT == TRUE
219 #undef OPTION_FM1_SOCKET_SUPPORT
220 #define OPTION_FM1_SOCKET_SUPPORT TRUE
221 #endif
222#endif
223
224#ifdef INSTALL_FP1_SOCKET_SUPPORT
225 #if INSTALL_FP1_SOCKET_SUPPORT == TRUE
226 #undef OPTION_FP1_SOCKET_SUPPORT
227 #define OPTION_FP1_SOCKET_SUPPORT TRUE
228 #endif
229#endif
230
231#ifdef INSTALL_FT1_SOCKET_SUPPORT
232 #if INSTALL_FT1_SOCKET_SUPPORT == TRUE
233 #undef OPTION_FT1_SOCKET_SUPPORT
234 #define OPTION_FT1_SOCKET_SUPPORT TRUE
235 #endif
236#endif
237
238#ifdef INSTALL_AM3_SOCKET_SUPPORT
239 #if INSTALL_AM3_SOCKET_SUPPORT == TRUE
240 #undef OPTION_AM3_SOCKET_SUPPORT
241 #define OPTION_AM3_SOCKET_SUPPORT TRUE
242 #endif
243#endif
244
245
246/* Enable the appropriate family support */
247// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3
248#ifdef INSTALL_FAMILY_10_SUPPORT
249 #if INSTALL_FAMILY_10_SUPPORT == TRUE
250 #undef OPTION_FAMILY10H
251 #define OPTION_FAMILY10H TRUE
252 #endif
253#endif
254
255// F12 is supported in FP1, FS1, & FM1
256#ifdef INSTALL_FAMILY_12_SUPPORT
257 #if INSTALL_FAMILY_12_SUPPORT == TRUE
258 #undef OPTION_FAMILY12H
259 #define OPTION_FAMILY12H TRUE
260 #endif
261#endif
262
263// F14 is supported in FT1
264#ifdef INSTALL_FAMILY_14_SUPPORT
265 #if INSTALL_FAMILY_14_SUPPORT == TRUE
266 #undef OPTION_FAMILY14H
267 #define OPTION_FAMILY14H TRUE
268 #endif
269#endif
270
271// F15 is supported in G34, C32, & AM3
272#ifdef INSTALL_FAMILY_15_SUPPORT
273 #if INSTALL_FAMILY_15_SUPPORT == TRUE
274 #undef OPTION_FAMILY15H
275 #define OPTION_FAMILY15H TRUE
276 #endif
277#endif
278
279
280/* Turn off families not required by socket designations */
281#if (OPTION_FAMILY10H == TRUE)
282 #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
283 #undef OPTION_FAMILY10H
284 #define OPTION_FAMILY10H FALSE
285 #endif
286#endif
287
288#if (OPTION_FAMILY12H == TRUE)
289 #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE)
290 #undef OPTION_FAMILY12H
291 #define OPTION_FAMILY12H FALSE
292 #endif
293#endif
294
295#if (OPTION_FAMILY14H == TRUE)
296 #if (OPTION_FT1_SOCKET_SUPPORT == FALSE)
297 #undef OPTION_FAMILY14H
298 #define OPTION_FAMILY14H FALSE
299 #endif
300#endif
301
302#if (OPTION_FAMILY15H == TRUE)
303 #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
304 #undef OPTION_FAMILY15H
305 #define OPTION_FAMILY15H FALSE
306 #endif
307#endif
308
309
310/* Check for invalid combinations of socket/family */
311#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
312 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
313 #error No G34 supported families included in the build
314 #endif
315#endif
316
317#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
318 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
319 #error No C32 supported families included in the build
320 #endif
321#endif
322
323#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
324 #if (OPTION_FAMILY10H == FALSE)
325 #error No S1G3 supported families included in the build
326 #endif
327#endif
328
329#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
330 #if (OPTION_FAMILY10H == FALSE)
331 #error No S1G4 supported families included in the build
332 #endif
333#endif
334
335#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
336 #if (OPTION_FAMILY10H == FALSE)
337 #error No ASB2 supported families included in the build
338 #endif
339#endif
340
341#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
342 #if (OPTION_FAMILY12H == FALSE)
343 #error No FS1 supported families included in the build
344 #endif
345#endif
346
347#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
348 #if (OPTION_FAMILY12H == FALSE)
349 #error No FM1 supported families included in the build
350 #endif
351#endif
352
353#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
354 #if (OPTION_FAMILY12H == FALSE)
355 #error No FP1 supported families included in the build
356 #endif
357#endif
358
359#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
360 #if (OPTION_FAMILY14H == FALSE)
361 #error No FT1 supported families included in the build
362 #endif
363#endif
364
365#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
366 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
367 #error No AM3 supported families included in the build
368 #endif
369#endif
370
371
372/* Process AGESA private data
373 *
374 * Turn on appropriate CPU models and memory controllers,
375 * as well as some other memory controls.
376 */
377
378/* Default all models to off */
379#define OPTION_FAMILY10H_BL FALSE
380#define OPTION_FAMILY10H_DA FALSE
381#define OPTION_FAMILY10H_HY FALSE
382#define OPTION_FAMILY10H_PH FALSE
383#define OPTION_FAMILY10H_RB FALSE
384#define OPTION_FAMILY12H_LN FALSE
385#define OPTION_FAMILY14H_ON FALSE
386#define OPTION_FAMILY15H_OR FALSE
387
388/* Default all memory controllers to off */
389#define OPTION_MEMCTLR_DR FALSE
390#define OPTION_MEMCTLR_HY FALSE
391#define OPTION_MEMCTLR_OR FALSE
392#define OPTION_MEMCTLR_C32 FALSE
393#define OPTION_MEMCTLR_DA FALSE
394#define OPTION_MEMCTLR_LN FALSE
395#define OPTION_MEMCTLR_ON FALSE
396#define OPTION_MEMCTLR_Ni FALSE
397#define OPTION_MEMCTLR_PH FALSE
398#define OPTION_MEMCTLR_RB FALSE
399
400/* Default all memory controls to off */
401#define OPTION_HW_WRITE_LEV_TRAINING FALSE
402#define OPTION_SW_WRITE_LEV_TRAINING FALSE
403#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
404#define OPTION_HW_DQS_REC_EN_TRAINING FALSE
405#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
406#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
407#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
408#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
409#define OPTION_MAX_RD_LAT_TRAINING FALSE
410#define OPTION_HW_DRAM_INIT FALSE
411#define OPTION_SW_DRAM_INIT FALSE
412#define OPTION_S3_MEM_SUPPORT FALSE
413#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
414
415/* Defaults for public user options */
416#define OPTION_UDIMMS FALSE
417#define OPTION_RDIMMS FALSE
418#define OPTION_SODIMMS FALSE
419#define OPTION_LRDIMMS FALSE
420#define OPTION_DDR2 FALSE
421#define OPTION_DDR3 FALSE
422#define OPTION_ECC FALSE
423#define OPTION_BANK_INTERLEAVE FALSE
424#define OPTION_DCT_INTERLEAVE FALSE
425#define OPTION_NODE_INTERLEAVE FALSE
426#define OPTION_PARALLEL_TRAINING FALSE
427#define OPTION_ONLINE_SPARE FALSE
428#define OPTION_MEM_RESTORE FALSE
429#define OPTION_DIMM_EXCLUDE FALSE
430
431/* Default all CPU controls to off */
432#define OPTION_MULTISOCKET FALSE
433#define OPTION_SRAT FALSE
434#define OPTION_SLIT FALSE
435#define OPTION_HT_ASSIST FALSE
436#define OPTION_ATM_MODE FALSE
437#define OPTION_CPU_CORELEVLING FALSE
438#define OPTION_MSG_BASED_C1E FALSE
439#define OPTION_CPU_CFOH FALSE
440#define OPTION_C6_STATE FALSE
441#define OPTION_IO_CSTATE FALSE
442#define OPTION_CPB FALSE
443#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
444#define OPTION_S3SCRIPT FALSE
445#define OPTION_GFX_RECOVERY FALSE
446
447/* Enable all private controls based on socket/family enables */
448#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
449 #if (OPTION_FAMILY10H == TRUE)
450 #undef OPTION_FAMILY10H_HY
451 #define OPTION_FAMILY10H_HY TRUE
452 #undef OPTION_MEMCTLR_HY
453 #define OPTION_MEMCTLR_HY TRUE
454 #undef OPTION_HW_WRITE_LEV_TRAINING
455 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
456 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
457 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
458 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
459 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
460 #undef OPTION_MAX_RD_LAT_TRAINING
461 #define OPTION_MAX_RD_LAT_TRAINING TRUE
462 #undef OPTION_SW_DRAM_INIT
463 #define OPTION_SW_DRAM_INIT TRUE
464 #undef OPTION_S3_MEM_SUPPORT
465 #define OPTION_S3_MEM_SUPPORT TRUE
466 #undef OPTION_MULTISOCKET
467 #define OPTION_MULTISOCKET TRUE
468 #undef OPTION_SRAT
469 #define OPTION_SRAT TRUE
470 #undef OPTION_SLIT
471 #define OPTION_SLIT TRUE
472 #undef OPTION_HT_ASSIST
473 #define OPTION_HT_ASSIST TRUE
474 #undef OPTION_CPU_CORELEVLING
475 #define OPTION_CPU_CORELEVLING TRUE
476 #undef OPTION_MSG_BASED_C1E
477 #define OPTION_MSG_BASED_C1E TRUE
478 #undef OPTION_CPU_CFOH
479 #define OPTION_CPU_CFOH TRUE
480 #undef OPTION_UDIMMS
481 #define OPTION_UDIMMS TRUE
482 #undef OPTION_RDIMMS
483 #define OPTION_RDIMMS TRUE
484 #undef OPTION_SODIMMS
485 #define OPTION_SODIMMS TRUE
486 #undef OPTION_DDR3
487 #define OPTION_DDR3 TRUE
488 #undef OPTION_ECC
489 #define OPTION_ECC TRUE
490 #undef OPTION_BANK_INTERLEAVE
491 #define OPTION_BANK_INTERLEAVE TRUE
492 #undef OPTION_DCT_INTERLEAVE
493 #define OPTION_DCT_INTERLEAVE TRUE
494 #undef OPTION_NODE_INTERLEAVE
495 #define OPTION_NODE_INTERLEAVE TRUE
496 #undef OPTION_PARALLEL_TRAINING
497 #define OPTION_PARALLEL_TRAINING TRUE
498 #undef OPTION_MEM_RESTORE
499 #define OPTION_MEM_RESTORE TRUE
500 #undef OPTION_ONLINE_SPARE
501 #define OPTION_ONLINE_SPARE TRUE
502 #undef OPTION_DIMM_EXCLUDE
503 #define OPTION_DIMM_EXCLUDE TRUE
504 #endif
505 #if (OPTION_FAMILY15H == TRUE)
506 #undef OPTION_FAMILY15H_OR
507 #define OPTION_FAMILY15H_OR TRUE
508 #undef OPTION_MEMCTLR_OR
509 #define OPTION_MEMCTLR_OR TRUE
510 #undef OPTION_HW_WRITE_LEV_TRAINING
511 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
512 #undef OPTION_CONTINOUS_PATTERN_GENERATION
513 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
514 #undef OPTION_HW_DQS_REC_EN_TRAINING
515 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
516 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
517 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
518 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
519 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
520 #undef OPTION_MAX_RD_LAT_TRAINING
521 #define OPTION_MAX_RD_LAT_TRAINING TRUE
522 #undef OPTION_SW_DRAM_INIT
523 #define OPTION_SW_DRAM_INIT TRUE
524 #undef OPTION_S3_MEM_SUPPORT
525 #define OPTION_S3_MEM_SUPPORT TRUE
526 #undef OPTION_MULTISOCKET
527 #define OPTION_MULTISOCKET TRUE
528 #undef OPTION_C6_STATE
529 #define OPTION_C6_STATE TRUE
530 #undef OPTION_IO_CSTATE
531 #define OPTION_IO_CSTATE TRUE
532 #undef OPTION_CPB
533 #define OPTION_CPB TRUE
534 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
535 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
536 #undef OPTION_SRAT
537 #define OPTION_SRAT TRUE
538 #undef OPTION_SLIT
539 #define OPTION_SLIT TRUE
540 #undef OPTION_HT_ASSIST
541 #define OPTION_HT_ASSIST TRUE
542 #undef OPTION_ATM_MODE
543 #define OPTION_ATM_MODE TRUE
544 #undef OPTION_CPU_CORELEVLING
545 #define OPTION_CPU_CORELEVLING TRUE
546 #undef OPTION_MSG_BASED_C1E
547 #define OPTION_MSG_BASED_C1E TRUE
548 #undef OPTION_CPU_CFOH
549 #define OPTION_CPU_CFOH TRUE
550 #undef OPTION_UDIMMS
551 #define OPTION_UDIMMS TRUE
552 #undef OPTION_RDIMMS
553 #define OPTION_RDIMMS TRUE
554 #undef OPTION_SODIMMS
555 #define OPTION_SODIMMS TRUE
556 #undef OPTION_LRDIMMS
557 #define OPTION_LRDIMMS TRUE
558 #undef OPTION_DDR3
559 #define OPTION_DDR3 TRUE
560 #undef OPTION_ECC
561 #define OPTION_ECC TRUE
562 #undef OPTION_BANK_INTERLEAVE
563 #define OPTION_BANK_INTERLEAVE TRUE
564 #undef OPTION_DCT_INTERLEAVE
565 #define OPTION_DCT_INTERLEAVE TRUE
566 #undef OPTION_NODE_INTERLEAVE
567 #define OPTION_NODE_INTERLEAVE TRUE
568 #undef OPTION_MEM_RESTORE
569 #define OPTION_MEM_RESTORE TRUE
570 #undef OPTION_ONLINE_SPARE
571 #define OPTION_ONLINE_SPARE TRUE
572 #undef OPTION_DIMM_EXCLUDE
573 #define OPTION_DIMM_EXCLUDE TRUE
574 #endif
575#endif
576
577#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
578 #if (OPTION_FAMILY10H == TRUE)
579 #undef OPTION_FAMILY10H_HY
580 #define OPTION_FAMILY10H_HY TRUE
581 #undef OPTION_MEMCTLR_C32
582 #define OPTION_MEMCTLR_C32 TRUE
583 #undef OPTION_HW_WRITE_LEV_TRAINING
584 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
585 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
586 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
587 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
588 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
589 #undef OPTION_MAX_RD_LAT_TRAINING
590 #define OPTION_MAX_RD_LAT_TRAINING TRUE
591 #undef OPTION_SW_DRAM_INIT
592 #define OPTION_SW_DRAM_INIT TRUE
593 #undef OPTION_S3_MEM_SUPPORT
594 #define OPTION_S3_MEM_SUPPORT TRUE
595 #undef OPTION_ADDR_TO_CS_TRANSLATOR
596 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
597 #undef OPTION_MULTISOCKET
598 #define OPTION_MULTISOCKET TRUE
599 #undef OPTION_SRAT
600 #define OPTION_SRAT TRUE
601 #undef OPTION_SLIT
602 #define OPTION_SLIT TRUE
603 #undef OPTION_HT_ASSIST
604 #define OPTION_HT_ASSIST TRUE
605 #undef OPTION_CPU_CORELEVLING
606 #define OPTION_CPU_CORELEVLING TRUE
607 #undef OPTION_MSG_BASED_C1E
608 #define OPTION_MSG_BASED_C1E TRUE
609 #undef OPTION_CPU_CFOH
610 #define OPTION_CPU_CFOH TRUE
611 #undef OPTION_UDIMMS
612 #define OPTION_UDIMMS TRUE
613 #undef OPTION_RDIMMS
614 #define OPTION_RDIMMS TRUE
615 #undef OPTION_SODIMMS
616 #define OPTION_SODIMMS TRUE
617 #undef OPTION_DDR3
618 #define OPTION_DDR3 TRUE
619 #undef OPTION_ECC
620 #define OPTION_ECC TRUE
621 #undef OPTION_BANK_INTERLEAVE
622 #define OPTION_BANK_INTERLEAVE TRUE
623 #undef OPTION_DCT_INTERLEAVE
624 #define OPTION_DCT_INTERLEAVE TRUE
625 #undef OPTION_NODE_INTERLEAVE
626 #define OPTION_NODE_INTERLEAVE TRUE
627 #undef OPTION_PARALLEL_TRAINING
628 #define OPTION_PARALLEL_TRAINING TRUE
629 #undef OPTION_MEM_RESTORE
630 #define OPTION_MEM_RESTORE TRUE
631 #undef OPTION_ONLINE_SPARE
632 #define OPTION_ONLINE_SPARE TRUE
633 #undef OPTION_DIMM_EXCLUDE
634 #define OPTION_DIMM_EXCLUDE TRUE
635 #endif
636 #if (OPTION_FAMILY15H == TRUE)
637 #undef OPTION_FAMILY15H_OR
638 #define OPTION_FAMILY15H_OR TRUE
639 #undef OPTION_MEMCTLR_OR
640 #define OPTION_MEMCTLR_OR TRUE
641 #undef OPTION_HW_WRITE_LEV_TRAINING
642 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
643 #undef OPTION_CONTINOUS_PATTERN_GENERATION
644 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
645 #undef OPTION_HW_DQS_REC_EN_TRAINING
646 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
647 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
648 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
649 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
650 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
651 #undef OPTION_MAX_RD_LAT_TRAINING
652 #define OPTION_MAX_RD_LAT_TRAINING TRUE
653 #undef OPTION_SW_DRAM_INIT
654 #define OPTION_SW_DRAM_INIT TRUE
655 #undef OPTION_S3_MEM_SUPPORT
656 #define OPTION_S3_MEM_SUPPORT TRUE
657 #undef OPTION_ADDR_TO_CS_TRANSLATOR
658 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
659 #undef OPTION_MULTISOCKET
660 #define OPTION_MULTISOCKET TRUE
661 #undef OPTION_C6_STATE
662 #define OPTION_C6_STATE TRUE
663 #undef OPTION_IO_CSTATE
664 #define OPTION_IO_CSTATE TRUE
665 #undef OPTION_CPB
666 #define OPTION_CPB TRUE
667 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
668 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
669 #undef OPTION_SRAT
670 #define OPTION_SRAT TRUE
671 #undef OPTION_SLIT
672 #define OPTION_SLIT TRUE
673 #undef OPTION_HT_ASSIST
674 #define OPTION_HT_ASSIST TRUE
675 #undef OPTION_ATM_MODE
676 #define OPTION_ATM_MODE TRUE
677 #undef OPTION_CPU_CORELEVLING
678 #define OPTION_CPU_CORELEVLING TRUE
679 #undef OPTION_MSG_BASED_C1E
680 #define OPTION_MSG_BASED_C1E TRUE
681 #undef OPTION_CPU_CFOH
682 #define OPTION_CPU_CFOH TRUE
683 #undef OPTION_UDIMMS
684 #define OPTION_UDIMMS TRUE
685 #undef OPTION_RDIMMS
686 #define OPTION_RDIMMS TRUE
687 #undef OPTION_SODIMMS
688 #define OPTION_SODIMMS TRUE
689 #undef OPTION_LRDIMMS
690 #define OPTION_LRDIMMS TRUE
691 #undef OPTION_DDR3
692 #define OPTION_DDR3 TRUE
693 #undef OPTION_ECC
694 #define OPTION_ECC TRUE
695 #undef OPTION_BANK_INTERLEAVE
696 #define OPTION_BANK_INTERLEAVE TRUE
697 #undef OPTION_DCT_INTERLEAVE
698 #define OPTION_DCT_INTERLEAVE TRUE
699 #undef OPTION_NODE_INTERLEAVE
700 #define OPTION_NODE_INTERLEAVE TRUE
701 #undef OPTION_MEM_RESTORE
702 #define OPTION_MEM_RESTORE TRUE
703 #undef OPTION_ONLINE_SPARE
704 #define OPTION_ONLINE_SPARE TRUE
705 #undef OPTION_DIMM_EXCLUDE
706 #define OPTION_DIMM_EXCLUDE TRUE
707 #endif
708#endif
709
710#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
711 #if (OPTION_FAMILY10H == TRUE)
712 #undef OPTION_FAMILY10H_BL
713 #define OPTION_FAMILY10H_BL TRUE
714 #undef OPTION_FAMILY10H_DA
715 #define OPTION_FAMILY10H_DA TRUE
716 #undef OPTION_MEMCTLR_DA
717 #define OPTION_MEMCTLR_DA TRUE
718 #undef OPTION_HW_WRITE_LEV_TRAINING
719 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
720 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
721 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
722 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
723 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
724 #undef OPTION_MAX_RD_LAT_TRAINING
725 #define OPTION_MAX_RD_LAT_TRAINING TRUE
726 #undef OPTION_SW_DRAM_INIT
727 #define OPTION_SW_DRAM_INIT TRUE
728 #undef OPTION_S3_MEM_SUPPORT
729 #define OPTION_S3_MEM_SUPPORT TRUE
730 #undef OPTION_CPU_CORELEVLING
731 #define OPTION_CPU_CORELEVLING TRUE
732 #undef OPTION_CPU_CFOH
733 #define OPTION_CPU_CFOH TRUE
734 #undef OPTION_UDIMMS
735 #define OPTION_UDIMMS TRUE
736 #undef OPTION_SODIMMS
737 #define OPTION_SODIMMS TRUE
738 #undef OPTION_DDR3
739 #define OPTION_DDR3 TRUE
740 #undef OPTION_ECC
741 #define OPTION_ECC TRUE
742 #undef OPTION_BANK_INTERLEAVE
743 #define OPTION_BANK_INTERLEAVE TRUE
744 #undef OPTION_DCT_INTERLEAVE
745 #define OPTION_DCT_INTERLEAVE TRUE
746 #undef OPTION_NODE_INTERLEAVE
747 #define OPTION_NODE_INTERLEAVE TRUE
748 #undef OPTION_PARALLEL_TRAINING
749 #define OPTION_PARALLEL_TRAINING TRUE
750 #undef OPTION_MEM_RESTORE
751 #define OPTION_MEM_RESTORE TRUE
752 #undef OPTION_ONLINE_SPARE
753 #define OPTION_ONLINE_SPARE TRUE
754 #undef OPTION_DIMM_EXCLUDE
755 #define OPTION_DIMM_EXCLUDE TRUE
756 #endif
757#endif
758
759#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
760 #if (OPTION_FAMILY10H == TRUE)
761 #undef OPTION_FAMILY10H_BL
762 #define OPTION_FAMILY10H_BL TRUE
763 #undef OPTION_FAMILY10H_DA
764 #define OPTION_FAMILY10H_DA TRUE
765 #undef OPTION_MEMCTLR_DA
766 #define OPTION_MEMCTLR_DA TRUE
767 #undef OPTION_HW_WRITE_LEV_TRAINING
768 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
769 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
770 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
771 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
772 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
773 #undef OPTION_MAX_RD_LAT_TRAINING
774 #define OPTION_MAX_RD_LAT_TRAINING TRUE
775 #undef OPTION_SW_DRAM_INIT
776 #define OPTION_SW_DRAM_INIT TRUE
777 #undef OPTION_S3_MEM_SUPPORT
778 #define OPTION_S3_MEM_SUPPORT TRUE
779 #undef OPTION_CPU_CORELEVLING
780 #define OPTION_CPU_CORELEVLING TRUE
781 #undef OPTION_CPU_CFOH
782 #define OPTION_CPU_CFOH TRUE
783 #undef OPTION_UDIMMS
784 #define OPTION_UDIMMS TRUE
785 #undef OPTION_SODIMMS
786 #define OPTION_SODIMMS TRUE
787 #undef OPTION_DDR3
788 #define OPTION_DDR3 TRUE
789 #undef OPTION_ECC
790 #define OPTION_ECC TRUE
791 #undef OPTION_BANK_INTERLEAVE
792 #define OPTION_BANK_INTERLEAVE TRUE
793 #undef OPTION_DCT_INTERLEAVE
794 #define OPTION_DCT_INTERLEAVE TRUE
795 #undef OPTION_NODE_INTERLEAVE
796 #define OPTION_NODE_INTERLEAVE TRUE
797 #undef OPTION_MEM_RESTORE
798 #define OPTION_MEM_RESTORE TRUE
799 #undef OPTION_DIMM_EXCLUDE
800 #define OPTION_DIMM_EXCLUDE TRUE
801 #endif
802#endif
803
804#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
805 #if (OPTION_FAMILY10H == TRUE)
806 #undef OPTION_FAMILY10H_BL
807 #define OPTION_FAMILY10H_BL TRUE
808 #undef OPTION_FAMILY10H_DA
809 #define OPTION_FAMILY10H_DA TRUE
810 #undef OPTION_MEMCTLR_Ni
811 #define OPTION_MEMCTLR_Ni TRUE
812 #undef OPTION_HW_WRITE_LEV_TRAINING
813 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
814 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
815 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
816 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
817 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
818 #undef OPTION_MAX_RD_LAT_TRAINING
819 #define OPTION_MAX_RD_LAT_TRAINING TRUE
820 #undef OPTION_SW_DRAM_INIT
821 #define OPTION_SW_DRAM_INIT TRUE
822 #undef OPTION_S3_MEM_SUPPORT
823 #define OPTION_S3_MEM_SUPPORT TRUE
824 #undef OPTION_CPU_CORELEVLING
825 #define OPTION_CPU_CORELEVLING TRUE
826 #undef OPTION_CPU_CFOH
827 #define OPTION_CPU_CFOH TRUE
828 #undef OPTION_UDIMMS
829 #define OPTION_UDIMMS TRUE
830 #undef OPTION_SODIMMS
831 #define OPTION_SODIMMS TRUE
832 #undef OPTION_DDR3
833 #define OPTION_DDR3 TRUE
834 #undef OPTION_ECC
835 #define OPTION_ECC TRUE
836 #undef OPTION_BANK_INTERLEAVE
837 #define OPTION_BANK_INTERLEAVE TRUE
838 #undef OPTION_DCT_INTERLEAVE
839 #define OPTION_DCT_INTERLEAVE TRUE
840 #undef OPTION_NODE_INTERLEAVE
841 #define OPTION_NODE_INTERLEAVE TRUE
842 #undef OPTION_MEM_RESTORE
843 #define OPTION_MEM_RESTORE TRUE
844 #undef OPTION_DIMM_EXCLUDE
845 #define OPTION_DIMM_EXCLUDE TRUE
846 #endif
847#endif
848
849#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
850 #if (OPTION_FAMILY12H == TRUE)
851 #undef OPTION_FAMILY12H_LN
852 #define OPTION_FAMILY12H_LN TRUE
853 #undef OPTION_MEMCTLR_LN
854 #define OPTION_MEMCTLR_LN TRUE
855 #undef OPTION_HW_WRITE_LEV_TRAINING
856 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
857 #undef OPTION_CONTINOUS_PATTERN_GENERATION
858 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
859 #undef OPTION_HW_DQS_REC_EN_TRAINING
860 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
861 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
862 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
863 #undef OPTION_MAX_RD_LAT_TRAINING
864 #define OPTION_MAX_RD_LAT_TRAINING TRUE
865 #undef OPTION_SW_DRAM_INIT
866 #define OPTION_SW_DRAM_INIT TRUE
867 #undef OPTION_S3_MEM_SUPPORT
868 #define OPTION_S3_MEM_SUPPORT TRUE
869 #undef OPTION_GFX_RECOVERY
870 #define OPTION_GFX_RECOVERY TRUE
871 #undef OPTION_C6_STATE
872 #define OPTION_C6_STATE TRUE
873 #undef OPTION_IO_CSTATE
874 #define OPTION_IO_CSTATE TRUE
875 #undef OPTION_CPB
876 #define OPTION_CPB TRUE
877 #undef OPTION_S3SCRIPT
878 #define OPTION_S3SCRIPT TRUE
879 #undef OPTION_UDIMMS
880 #define OPTION_UDIMMS TRUE
881 #undef OPTION_SODIMMS
882 #define OPTION_SODIMMS TRUE
883 #undef OPTION_DDR3
884 #define OPTION_DDR3 TRUE
885 #undef OPTION_BANK_INTERLEAVE
886 #define OPTION_BANK_INTERLEAVE TRUE
887 #undef OPTION_DCT_INTERLEAVE
888 #define OPTION_DCT_INTERLEAVE TRUE
889 #undef OPTION_MEM_RESTORE
890 #define OPTION_MEM_RESTORE TRUE
891 #undef OPTION_DIMM_EXCLUDE
892 #define OPTION_DIMM_EXCLUDE TRUE
893 #endif
894#endif
895
896#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
897 #if (OPTION_FAMILY12H == TRUE)
898 #undef OPTION_FAMILY12H_LN
899 #define OPTION_FAMILY12H_LN TRUE
900 #undef OPTION_MEMCTLR_LN
901 #define OPTION_MEMCTLR_LN TRUE
902 #undef OPTION_HW_WRITE_LEV_TRAINING
903 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
904 #undef OPTION_CONTINOUS_PATTERN_GENERATION
905 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
906 #undef OPTION_HW_DQS_REC_EN_TRAINING
907 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
908 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
909 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
910 #undef OPTION_MAX_RD_LAT_TRAINING
911 #define OPTION_MAX_RD_LAT_TRAINING TRUE
912 #undef OPTION_SW_DRAM_INIT
913 #define OPTION_SW_DRAM_INIT TRUE
914 #undef OPTION_S3_MEM_SUPPORT
915 #define OPTION_S3_MEM_SUPPORT TRUE
916 #undef OPTION_GFX_RECOVERY
917 #define OPTION_GFX_RECOVERY TRUE
918 #undef OPTION_C6_STATE
919 #define OPTION_C6_STATE TRUE
920 #undef OPTION_IO_CSTATE
921 #define OPTION_IO_CSTATE TRUE
922 #undef OPTION_CPB
923 #define OPTION_CPB TRUE
924 #undef OPTION_S3SCRIPT
925 #define OPTION_S3SCRIPT TRUE
926 #undef OPTION_UDIMMS
927 #define OPTION_UDIMMS TRUE
928 #undef OPTION_SODIMMS
929 #define OPTION_SODIMMS TRUE
930 #undef OPTION_DDR3
931 #define OPTION_DDR3 TRUE
932 #undef OPTION_BANK_INTERLEAVE
933 #define OPTION_BANK_INTERLEAVE TRUE
934 #undef OPTION_DCT_INTERLEAVE
935 #define OPTION_DCT_INTERLEAVE TRUE
936 #undef OPTION_MEM_RESTORE
937 #define OPTION_MEM_RESTORE TRUE
938 #undef OPTION_DIMM_EXCLUDE
939 #define OPTION_DIMM_EXCLUDE TRUE
940 #endif
941#endif
942
943#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
944 #if (OPTION_FAMILY12H == TRUE)
945 #undef OPTION_FAMILY12H_LN
946 #define OPTION_FAMILY12H_LN TRUE
947 #undef OPTION_MEMCTLR_LN
948 #define OPTION_MEMCTLR_LN TRUE
949 #undef OPTION_HW_WRITE_LEV_TRAINING
950 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
951 #undef OPTION_CONTINOUS_PATTERN_GENERATION
952 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
953 #undef OPTION_HW_DQS_REC_EN_TRAINING
954 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
955 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
956 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
957 #undef OPTION_MAX_RD_LAT_TRAINING
958 #define OPTION_MAX_RD_LAT_TRAINING TRUE
959 #undef OPTION_SW_DRAM_INIT
960 #define OPTION_SW_DRAM_INIT TRUE
961 #undef OPTION_S3_MEM_SUPPORT
962 #define OPTION_S3_MEM_SUPPORT TRUE
963 #undef OPTION_ADDR_TO_CS_TRANSLATOR
964 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
965 #undef OPTION_GFX_RECOVERY
966 #define OPTION_GFX_RECOVERY TRUE
967 #undef OPTION_C6_STATE
968 #define OPTION_C6_STATE TRUE
969 #undef OPTION_IO_CSTATE
970 #define OPTION_IO_CSTATE TRUE
971 #undef OPTION_CPB
972 #define OPTION_CPB TRUE
973 #undef OPTION_S3SCRIPT
974 #define OPTION_S3SCRIPT TRUE
975 #undef OPTION_UDIMMS
976 #define OPTION_UDIMMS TRUE
977 #undef OPTION_SODIMMS
978 #define OPTION_SODIMMS TRUE
979 #undef OPTION_DDR3
980 #define OPTION_DDR3 TRUE
981 #undef OPTION_BANK_INTERLEAVE
982 #define OPTION_BANK_INTERLEAVE TRUE
983 #undef OPTION_DCT_INTERLEAVE
984 #define OPTION_DCT_INTERLEAVE TRUE
985 #undef OPTION_MEM_RESTORE
986 #define OPTION_MEM_RESTORE TRUE
987 #undef OPTION_ONLINE_SPARE
988 #define OPTION_ONLINE_SPARE TRUE
989 #undef OPTION_DIMM_EXCLUDE
990 #define OPTION_DIMM_EXCLUDE TRUE
991 #endif
992#endif
993
994#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
995 #if (OPTION_FAMILY14H == TRUE)
996 #undef OPTION_FAMILY14H_ON
997 #define OPTION_FAMILY14H_ON TRUE
998 #undef OPTION_MEMCTLR_ON
999 #define OPTION_MEMCTLR_ON TRUE
1000 #undef OPTION_HW_WRITE_LEV_TRAINING
1001 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1002 #undef OPTION_CONTINOUS_PATTERN_GENERATION
1003 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
1004 #undef OPTION_MAX_RD_LAT_TRAINING
1005 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1006 #undef OPTION_HW_DQS_REC_EN_TRAINING
1007 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
1008 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1009 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1010 #undef OPTION_SW_DRAM_INIT
1011 #define OPTION_SW_DRAM_INIT TRUE
1012 #undef OPTION_S3_MEM_SUPPORT
1013 #define OPTION_S3_MEM_SUPPORT TRUE
1014 #undef OPTION_GFX_RECOVERY
1015 #define OPTION_GFX_RECOVERY TRUE
1016 #undef OPTION_C6_STATE
1017 #define OPTION_C6_STATE TRUE
1018 #undef OPTION_IO_CSTATE
1019 #define OPTION_IO_CSTATE TRUE
1020 #undef OPTION_S3SCRIPT
1021 #define OPTION_S3SCRIPT TRUE
1022 #undef OPTION_UDIMMS
1023 #define OPTION_UDIMMS TRUE
1024 #undef OPTION_SODIMMS
1025 #define OPTION_SODIMMS TRUE
1026 #undef OPTION_DDR3
1027 #define OPTION_DDR3 TRUE
1028 #undef OPTION_BANK_INTERLEAVE
1029 #define OPTION_BANK_INTERLEAVE TRUE
1030 #undef OPTION_MEM_RESTORE
1031 #define OPTION_MEM_RESTORE TRUE
1032 #undef OPTION_DIMM_EXCLUDE
1033 #define OPTION_DIMM_EXCLUDE TRUE
1034 #endif
1035#endif
1036
1037#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
1038 #if (OPTION_FAMILY10H == TRUE)
1039 #undef OPTION_FAMILY10H_BL
1040 #define OPTION_FAMILY10H_BL TRUE
1041 #undef OPTION_FAMILY10H_DA
1042 #define OPTION_FAMILY10H_DA TRUE
1043 #undef OPTION_FAMILY10H_PH
1044 #define OPTION_FAMILY10H_PH TRUE
1045 #undef OPTION_FAMILY10H_RB
1046 #define OPTION_FAMILY10H_RB TRUE
1047 #undef OPTION_MEMCTLR_RB
1048 #define OPTION_MEMCTLR_RB TRUE
1049 #undef OPTION_MEMCTLR_DA
1050 #define OPTION_MEMCTLR_DA TRUE
1051 #undef OPTION_MEMCTLR_PH
1052 #define OPTION_MEMCTLR_PH TRUE
1053 #undef OPTION_HW_WRITE_LEV_TRAINING
1054 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1055 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
1056 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
1057 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1058 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1059 #undef OPTION_MAX_RD_LAT_TRAINING
1060 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1061 #undef OPTION_SW_DRAM_INIT
1062 #define OPTION_SW_DRAM_INIT TRUE
1063 #undef OPTION_S3_MEM_SUPPORT
1064 #define OPTION_S3_MEM_SUPPORT TRUE
1065 #undef OPTION_CPU_CORELEVLING
1066 #define OPTION_CPU_CORELEVLING TRUE
1067 #undef OPTION_CPU_CFOH
1068 #define OPTION_CPU_CFOH TRUE
1069 #undef OPTION_IO_CSTATE
1070 #define OPTION_IO_CSTATE TRUE
1071 #undef OPTION_CPB
1072 #define OPTION_CPB TRUE
1073 #undef OPTION_UDIMMS
1074 #define OPTION_UDIMMS TRUE
1075 #undef OPTION_SODIMMS
1076 #define OPTION_SODIMMS TRUE
1077 #undef OPTION_DDR3
1078 #define OPTION_DDR3 TRUE
1079 #undef OPTION_ECC
1080 #define OPTION_ECC TRUE
1081 #undef OPTION_BANK_INTERLEAVE
1082 #define OPTION_BANK_INTERLEAVE TRUE
1083 #undef OPTION_DCT_INTERLEAVE
1084 #define OPTION_DCT_INTERLEAVE TRUE
1085 #undef OPTION_NODE_INTERLEAVE
1086 #define OPTION_NODE_INTERLEAVE TRUE
1087 #undef OPTION_PARALLEL_TRAINING
1088 #define OPTION_PARALLEL_TRAINING TRUE
1089 #undef OPTION_MEM_RESTORE
1090 #define OPTION_MEM_RESTORE TRUE
1091 #undef OPTION_ONLINE_SPARE
1092 #define OPTION_ONLINE_SPARE TRUE
1093 #undef OPTION_DIMM_EXCLUDE
1094 #define OPTION_DIMM_EXCLUDE TRUE
1095 #endif
1096 #if (OPTION_FAMILY15H == TRUE)
1097 #undef OPTION_FAMILY15H_OR
1098 #define OPTION_FAMILY15H_OR TRUE
1099 #undef OPTION_MEMCTLR_OR
1100 #define OPTION_MEMCTLR_OR TRUE
1101 #undef OPTION_HW_WRITE_LEV_TRAINING
1102 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1103 #undef OPTION_CONTINOUS_PATTERN_GENERATION
1104 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
1105 #undef OPTION_HW_DQS_REC_EN_TRAINING
1106 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
1107 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1108 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1109 #undef OPTION_MAX_RD_LAT_TRAINING
1110 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1111 #undef OPTION_SW_DRAM_INIT
1112 #define OPTION_SW_DRAM_INIT TRUE
1113 #undef OPTION_C6_STATE
1114 #define OPTION_C6_STATE TRUE
1115 #undef OPTION_IO_CSTATE
1116 #define OPTION_IO_CSTATE TRUE
1117 #undef OPTION_CPB
1118 #define OPTION_CPB TRUE
1119 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
1120 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
1121 #undef OPTION_S3_MEM_SUPPORT
1122 #define OPTION_S3_MEM_SUPPORT TRUE
1123 #undef OPTION_ADDR_TO_CS_TRANSLATOR
1124 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
1125 #undef OPTION_CPU_CORELEVLING
1126 #define OPTION_CPU_CORELEVLING TRUE
1127 #undef OPTION_CPU_CFOH
1128 #define OPTION_CPU_CFOH TRUE
1129 #undef OPTION_MSG_BASED_C1E
1130 #define OPTION_MSG_BASED_C1E TRUE
1131 #undef OPTION_UDIMMS
1132 #define OPTION_UDIMMS TRUE
1133 #undef OPTION_RDIMMS
1134 #define OPTION_RDIMMS TRUE
1135 #undef OPTION_LRDIMMS
1136 #define OPTION_LRDIMMS TRUE
1137 #undef OPTION_SODIMMS
1138 #define OPTION_SODIMMS TRUE
1139 #undef OPTION_DDR3
1140 #define OPTION_DDR3 TRUE
1141 #undef OPTION_ECC
1142 #define OPTION_ECC TRUE
1143 #undef OPTION_BANK_INTERLEAVE
1144 #define OPTION_BANK_INTERLEAVE TRUE
1145 #undef OPTION_DCT_INTERLEAVE
1146 #define OPTION_DCT_INTERLEAVE TRUE
1147 #undef OPTION_NODE_INTERLEAVE
1148 #define OPTION_NODE_INTERLEAVE TRUE
1149 #undef OPTION_MEM_RESTORE
1150 #define OPTION_MEM_RESTORE TRUE
1151 #undef OPTION_ONLINE_SPARE
1152 #define OPTION_ONLINE_SPARE TRUE
1153 #undef OPTION_DIMM_EXCLUDE
1154 #define OPTION_DIMM_EXCLUDE TRUE
1155 #endif
1156#endif
1157
1158#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
1159 #undef GNB_SUPPORT
1160 #define GNB_SUPPORT TRUE
1161#endif
1162
1163#define OPTION_ACPI_PSTATES TRUE
1164#define OPTION_WHEA TRUE
1165#define OPTION_DMI TRUE
1166#define OPTION_EARLY_SAMPLES FALSE
1167#define CFG_ACPI_PSTATES_PPC TRUE
1168#define CFG_ACPI_PSTATES_PCT TRUE
1169#define CFG_ACPI_PSTATES_PSD TRUE
1170#define CFG_ACPI_PSTATES_PSS TRUE
1171#define CFG_ACPI_PSTATES_XPSS TRUE
1172#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
1173#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
1174#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
1175#define OPTION_ALIB TRUE
1176/*---------------------------------------------------------------------------
1177 * Processing the options: Second, process the user's selections
1178 *--------------------------------------------------------------------------*/
1179#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
1180 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
1181 #undef OPTION_MULTISOCKET
1182 #define OPTION_MULTISOCKET FALSE
1183 #endif
1184#endif
1185#ifdef BLDOPT_REMOVE_ECC_SUPPORT
1186 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
1187 #undef OPTION_ECC
1188 #define OPTION_ECC FALSE
1189 #endif
1190#endif
1191#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
1192 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
1193 #undef OPTION_UDIMMS
1194 #define OPTION_UDIMMS FALSE
1195 #endif
1196#endif
1197#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
1198 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
1199 #undef OPTION_RDIMMS
1200 #define OPTION_RDIMMS FALSE
1201 #endif
1202#endif
1203#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
1204 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
1205 #undef OPTION_SODIMMS
1206 #define OPTION_SODIMMS FALSE
1207 #endif
1208#endif
1209#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
1210 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
1211 #undef OPTION_LRDIMMS
1212 #define OPTION_LRDIMMS FALSE
1213 #endif
1214#endif
1215#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
1216 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
1217 #undef OPTION_BANK_INTERLEAVE
1218 #define OPTION_BANK_INTERLEAVE FALSE
1219 #endif
1220#endif
1221#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
1222 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
1223 #undef OPTION_DCT_INTERLEAVE
1224 #define OPTION_DCT_INTERLEAVE FALSE
1225 #endif
1226#endif
1227#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
1228 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
1229 #undef OPTION_NODE_INTERLEAVE
1230 #define OPTION_NODE_INTERLEAVE FALSE
1231 #endif
1232#endif
1233#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
1234 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
1235 #undef OPTION_PARALLEL_TRAINING
1236 #define OPTION_PARALLEL_TRAINING FALSE
1237 #endif
1238#endif
1239#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
1240 #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
1241 #undef OPTION_ONLINE_SPARE
1242 #define OPTION_ONLINE_SPARE FALSE
1243 #endif
1244#endif
1245#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
1246 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
1247 #undef OPTION_MEM_RESTORE
1248 #define OPTION_MEM_RESTORE FALSE
1249 #endif
1250#endif
1251#ifdef BLDOPT_REMOVE_ACPI_PSTATES
1252 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
1253 #undef OPTION_ACPI_PSTATES
1254 #define OPTION_ACPI_PSTATES FALSE
1255 #endif
1256#endif
1257#ifdef BLDOPT_REMOVE_SRAT
1258 #if BLDOPT_REMOVE_SRAT == TRUE
1259 #undef OPTION_SRAT
1260 #define OPTION_SRAT FALSE
1261 #endif
1262#endif
1263#ifdef BLDOPT_REMOVE_SLIT
1264 #if BLDOPT_REMOVE_SLIT == TRUE
1265 #undef OPTION_SLIT
1266 #define OPTION_SLIT FALSE
1267 #endif
1268#endif
1269#ifdef BLDOPT_REMOVE_WHEA
1270 #if BLDOPT_REMOVE_WHEA == TRUE
1271 #undef OPTION_WHEA
1272 #define OPTION_WHEA FALSE
1273 #endif
1274#endif
1275#ifdef BLDOPT_REMOVE_DMI
1276 #if BLDOPT_REMOVE_DMI == TRUE
1277 #undef OPTION_DMI
1278 #define OPTION_DMI FALSE
1279 #endif
1280#endif
1281#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
1282 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
1283 #undef OPTION_ADDR_TO_CS_TRANSLATOR
1284 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
1285 #endif
1286#endif
1287
1288#ifdef BLDOPT_REMOVE_HT_ASSIST
1289 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
1290 #undef OPTION_HT_ASSIST
1291 #define OPTION_HT_ASSIST FALSE
1292 #endif
1293#endif
1294
1295#ifdef BLDOPT_REMOVE_ATM_MODE
1296 #if BLDOPT_REMOVE_ATM_MODE == TRUE
1297 #undef OPTION_ATM_MODE
1298 #define OPTION_ATM_MODE FALSE
1299 #endif
1300#endif
1301
1302#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
1303 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
1304 #undef OPTION_MSG_BASED_C1E
1305 #define OPTION_MSG_BASED_C1E FALSE
1306 #endif
1307#endif
1308
1309#ifdef BLDOPT_REMOVE_C6_STATE
1310 #if BLDOPT_REMOVE_C6_STATE == TRUE
1311 #undef OPTION_C6_STATE
1312 #define OPTION_C6_STATE FALSE
1313 #endif
1314#endif
1315
1316#ifdef BLDOPT_REMOVE_GFX_RECOVERY
1317 #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
1318 #undef OPTION_GFX_RECOVERY
1319 #define OPTION_GFX_RECOVERY FALSE
1320 #endif
1321#endif
1322
1323#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
1324 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
1325 #undef CFG_ACPI_PSTATES_PPC
1326 #define CFG_ACPI_PSTATES_PPC FALSE
1327 #endif
1328#endif
1329
1330#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
1331 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
1332 #undef CFG_ACPI_PSTATES_PCT
1333 #define CFG_ACPI_PSTATES_PCT FALSE
1334 #endif
1335#endif
1336
1337#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
1338 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
1339 #undef CFG_ACPI_PSTATES_PSD
1340 #define CFG_ACPI_PSTATES_PSD FALSE
1341 #endif
1342#endif
1343
1344#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
1345 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
1346 #undef CFG_ACPI_PSTATES_PSS
1347 #define CFG_ACPI_PSTATES_PSS FALSE
1348 #endif
1349#endif
1350
1351#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
1352 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
1353 #undef CFG_ACPI_PSTATES_XPSS
1354 #define CFG_ACPI_PSTATES_XPSS FALSE
1355 #endif
1356#endif
1357
1358#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
1359 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
1360 #undef CFG_ACPI_PSTATE_PSD_INDPX
1361 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
1362 #endif
1363#endif
1364
1365#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
1366 #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
1367 #undef CFG_VRM_HIGH_SPEED_ENABLE
1368 #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
1369 #endif
1370#endif
1371
1372#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
1373 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
1374 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
1375 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
1376 #endif
1377#endif
1378
1379#ifdef BLDCFG_STARTING_BUSNUM
1380 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
1381#else
1382 #define CFG_STARTING_BUSNUM (0)
1383#endif
1384
1385#ifdef BLDCFG_AMD_PLATFORM_TYPE
1386 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
1387#else
1388 #define CFG_AMD_PLATFORM_TYPE 0
1389#endif
1390
1391CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
1392
1393#ifdef BLDCFG_MAXIMUM_BUSNUM
1394 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
1395#else
1396 #define CFG_MAXIMUM_BUSNUM (0xF8)
1397#endif
1398
1399#ifdef BLDCFG_ALLOCATED_BUSNUM
1400 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
1401#else
1402 #define CFG_ALLOCATED_BUSNUM (0x20)
1403#endif
1404
1405#ifdef BLDCFG_BUID_SWAP_LIST
1406 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
1407#else
1408 #define CFG_BUID_SWAP_LIST (NULL)
1409#endif
1410
1411#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
1412 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
1413#else
1414 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
1415#endif
1416
1417#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
1418 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
1419#else
1420 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
1421#endif
1422
1423#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
1424 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
1425#else
1426 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
1427#endif
1428
1429#ifdef BLDCFG_BUS_NUMBERS_LIST
1430 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
1431#else
1432 #define CFG_BUS_NUMBERS_LIST (NULL)
1433#endif
1434
1435#ifdef BLDCFG_IGNORE_LINK_LIST
1436 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
1437#else
1438 #define CFG_IGNORE_LINK_LIST (NULL)
1439#endif
1440
1441#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
1442 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
1443#else
1444 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
1445#endif
1446
1447#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
1448 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
1449#else
1450 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
1451#endif
1452
1453#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
1454 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
1455#else
1456 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
1457#endif
1458
1459#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
1460 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
1461#else
1462 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
1463#endif
1464
1465#ifdef BLDCFG_USE_HT_ASSIST
1466 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
1467#else
1468 #define CFG_USE_HT_ASSIST (TRUE)
1469#endif
1470
1471#ifdef BLDCFG_USE_ATM_MODE
1472 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
1473#else
1474 #define CFG_USE_ATM_MODE (TRUE)
1475#endif
1476
1477#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
1478 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
1479#else
1480 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
1481#endif
1482
1483#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
1484 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
1485#else
1486 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
1487#endif
1488
1489#ifdef BLDCFG_VRM_ADDITIONAL_DELAY
1490 #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY)
1491#else
1492 #define CFG_VRM_ADDITIONAL_DELAY (0)
1493#endif
1494
1495#ifdef BLDCFG_VRM_CURRENT_LIMIT
1496 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
1497#else
1498 #define CFG_VRM_CURRENT_LIMIT 0
1499#endif
1500
1501#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
1502 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
1503#else
1504 #define CFG_VRM_LOW_POWER_THRESHOLD 0
1505#endif
1506
1507#ifdef BLDCFG_VRM_SLEW_RATE
1508 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
1509#else
1510 #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
1511#endif
1512
1513#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1514 #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1515#else
1516 #define CFG_VRM_INRUSH_CURRENT_LIMIT 0
1517#endif
1518
1519#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
1520 #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY)
1521#else
1522 #define CFG_VRM_NB_ADDITIONAL_DELAY (0)
1523#endif
1524
1525#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
1526 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
1527#else
1528 #define CFG_VRM_NB_CURRENT_LIMIT (0)
1529#endif
1530
1531#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1532 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1533#else
1534 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
1535#endif
1536
1537#ifdef BLDCFG_VRM_NB_SLEW_RATE
1538 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
1539#else
1540 #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
1541#endif
1542
1543#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1544 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1545#else
1546 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0)
1547#endif
1548
1549
1550#ifdef BLDCFG_PLAT_NUM_IO_APICS
1551 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
1552#else
1553 #define CFG_PLAT_NUM_IO_APICS 0
1554#endif
1555
1556#ifdef BLDCFG_MEM_INIT_PSTATE
1557 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
1558#else
1559 #define CFG_MEM_INIT_PSTATE 0
1560#endif
1561
1562#ifdef BLDCFG_PLATFORM_C1E_MODE
1563 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
1564#else
1565 #define CFG_C1E_MODE C1eModeDisabled
1566#endif
1567
1568#ifdef BLDCFG_PLATFORM_C1E_OPDATA
1569 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
1570#else
1571 #define CFG_C1E_OPDATA 0
1572#endif
1573
1574#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
1575 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
1576#else
1577 #define CFG_C1E_OPDATA1 0
1578#endif
1579
1580#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
1581 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
1582#else
1583 #define CFG_C1E_OPDATA2 0
1584#endif
1585
1586#ifdef BLDCFG_PLATFORM_CSTATE_MODE
1587 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
1588#else
1589 #define CFG_CSTATE_MODE CStateModeDisabled
1590#endif
1591
1592#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
1593 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
1594#else
1595 #define CFG_CSTATE_OPDATA 0
1596#endif
1597
1598#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1599 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1600#else
1601 #define CFG_CSTATE_IO_BASE_ADDRESS 0
1602#endif
1603
1604#ifdef BLDCFG_PLATFORM_CPB_MODE
1605 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
1606#else
1607 #define CFG_CPB_MODE CpbModeAuto
1608#endif
1609
1610#ifdef BLDCFG_CORE_LEVELING_MODE
1611 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
1612#else
1613 #define CFG_CORE_LEVELING_MODE 0
1614#endif
1615
1616#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
1617 #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE
1618#else
1619 #define CFG_AMD_PSTATE_CAP_VALUE 0
1620#endif
1621
1622#ifdef BLDCFG_HEAP_DRAM_ADDRESS
1623 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
1624#else
1625 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
1626#endif
1627
1628#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1629 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1630#else
1631 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
1632#endif
1633
1634#ifdef BLDCFG_MEMORY_MODE_UNGANGED
1635 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
1636#else
1637 #define CFG_MEMORY_MODE_UNGANGED TRUE
1638#endif
1639
1640#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
1641 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
1642#else
1643 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
1644#endif
1645
1646#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
1647 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
1648#else
1649 #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
1650#endif
1651
1652#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
1653 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
1654#else
1655 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
1656#endif
1657
1658#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
1659 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
1660#else
1661 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
1662#endif
1663
1664#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
1665 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
1666#else
1667 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
1668#endif
1669
1670#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
1671 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
1672#else
1673 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
1674#endif
1675
1676#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1677 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1678#else
1679 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
1680#endif
1681
1682#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1683 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1684#else
1685 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
1686#endif
1687
1688#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1689 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1690#else
1691 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
1692#endif
1693
1694#ifdef BLDCFG_MEMORY_POWER_DOWN
1695 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
1696#else
1697 #define CFG_MEMORY_POWER_DOWN FALSE
1698#endif
1699
1700#ifdef BLDCFG_POWER_DOWN_MODE
1701 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
1702#else
1703 #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
1704#endif
1705
1706#ifdef BLDCFG_ONLINE_SPARE
1707 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
1708#else
1709 #define CFG_ONLINE_SPARE FALSE
1710#endif
1711
1712#ifdef BLDCFG_MEMORY_PARITY_ENABLE
1713 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
1714#else
1715 #define CFG_MEMORY_PARITY_ENABLE FALSE
1716#endif
1717
1718#ifdef BLDCFG_BANK_SWIZZLE
1719 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
1720#else
1721 #define CFG_BANK_SWIZZLE TRUE
1722#endif
1723
1724#ifdef BLDCFG_TIMING_MODE_SELECT
1725 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
1726#else
1727 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
1728#endif
1729
1730#ifdef BLDCFG_MEMORY_CLOCK_SELECT
1731 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
1732#else
1733 #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
1734#endif
1735
1736#ifdef BLDCFG_DQS_TRAINING_CONTROL
1737 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
1738#else
1739 #define CFG_DQS_TRAINING_CONTROL TRUE
1740#endif
1741
1742#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
1743 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
1744#else
1745 #define CFG_IGNORE_SPD_CHECKSUM FALSE
1746#endif
1747
1748#ifdef BLDCFG_USE_BURST_MODE
1749 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
1750#else
1751 #define CFG_USE_BURST_MODE FALSE
1752#endif
1753
1754#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
1755 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
1756#else
1757 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
1758#endif
1759
1760#ifdef BLDCFG_ENABLE_ECC_FEATURE
1761 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
1762#else
1763 #define CFG_ENABLE_ECC_FEATURE TRUE
1764#endif
1765
1766#ifdef BLDCFG_ECC_REDIRECTION
1767 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
1768#else
1769 #define CFG_ECC_REDIRECTION FALSE
1770#endif
1771
1772#ifdef BLDCFG_SCRUB_DRAM_RATE
1773 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
1774#else
1775 #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
1776#endif
1777
1778#ifdef BLDCFG_SCRUB_L2_RATE
1779 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
1780#else
1781 #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
1782#endif
1783
1784#ifdef BLDCFG_SCRUB_L3_RATE
1785 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
1786#else
1787 #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
1788#endif
1789
1790#ifdef BLDCFG_SCRUB_IC_RATE
1791 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
1792#else
1793 #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
1794#endif
1795
1796#ifdef BLDCFG_SCRUB_DC_RATE
1797 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
1798#else
1799 #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
1800#endif
1801
1802#ifdef BLDCFG_ECC_SYNC_FLOOD
1803 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
1804#else
1805 #define CFG_ECC_SYNC_FLOOD 0
1806#endif
1807
1808#ifdef BLDCFG_ECC_SYMBOL_SIZE
1809 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
1810#else
1811 #define CFG_ECC_SYMBOL_SIZE 0
1812#endif
1813
1814#ifdef BLDCFG_1GB_ALIGN
1815 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
1816#else
1817 #define CFG_1GB_ALIGN FALSE
1818#endif
1819
1820#ifdef BLDCFG_UMA_ALLOCATION_MODE
1821 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
1822#else
1823 #define CFG_UMA_MODE UMA_AUTO
1824#endif
1825
1826#ifdef BLDCFG_UMA_ALLOCATION_SIZE
1827 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
1828#else
1829 #define CFG_UMA_SIZE 0
1830#endif
1831
1832#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
1833 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
1834#else
1835 #define CFG_UMA_ABOVE4G FALSE
1836#endif
1837
1838#ifdef BLDCFG_UMA_ALIGNMENT
1839 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
1840#else
1841 #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
1842#endif
1843
1844#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
1845 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
1846#else
1847 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
1848#endif
1849
1850#ifdef BLDCFG_S3_LATE_RESTORE
1851 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
1852#else
1853 #define CFG_S3_LATE_RESTORE TRUE
1854#endif
1855
1856#ifdef BLDCFG_USE_32_BYTE_REFRESH
1857 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
1858#else
1859 #define CFG_USE_32_BYTE_REFRESH (FALSE)
1860#endif
1861
1862#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
1863 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1864#else
1865 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
1866#endif
1867
1868#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
1869 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
1870#else
1871 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
1872#endif
1873
1874#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
1875 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
1876#else
1877 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
1878#endif
1879
1880#ifdef BLDCFG_CFG_GNB_HD_AUDIO
1881 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
1882#else
1883 #define CFG_GNB_HD_AUDIO TRUE
1884#endif
1885
1886#ifdef BLDCFG_CFG_ABM_SUPPORT
1887 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
1888#else
1889 #define CFG_ABM_SUPPORT FALSE
1890#endif
1891
1892#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1893 #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1894#else
1895 #define CFG_DYNAMIC_REFRESH_RATE 0
1896#endif
1897
1898#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1899 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1900#else
1901 #define CFG_LCD_BACK_LIGHT_CONTROL 0
1902#endif
1903
1904#ifdef BLDCFG_STEREO_3D_PINOUT
1905 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
1906#else
1907 #define CFG_GNB_STEREO_3D_PINOUT 0
1908#endif
1909
1910#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
1911 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
1912#else
1913 #define CFG_GNB_IGPU_SSID 0
1914#endif
1915
1916#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1917 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1918#else
1919 #define CFG_GNB_HDAUDIO_SSID 0
1920#endif
1921
1922#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1923 #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1924#else
1925 #define CFG_GNB_PCIE_SSID 0x12341022
1926#endif
1927
1928#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1929 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1930#else
1931 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
1932#endif
1933
1934#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1935 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1936#else
1937 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
1938#endif
1939
1940#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1941 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1942#else
1943 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
1944#endif
1945
1946#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
1947 #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
1948 #undef OPTION_EARLY_SAMPLES
1949 #define OPTION_EARLY_SAMPLES FALSE
1950 #else
1951 #undef OPTION_EARLY_SAMPLES
1952 #define OPTION_EARLY_SAMPLES TRUE
1953 #endif
1954#endif
1955
1956#ifdef BLDOPT_REMOVE_ALIB
1957 #if BLDOPT_REMOVE_ALIB == TRUE
1958 #undef OPTION_ALIB
1959 #define OPTION_ALIB FALSE
1960 #else
1961 #undef OPTION_ALIB
1962 #define OPTION_ALIB TRUE
1963 #endif
1964#endif
1965
1966/*---------------------------------------------------------------------------
1967 * Processing the options: Third, perform the option cross checks
1968 *--------------------------------------------------------------------------*/
1969// Assure that at least one type of memory support is included
1970#if OPTION_UDIMMS == FALSE
1971 #if OPTION_RDIMMS == FALSE
1972 #if OPTION_SODIMMS == FALSE
1973 #if OPTION_LRDIMMS == FALSE
1974 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
1975 #endif
1976 #endif
1977 #endif
1978#endif
1979// Ensure at least one dimm type is capable
1980#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
1981 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
1982 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
1983 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
1984 #error BLDCFG: No dimm type is capable
1985 #endif
1986 #endif
1987 #endif
1988#endif
1989// Check LRDIMM CODE and LRDIMM CFG item
1990#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
1991 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
1992 #error Warning: LRDIMM capability is false, but LRIDMM support code included
1993 #endif
1994#endif
1995// Turn off multi-socket based features if only one node...
1996#if OPTION_MULTISOCKET == FALSE
1997 #undef OPTION_PARALLEL_TRAINING
1998 #define OPTION_PARALLEL_TRAINING FALSE
1999 #undef OPTION_NODE_INTERLEAVE
2000 #define OPTION_NODE_INTERLEAVE FALSE
2001#endif
2002// Ensure that at least one write leveling option is selected
2003#if OPTION_DDR3 == TRUE
2004 #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
2005 #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
2006 #error No Write leveling option selected for DDR3
2007 #endif
2008 #endif
2009 #if OPTION_SW_DRAM_INIT == FALSE
2010 #error Software dram init must be enabled for DDR3 dimms
2011 #endif
2012#endif
2013// Ensure at least one DQS receiver training option is selected
2014#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
2015 #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
2016 #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
2017 #error No DQS receiver training option has been slected
2018 #endif
2019 #endif
2020#endif
2021// Ensure at least one Rd Wr position training option has been selected
2022#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
2023 #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
2024 #error No Rd Wr position training option has been selected
2025 #endif
2026#endif
2027// Ensure at least one dram init option has been selected
2028#if OPTION_HW_DRAM_INIT == FALSE
2029 #if OPTION_SW_DRAM_INIT == FALSE
2030 #error No Dram init option has been selected
2031 #endif
2032#endif
2033// Ensure the frequency limit is valid
2034#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933)
2035 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
2036 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
2037 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
2038 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
2039 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
2040 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
2041 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
2042 #error BLDCFG: Unsupported memory bus frequency
2043 #endif
2044 #endif
2045 #endif
2046 #endif
2047 #endif
2048 #endif
2049 #endif
2050#endif
2051// Ensure timing mode is valid
2052#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
2053 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
2054 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
2055 #error BLDCFG: Invalid timing mode is set
2056 #endif
2057 #endif
2058#endif
2059// Ensure the scrub rate is valid
2060#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
2061 #error BLDCFG: Unsupported dram scrub rate set
2062#endif
2063#if CFG_SCRUB_L2_RATE > 0x16
2064 #error BLDCFG: Unsupported L2 scrubber rate set
2065#endif
2066#if CFG_SCRUB_L3_RATE > 0x16
2067 #error BLDCFG: unsupported L3 scrubber rate set
2068#endif
2069#if CFG_SCRUB_IC_RATE > 0x16
2070 #error BLDCFG: Unsupported Instruction cache scrub rate set
2071#endif
2072#if CFG_SCRUB_DC_RATE > 0x16
2073 #error BLDCFG: Unsupported Dcache scrub rate set
2074#endif
2075// Ensure Quad rank dimm type is valid
2076#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
2077 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
2078 #error BLDCFG: Invalid quad rank dimm type set
2079 #endif
2080#endif
2081// Ensure ECC symbol size is valid
2082#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
2083 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
2084 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
2085 #error BLDCFG: Invalid Ecc symbol size set
2086 #endif
2087 #endif
2088#endif
2089// Ensure power down mode is valid
2090#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
2091 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
2092 #error BLDCFG: Invalid power down mode set
2093 #endif
2094#endif
2095
2096/*****************************************************************************
2097 *
2098 * Process the option logic, setting local control variables
2099 *
2100 ****************************************************************************/
2101#if OPTION_ACPI_PSTATES == TRUE
2102 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
2103 #define OPTFCN_GATHER_DATA PStateGatherData
2104 #if OPTION_MULTISOCKET == TRUE
2105 #define OPTFCN_PSTATE_LEVELING PStateLeveling
2106 #else
2107 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
2108 #endif
2109#else
2110 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
2111 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
2112 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
2113#endif
2114
2115
2116/*****************************************************************************
2117 *
2118 * Include the structure definitions for the defaults table structures
2119 *
2120 ****************************************************************************/
2121#include "Options.h"
2122#include "OptionCpuFamiliesInstall.h"
2123#include "OptionsHt.h"
2124#include "OptionHtInstall.h"
2125#include "OptionMemory.h"
2126#include "PlatformMemoryConfiguration.h"
2127#include "OptionMemoryInstall.h"
2128#include "OptionMemoryRecovery.h"
2129#include "OptionMemoryRecoveryInstall.h"
2130#include "OptionCpuFeaturesInstall.h"
2131#include "OptionDmi.h"
2132#include "OptionDmiInstall.h"
2133#include "OptionPstate.h"
2134#include "OptionPstateInstall.h"
2135#include "OptionWhea.h"
2136#include "OptionWheaInstall.h"
2137#include "OptionSrat.h"
2138#include "OptionSratInstall.h"
2139#include "OptionSlit.h"
2140#include "OptionSlitInstall.h"
2141#include "OptionMultiSocket.h"
2142#include "OptionMultiSocketInstall.h"
2143#include "OptionIdsInstall.h"
2144#include "OptionGfxRecovery.h"
2145#include "OptionGfxRecoveryInstall.h"
2146#include "OptionGnb.h"
2147#include "OptionGnbInstall.h"
2148#include "OptionS3ScriptInstall.h"
2149
2150
2151/*****************************************************************************
2152 *
2153 * Generate the output structures (defaults tables)
2154 *
2155 ****************************************************************************/
2156BUILD_OPT_CFG UserOptions = {
2157 { // AGESA version string
2158 AGESA_CODE_SIGNATURE, // code header Signature
2159 AGESA_PACKAGE_STRING, // 8 character ID
2160 AGESA_VERSION_STRING, // 12 character version string
2161 0 // null string terminator
2162 },
2163 //Build Option Area
2164 OPTION_UDIMMS, //UDIMMS
2165 OPTION_RDIMMS, //RDIMMS
2166 OPTION_LRDIMMS, //LRDIMMS
2167 OPTION_ECC, //ECC
2168 OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE
2169 OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE
2170 OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE
2171 OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING
2172 OPTION_ONLINE_SPARE, //ONLINE_SPARE
2173 OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE
2174 OPTION_MULTISOCKET, //MULTISOCKET
2175 OPTION_ACPI_PSTATES, //ACPI_PSTATES
2176 OPTION_SRAT, //SRAT
2177 OPTION_SLIT, //SLIT
2178 OPTION_WHEA, //WHEA
2179 OPTION_DMI, //DMI
2180 OPTION_EARLY_SAMPLES, //EARLY_SAMPLES
2181 OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR
2182
2183 //Build Configuration Area
2184 CFG_PCI_MMIO_BASE,
2185 CFG_PCI_MMIO_SIZE,
2186 {
2187 // CoreVrm
2188 {
2189 CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit
2190 CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold
2191 CFG_VRM_SLEW_RATE, // VrmSlewRate
2192 CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay
2193 CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable
2194 CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit
2195 },
2196 // NbVrm
2197 {
2198 CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit
2199 CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold
2200 CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate
2201 CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay
2202 CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable
2203 CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit
2204 }
2205 },
2206 CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber
2207 CFG_MEM_INIT_PSTATE, //MemoryInitPstate
2208 CFG_C1E_MODE, //C1eMode
2209 CFG_C1E_OPDATA, //C1ePlatformData
2210 CFG_C1E_OPDATA1, //C1ePlatformData1
2211 CFG_C1E_OPDATA2, //C1ePlatformData2
2212 CFG_CSTATE_MODE, //CStateMode
2213 CFG_CSTATE_OPDATA, //CStatePlatformData
2214 CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress
2215 CFG_CPB_MODE, //CpbMode
2216 CFG_CORE_LEVELING_MODE, //CoreLevelingCofig
2217 {
2218 CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode.
2219 CFG_USE_HT_ASSIST, // CfgUseHtAssist
2220 CFG_USE_ATM_MODE, // CfgUseAtmMode
2221 CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets.
2222 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
2223 CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode.
2224 },
2225 (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings
2226 CFG_AMD_PLATFORM_TYPE, //AmdPlatformType
2227 CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck
2228
2229 CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit
2230 CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged
2231 CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable
2232 CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType
2233 CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable
2234 CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable
2235 CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable
2236 CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable
2237 CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving
2238 CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving
2239 CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving
2240 CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown
2241 CFG_POWER_DOWN_MODE, // CfgPowerDownMode
2242 CFG_ONLINE_SPARE, // CfgOnlineSpare
2243 CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable
2244 CFG_BANK_SWIZZLE, // CfgBankSwizzle
2245 CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect
2246 CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect
2247 CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl
2248 CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum
2249 CFG_USE_BURST_MODE, // CfgUseBurstMode
2250 CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn
2251 CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature
2252 CFG_ECC_REDIRECTION, // CfgEccRedirection
2253 CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate
2254 CFG_SCRUB_L2_RATE, // CfgScrubL2Rate
2255 CFG_SCRUB_L3_RATE, // CfgScrubL3Rate
2256 CFG_SCRUB_IC_RATE, // CfgScrubIcRate
2257 CFG_SCRUB_DC_RATE, // CfgScrubDcRate
2258 CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood
2259 CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize
2260 CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress
2261 CFG_1GB_ALIGN, // CfgNodeMem1GBAlign
2262 CFG_S3_LATE_RESTORE, // CfgS3LateRestore
2263 CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent
2264 (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
2265 CFG_UMA_MODE, // CfgUmaMode
2266 CFG_UMA_SIZE, // CfgUmaSize
2267 CFG_UMA_ABOVE4G, // CfgUmaAbove4G
2268 CFG_UMA_ALIGNMENT, // CfgUmaAlignment
2269 CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb
2270 CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0
2271 CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1
2272 CFG_GNB_HD_AUDIO, // CfgGnbHdAudio
2273 CFG_ABM_SUPPORT, // CfgAbmSupport
2274 CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate
2275 CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl
2276 CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex
2277 CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress
2278 CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID
2279 CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID
2280 CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID
2281 CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
2282 CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
2283
2284 0, //reserved...
2285};
2286
2287CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
2288{
2289 #if AGESA_ENTRY_INIT_RESET == TRUE
2290 { AMD_INIT_RESET,
2291 sizeof (AMD_RESET_PARAMS),
2292 (PF_AGESA_FUNCTION) AmdInitResetConstructor,
2293 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2294 AMD_INIT_RESET_HANDLE
2295 },
2296 #endif
2297
2298 #if AGESA_ENTRY_INIT_RECOVERY == TRUE
2299 { AMD_INIT_RECOVERY,
2300 sizeof (AMD_RECOVERY_PARAMS),
2301 (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
2302 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2303 AMD_INIT_POST_HANDLE
2304 },
2305 #endif
2306
2307 #if AGESA_ENTRY_INIT_EARLY == TRUE
2308 { AMD_INIT_EARLY,
2309 sizeof (AMD_EARLY_PARAMS),
2310 (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
2311 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2312 AMD_INIT_EARLY_HANDLE
2313 },
2314 #endif
2315
2316 #if AGESA_ENTRY_INIT_ENV == TRUE
2317 { AMD_INIT_ENV,
2318 sizeof (AMD_ENV_PARAMS),
2319 (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
2320 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2321 AMD_INIT_ENV_HANDLE
2322 },
2323 #endif
2324
2325 #if AGESA_ENTRY_INIT_LATE == TRUE
2326 { AMD_INIT_LATE,
2327 sizeof (AMD_LATE_PARAMS),
2328 (PF_AGESA_FUNCTION) AmdInitLateInitializer,
2329 (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
2330 AMD_INIT_LATE_HANDLE
2331 },
2332 #endif
2333
2334 #if AGESA_ENTRY_INIT_MID == TRUE
2335 { AMD_INIT_MID,
2336 sizeof (AMD_MID_PARAMS),
2337 (PF_AGESA_FUNCTION) AmdInitMidInitializer,
2338 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2339 AMD_INIT_MID_HANDLE
2340 },
2341 #endif
2342
2343 #if AGESA_ENTRY_INIT_POST == TRUE
2344 { AMD_INIT_POST,
2345 sizeof (AMD_POST_PARAMS),
2346 (PF_AGESA_FUNCTION) AmdInitPostInitializer,
2347 (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
2348 AMD_INIT_POST_HANDLE
2349 },
2350 #endif
2351
2352 #if AGESA_ENTRY_INIT_RESUME == TRUE
2353 { AMD_INIT_RESUME,
2354 sizeof (AMD_RESUME_PARAMS),
2355 (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
2356 (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
2357 AMD_INIT_RESUME_HANDLE
2358 },
2359 #endif
2360
2361 #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
2362 { AMD_S3LATE_RESTORE,
2363 sizeof (AMD_S3LATE_PARAMS),
2364 (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
2365 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2366 AMD_S3_LATE_RESTORE_HANDLE
2367 },
2368 #endif
2369
2370 #if AGESA_ENTRY_INIT_S3SAVE == TRUE
2371 { AMD_S3_SAVE,
2372 sizeof (AMD_S3SAVE_PARAMS),
2373 (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
2374 (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
2375 AMD_S3_SAVE_HANDLE
2376 },
2377 #endif
2378
2379 #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
2380 { AMD_LATE_RUN_AP_TASK,
2381 sizeof (AP_EXE_PARAMS),
2382 (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
2383 (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
2384 AMD_LATE_RUN_AP_TASK_HANDLE
2385 },
2386 #endif
2387 { 0, NULL }
2388};
2389
2390CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
2391
2392CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
2393{
2394 { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
2395 { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
2396
2397 #if AGESA_ENTRY_INIT_RESET == TRUE
2398 { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
2399 #endif
2400
2401 #if AGESA_ENTRY_INIT_RECOVERY == TRUE
2402 { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
2403 #endif
2404
2405 #if AGESA_ENTRY_INIT_EARLY == TRUE
2406 { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
2407 #endif
2408
2409 #if AGESA_ENTRY_INIT_POST == TRUE
2410 { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
2411 #endif
2412
2413 #if AGESA_ENTRY_INIT_ENV == TRUE
2414 { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
2415 #endif
2416
2417 #if AGESA_ENTRY_INIT_MID == TRUE
2418 { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
2419 #endif
2420
2421 #if AGESA_ENTRY_INIT_LATE == TRUE
2422 { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
2423 #endif
2424
2425 #if AGESA_ENTRY_INIT_S3SAVE == TRUE
2426 { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
2427 #endif
2428
2429 #if AGESA_ENTRY_INIT_RESUME == TRUE
2430 { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
2431 #endif
2432
2433 #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
2434 { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
2435 #endif
2436
2437 #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
2438 { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
2439 { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
2440 { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
2441 { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
2442 { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
2443 { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
2444 #endif
2445
2446 #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
2447 { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
2448 #endif
2449 { 0, NULL }
2450};
2451
2452CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
2453{
2454 IDS_LATE_RUN_AP_TASK
2455 // Get DMI info
2456 CPU_DMI_AP_GET_TYPE4_TYPE7
2457 // Probe filter enable
2458 HT_ASSIST_AP_DISABLE_CACHE
2459 HT_ASSIST_AP_ENABLE_CACHE
2460
2461 { 0, NULL }
2462};
2463
2464#if AGESA_ENTRY_INIT_RESET == TRUE
2465 #if IDSOPT_IDS_ENABLED == TRUE
2466 #if IDSOPT_TRACING_ENABLED == TRUE
2467 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
2468 CONST CHAR8 *BldOptDebugOutput[] = {
2469 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
2470 //Build Option Area
2471 MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS)
2472 MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS)
2473 MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS)
2474 MAKE_DBG_STR (\nOptECC, OPTION_ECC)
2475 MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE)
2476 MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE)
2477 MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE)
2478 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
2479 MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE)
2480 MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
2481 MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE)
2482 MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET)
2483 MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES)
2484 MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT)
2485 MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT)
2486 MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA)
2487 MAKE_DBG_STR (\nOptDMI, OPTION_DMI)
2488 MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES),
2489
2490 //Build Configuration Area
2491 // CoreVrm
2492 MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT)
2493 MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
2494 MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE)
2495 MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY)
2496 MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE)
2497 MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT)
2498 // NbVrm
2499 MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT)
2500 MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
2501 MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE)
2502 MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY)
2503 MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE)
2504 MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT),
2505
2506 MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS)
2507 MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE)
2508 MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE)
2509 MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA)
2510 MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1)
2511 MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2)
2512 MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE)
2513 MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA)
2514 MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS)
2515 MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE)
2516 MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE),
2517
2518 MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE)
2519 MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST)
2520 MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE)
2521 MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH)
2522 MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
2523 MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD)
2524
2525 MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST)
2526
2527 MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE)
2528 MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE)
2529 MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE)
2530 MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE),
2531
2532 MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
2533 MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT)
2534 MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT)
2535
2536 MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED)
2537 MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE)
2538 MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE)
2539 MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE)
2540 MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE)
2541 MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE)
2542 MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE)
2543 MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL)
2544 MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM)
2545 MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE)
2546 MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON),
2547
2548 MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN)
2549 MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE)
2550 MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE)
2551 MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE)
2552 MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE)
2553 MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
2554 MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
2555 MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING),
2556
2557 MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE)
2558 MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE)
2559 MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G)
2560 MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT)
2561
2562 MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE)
2563 MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION)
2564 MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE)
2565 MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE)
2566 MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE)
2567 MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE)
2568 MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE)
2569 MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD)
2570 MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE)
2571 MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS)
2572 MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN),
2573
2574 MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE)
2575 MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
2576
2577 MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST)
2578
2579 MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB)
2580 MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0)
2581 MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1)
2582 MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO)
2583 MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT)
2584 MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE)
2585 MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL)
2586 MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT)
2587 MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
2588 MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID),
2589 MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID),
2590 MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID),
2591
2592 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM),
2593 MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE),
2594 #endif
2595 NULL
2596 };
2597 #endif
2598 #endif
2599#endif