Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <acpi/acpigen.h> |
| 4 | #include <assert.h> |
| 5 | #include <cbmem.h> |
| 6 | #include <device/mmio.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <intelblocks/acpi.h> |
| 9 | #include <soc/acpi.h> |
| 10 | #include <soc/cpu.h> |
| 11 | #include <soc/iomap.h> |
| 12 | #include <soc/pci_devs.h> |
| 13 | #include <soc/soc_util.h> |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 14 | #include <soc/util.h> |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 15 | |
| 16 | #include "chip.h" |
| 17 | |
| 18 | /* Northbridge(NUMA) ACPI table generation. SRAT, SLIT, etc */ |
| 19 | |
| 20 | unsigned long acpi_create_srat_lapics(unsigned long current) |
| 21 | { |
| 22 | struct device *cpu; |
| 23 | unsigned int cpu_index = 0; |
| 24 | |
| 25 | for (cpu = all_devices; cpu; cpu = cpu->next) { |
| 26 | if ((cpu->path.type != DEVICE_PATH_APIC) || |
| 27 | (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { |
| 28 | continue; |
| 29 | } |
| 30 | if (!cpu->enabled) |
| 31 | continue; |
| 32 | printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", |
| 33 | cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); |
| 34 | current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, |
| 35 | cpu->path.apic.node_id, cpu->path.apic.apic_id); |
| 36 | cpu_index++; |
| 37 | } |
| 38 | return current; |
| 39 | } |
| 40 | |
| 41 | static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) |
| 42 | { |
| 43 | const struct SystemMemoryMapHob *memory_map; |
| 44 | unsigned int mmap_index; |
| 45 | |
| 46 | memory_map = get_system_memory_map(); |
| 47 | assert(memory_map != NULL); |
| 48 | printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); |
| 49 | |
| 50 | mmap_index = 0; |
| 51 | for (int e = 0; e < memory_map->numberEntries; ++e) { |
| 52 | const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; |
| 53 | uint64_t addr = |
| 54 | (uint64_t) ((uint64_t)mem_element->BaseAddress << |
| 55 | MEM_ADDR_64MB_SHIFT_BITS); |
| 56 | uint64_t size = |
| 57 | (uint64_t) ((uint64_t)mem_element->ElementSize << |
| 58 | MEM_ADDR_64MB_SHIFT_BITS); |
| 59 | |
| 60 | printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " |
| 61 | "ElementSize: 0x%x, reserved: %d\n", |
| 62 | e, addr, mem_element->BaseAddress, size, |
| 63 | mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); |
| 64 | |
| 65 | assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); |
| 66 | |
| 67 | /* skip reserved memory region */ |
| 68 | if (mem_element->Type & MEM_TYPE_RESERVED) |
| 69 | continue; |
| 70 | |
| 71 | /* skip if this address is already added */ |
| 72 | bool skip = false; |
| 73 | for (int idx = 0; idx < mmap_index; ++idx) { |
| 74 | uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + |
| 75 | srat_mem[idx].base_address_low; |
| 76 | if (addr == base_addr) { |
| 77 | skip = true; |
| 78 | break; |
| 79 | } |
| 80 | } |
| 81 | if (skip) |
| 82 | continue; |
| 83 | |
| 84 | srat_mem[mmap_index].type = 1; /* Memory affinity structure */ |
| 85 | srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); |
| 86 | srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); |
| 87 | srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); |
| 88 | srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); |
| 89 | srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); |
| 90 | srat_mem[mmap_index].proximity_domain = mem_element->SocketId; |
| 91 | srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; |
| 92 | if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) |
| 93 | srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; |
| 94 | ++mmap_index; |
| 95 | } |
| 96 | |
| 97 | return mmap_index; |
| 98 | } |
| 99 | |
| 100 | static unsigned long acpi_fill_srat(unsigned long current) |
| 101 | { |
| 102 | acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; |
| 103 | unsigned int mem_count; |
| 104 | |
| 105 | /* create all subtables for processors */ |
| 106 | current = acpi_create_srat_lapics(current); |
| 107 | |
| 108 | mem_count = get_srat_memory_entries(srat_mem); |
| 109 | for (int i = 0; i < mem_count; ++i) { |
| 110 | printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " |
| 111 | "length: 0x%x%x, proximity_domain: %d, flags: %x\n", |
| 112 | i, srat_mem[i].length, |
| 113 | srat_mem[i].base_address_high, srat_mem[i].base_address_low, |
| 114 | srat_mem[i].length_high, srat_mem[i].length_low, |
| 115 | srat_mem[i].proximity_domain, srat_mem[i].flags); |
| 116 | memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); |
| 117 | current += srat_mem[i].length; |
| 118 | } |
| 119 | |
| 120 | return current; |
| 121 | } |
| 122 | |
| 123 | static unsigned long acpi_fill_slit(unsigned long current) |
| 124 | { |
Marc Jones | 70907b0 | 2020-10-28 17:00:31 -0600 | [diff] [blame] | 125 | unsigned int nodes = soc_get_num_cpus(); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 126 | |
| 127 | uint8_t *p = (uint8_t *)current; |
| 128 | memset(p, 0, 8 + nodes * nodes); |
| 129 | *p = (uint8_t)nodes; |
| 130 | p += 8; |
| 131 | |
| 132 | /* this assumes fully connected socket topology */ |
| 133 | for (int i = 0; i < nodes; i++) { |
| 134 | for (int j = 0; j < nodes; j++) { |
| 135 | if (i == j) |
| 136 | p[i*nodes+j] = 10; |
| 137 | else |
| 138 | p[i*nodes+j] = 16; |
| 139 | } |
| 140 | } |
| 141 | |
| 142 | current += 8 + nodes * nodes; |
| 143 | return current; |
| 144 | } |
| 145 | |
| 146 | /* |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 147 | * This function adds PCIe bridge device entry in DMAR table. If it is called |
| 148 | * in the context of ATSR subtable, it adds ATSR subtable when it is first called. |
| 149 | */ |
| 150 | static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, |
Jacob Garber | 6df3870 | 2020-10-24 16:23:45 -0600 | [diff] [blame] | 151 | int port, int stack, const IIO_RESOURCE_INSTANCE *iio_resource, uint32_t pcie_seg, |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 152 | bool is_atsr, bool *first) |
| 153 | { |
| 154 | |
Marc Jones | 995a7e2 | 2020-10-28 17:08:54 -0600 | [diff] [blame] | 155 | if (soc_get_stack_for_port(port) != stack) |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 156 | return 0; |
| 157 | |
Jacob Garber | 6df3870 | 2020-10-24 16:23:45 -0600 | [diff] [blame] | 158 | const uint32_t bus = iio_resource->StackRes[stack].BusBase; |
| 159 | const uint32_t dev = iio_resource->PcieInfo.PortInfo[port].Device; |
| 160 | const uint32_t func = iio_resource->PcieInfo.PortInfo[port].Function; |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 161 | |
| 162 | const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), |
| 163 | PCI_VENDOR_ID); |
| 164 | if (id == 0xffffffff) |
| 165 | return 0; |
| 166 | |
| 167 | unsigned long atsr_size = 0; |
| 168 | unsigned long pci_br_size = 0; |
| 169 | if (is_atsr == true && first && *first == true) { |
| 170 | printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " |
| 171 | "PCI Segment Number: 0x%x\n", 0, pcie_seg); |
| 172 | atsr_size = acpi_create_dmar_atsr(current, 0, pcie_seg); |
| 173 | *first = false; |
| 174 | } |
| 175 | |
| 176 | printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " |
| 177 | "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", |
| 178 | 0, bus, dev, func); |
| 179 | pci_br_size = acpi_create_dmar_ds_pci_br(current + atsr_size, bus, dev, func); |
| 180 | |
| 181 | return (atsr_size + pci_br_size); |
| 182 | } |
| 183 | |
| 184 | static unsigned long acpi_create_drhd(unsigned long current, int socket, |
| 185 | int stack, const IIO_UDS *hob) |
| 186 | { |
| 187 | int IoApicID[] = { |
| 188 | // socket 0 |
| 189 | PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, |
| 190 | PC04_IOAPIC_ID, PC05_IOAPIC_ID, |
| 191 | // socket 1 |
| 192 | PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, |
| 193 | PC10_IOAPIC_ID, PC11_IOAPIC_ID, |
| 194 | }; |
| 195 | |
| 196 | uint32_t enum_id; |
| 197 | unsigned long tmp = current; |
| 198 | |
| 199 | uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; |
| 200 | uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; |
| 201 | uint32_t reg_base = |
| 202 | hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; |
| 203 | printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", |
| 204 | __func__, socket, stack, bus, pcie_seg, reg_base); |
| 205 | |
| 206 | /* Do not generate DRHD for non-PCIe stack */ |
| 207 | if (!reg_base) |
| 208 | return current; |
| 209 | |
| 210 | // Add DRHD Hardware Unit |
| 211 | if (socket == 0 && stack == CSTACK) { |
| 212 | printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " |
| 213 | "Register Base Address: 0x%x\n", |
| 214 | DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); |
| 215 | current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, |
| 216 | pcie_seg, reg_base); |
| 217 | } else { |
| 218 | printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " |
| 219 | "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); |
| 220 | current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); |
| 221 | } |
| 222 | |
| 223 | // Add PCH IOAPIC |
| 224 | if (socket == 0 && stack == CSTACK) { |
| 225 | printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " |
| 226 | "PCI Path: 0x%x, 0x%x\n", |
| 227 | PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, |
| 228 | PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); |
| 229 | current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, |
| 230 | PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); |
| 231 | } |
| 232 | |
| 233 | // Add IOAPIC entry |
| 234 | enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; |
| 235 | printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " |
| 236 | "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); |
| 237 | current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, |
| 238 | APIC_DEV_NUM, APIC_FUNC_NUM); |
| 239 | |
| 240 | // Add CBDMA devices for CSTACK |
| 241 | if (socket != 0 && stack == CSTACK) { |
| 242 | for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { |
| 243 | printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " |
| 244 | "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", |
| 245 | 0, bus, CBDMA_DEV_NUM, cbdma_func_id); |
| 246 | current += acpi_create_dmar_ds_pci(current, |
| 247 | bus, CBDMA_DEV_NUM, cbdma_func_id); |
| 248 | } |
| 249 | } |
| 250 | |
| 251 | // Add PCIe Ports |
| 252 | if (socket != 0 || stack != CSTACK) { |
| 253 | IIO_RESOURCE_INSTANCE iio_resource = |
| 254 | hob->PlatformData.IIO_resource[socket]; |
| 255 | for (int p = PORT_0; p < MAX_PORTS; ++p) |
| 256 | current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, |
Jacob Garber | 6df3870 | 2020-10-24 16:23:45 -0600 | [diff] [blame] | 257 | &iio_resource, pcie_seg, false, NULL); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 258 | |
| 259 | // Add VMD |
| 260 | if (hob->PlatformData.VMDStackEnable[socket][stack] && |
| 261 | stack >= PSTACK0 && stack <= PSTACK2) { |
| 262 | printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " |
| 263 | "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", |
| 264 | 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); |
| 265 | current += acpi_create_dmar_ds_pci(current, |
| 266 | bus, VMD_DEV_NUM, VMD_FUNC_NUM); |
| 267 | } |
| 268 | } |
| 269 | |
| 270 | // Add HPET |
| 271 | if (socket == 0 && stack == CSTACK) { |
| 272 | uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); |
| 273 | uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count |
| 274 | printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", |
| 275 | __func__, hpet_capid, num_hpets); |
| 276 | //BIT 15 |
| 277 | if (num_hpets && (num_hpets != 0x1f) && |
| 278 | (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { |
| 279 | printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " |
| 280 | "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", |
| 281 | 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); |
| 282 | current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, |
| 283 | HPET_DEV_NUM, HPET0_FUNC_NUM); |
| 284 | } |
| 285 | } |
| 286 | |
| 287 | acpi_dmar_drhd_fixup(tmp, current); |
| 288 | |
| 289 | return current; |
| 290 | } |
| 291 | |
| 292 | static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob) |
| 293 | { |
| 294 | for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { |
| 295 | uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; |
| 296 | unsigned long tmp = current; |
| 297 | bool first = true; |
| 298 | IIO_RESOURCE_INSTANCE iio_resource = |
| 299 | hob->PlatformData.IIO_resource[socket]; |
| 300 | |
| 301 | for (int stack = 0; stack <= PSTACK2; ++stack) { |
| 302 | uint32_t bus = iio_resource.StackRes[stack].BusBase; |
| 303 | uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; |
| 304 | if (!vtd_base) |
| 305 | continue; |
| 306 | uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); |
| 307 | printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " |
| 308 | "vtd_mmio_cap: 0x%llx\n", |
| 309 | __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); |
| 310 | |
| 311 | // ATSR is applicable only for platform supporting device IOTLBs |
| 312 | // through the VT-d extended capability register |
| 313 | assert(vtd_mmio_cap != 0xffffffffffffffff); |
| 314 | if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 |
| 315 | continue; |
| 316 | |
| 317 | for (int p = PORT_0; p < MAX_PORTS; ++p) { |
| 318 | if (socket == 0 && p == PORT_0) |
| 319 | continue; |
| 320 | current += acpi_create_dmar_ds_pci_br_for_port(current, p, |
Jacob Garber | 6df3870 | 2020-10-24 16:23:45 -0600 | [diff] [blame] | 321 | stack, &iio_resource, pcie_seg, true, &first); |
Marc Jones | 97321db | 2020-09-28 23:35:08 -0600 | [diff] [blame] | 322 | } |
| 323 | } |
| 324 | if (tmp != current) |
| 325 | acpi_dmar_atsr_fixup(tmp, current); |
| 326 | } |
| 327 | |
| 328 | return current; |
| 329 | } |
| 330 | |
| 331 | static unsigned long acpi_create_rmrr(unsigned long current) |
| 332 | { |
| 333 | uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); |
| 334 | |
| 335 | uint32_t *ptr; |
| 336 | |
| 337 | // reserve memory |
| 338 | ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); |
| 339 | if (!ptr) { |
| 340 | ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); |
| 341 | assert(ptr != NULL); |
| 342 | memset(ptr, 0, size); |
| 343 | } |
| 344 | |
| 345 | unsigned long tmp = current; |
| 346 | printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " |
| 347 | "End Address (limit): 0x%x\n", |
| 348 | 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); |
| 349 | current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, |
| 350 | (uint32_t) ((uint32_t) ptr + size - 1)); |
| 351 | |
| 352 | printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " |
| 353 | "PCI Path: 0x%x, 0x%x\n", |
| 354 | 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); |
| 355 | current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, |
| 356 | PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); |
| 357 | |
| 358 | acpi_dmar_rmrr_fixup(tmp, current); |
| 359 | |
| 360 | return current; |
| 361 | } |
| 362 | |
| 363 | static unsigned long acpi_create_rhsa(unsigned long current) |
| 364 | { |
| 365 | size_t hob_size; |
| 366 | const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; |
| 367 | const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); |
| 368 | assert(hob != NULL && hob_size != 0); |
| 369 | |
| 370 | for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { |
| 371 | IIO_RESOURCE_INSTANCE iio_resource = |
| 372 | hob->PlatformData.IIO_resource[socket]; |
| 373 | for (int stack = 0; stack <= PSTACK2; ++stack) { |
| 374 | uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; |
| 375 | if (!vtd_base) |
| 376 | continue; |
| 377 | |
| 378 | printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " |
| 379 | "Proximity Domain: 0x%x\n", vtd_base, socket); |
| 380 | current += acpi_create_dmar_rhsa(current, vtd_base, socket); |
| 381 | } |
| 382 | } |
| 383 | |
| 384 | return current; |
| 385 | } |
| 386 | |
| 387 | static unsigned long acpi_fill_dmar(unsigned long current) |
| 388 | { |
| 389 | size_t hob_size; |
| 390 | const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; |
| 391 | const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); |
| 392 | assert(hob != NULL && hob_size != 0); |
| 393 | |
| 394 | // DRHD |
| 395 | for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { |
| 396 | int socket = iio; |
| 397 | if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry |
| 398 | socket = 0; |
| 399 | |
| 400 | if (socket == 0) { |
| 401 | for (int stack = 1; stack <= PSTACK2; ++stack) |
| 402 | current = acpi_create_drhd(current, socket, stack, hob); |
| 403 | current = acpi_create_drhd(current, socket, CSTACK, hob); |
| 404 | } else { |
| 405 | for (int stack = 0; stack <= PSTACK2; ++stack) |
| 406 | current = acpi_create_drhd(current, socket, stack, hob); |
| 407 | } |
| 408 | } |
| 409 | |
| 410 | // RMRR |
| 411 | current = acpi_create_rmrr(current); |
| 412 | |
| 413 | // Root Port ATS Capability |
| 414 | current = acpi_create_atsr(current, hob); |
| 415 | |
| 416 | // RHSA |
| 417 | current = acpi_create_rhsa(current); |
| 418 | |
| 419 | return current; |
| 420 | } |
| 421 | |
| 422 | unsigned long northbridge_write_acpi_tables(const struct device *device, |
| 423 | unsigned long current, |
| 424 | struct acpi_rsdp *rsdp) |
| 425 | { |
| 426 | acpi_srat_t *srat; |
| 427 | acpi_slit_t *slit; |
| 428 | acpi_dmar_t *dmar; |
| 429 | |
| 430 | const config_t *const config = config_of(device); |
| 431 | |
| 432 | /* SRAT */ |
| 433 | current = ALIGN(current, 8); |
| 434 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
| 435 | srat = (acpi_srat_t *) current; |
| 436 | acpi_create_srat(srat, acpi_fill_srat); |
| 437 | current += srat->header.length; |
| 438 | acpi_add_table(rsdp, srat); |
| 439 | |
| 440 | /* SLIT */ |
| 441 | current = ALIGN(current, 8); |
| 442 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
| 443 | slit = (acpi_slit_t *) current; |
| 444 | acpi_create_slit(slit, acpi_fill_slit); |
| 445 | current += slit->header.length; |
| 446 | acpi_add_table(rsdp, slit); |
| 447 | |
| 448 | /* DMAR */ |
| 449 | if (config->vtd_support) { |
| 450 | current = ALIGN(current, 8); |
| 451 | dmar = (acpi_dmar_t *)current; |
| 452 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 453 | printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", DMAR_INTR_REMAP); |
| 454 | acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); |
| 455 | current += dmar->header.length; |
| 456 | current = acpi_align_current(current); |
| 457 | acpi_add_table(rsdp, dmar); |
| 458 | } |
| 459 | |
| 460 | return current; |
| 461 | } |