Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame^] | 2 | * This file is part of the coreboot project. |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <console/console.h> |
| 23 | #include <arch/smp/mpspec.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <string.h> |
| 26 | #include <stdint.h> |
| 27 | |
| 28 | #include <cpu/amd/amdk8_sysconf.h> |
| 29 | extern unsigned char bus_isa; |
| 30 | extern unsigned char bus_mcp55[8]; //1 |
| 31 | |
| 32 | extern unsigned apicid_mcp55; |
| 33 | |
| 34 | extern unsigned char bus_pcix[3]; // under bus_mcp55_2 |
| 35 | |
| 36 | void *smp_write_config_table(void *v) |
| 37 | { |
| 38 | static const char sig[4] = "PCMP"; |
| 39 | static const char oem[8] = "SUPERMIC"; |
| 40 | static const char productid[12] = "H8DMR "; |
| 41 | struct mp_config_table *mc; |
| 42 | unsigned sbdn; |
| 43 | |
| 44 | unsigned char bus_num; |
| 45 | int i,j; |
| 46 | |
| 47 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 48 | memset(mc, 0, sizeof(*mc)); |
| 49 | |
| 50 | memcpy(mc->mpc_signature, sig, sizeof(sig)); |
| 51 | mc->mpc_length = sizeof(*mc); /* initially just the header */ |
| 52 | mc->mpc_spec = 0x04; |
| 53 | mc->mpc_checksum = 0; /* not yet computed */ |
| 54 | memcpy(mc->mpc_oem, oem, sizeof(oem)); |
| 55 | memcpy(mc->mpc_productid, productid, sizeof(productid)); |
| 56 | mc->mpc_oemptr = 0; |
| 57 | mc->mpc_oemsize = 0; |
| 58 | mc->mpc_entry_count = 0; /* No entries yet... */ |
| 59 | mc->mpc_lapic = LAPIC_ADDR; |
| 60 | mc->mpe_length = 0; |
| 61 | mc->mpe_checksum = 0; |
| 62 | mc->reserved = 0; |
| 63 | |
| 64 | smp_write_processors(mc); |
| 65 | |
| 66 | get_bus_conf(); |
| 67 | sbdn = sysconf.sbdn; |
| 68 | |
| 69 | /*Bus: Bus ID Type*/ |
| 70 | /* define bus and isa numbers */ |
| 71 | for(bus_num = 0; bus_num < bus_isa; bus_num++) { |
| 72 | smp_write_bus(mc, bus_num, "PCI "); |
| 73 | } |
| 74 | smp_write_bus(mc, bus_isa, "ISA "); |
| 75 | |
| 76 | /*I/O APICs: APIC ID Version State Address*/ |
| 77 | { |
| 78 | device_t dev; |
| 79 | struct resource *res; |
| 80 | uint32_t dword; |
| 81 | |
| 82 | dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); |
| 83 | if (dev) { |
| 84 | res = find_resource(dev, PCI_BASE_ADDRESS_1); |
| 85 | if (res) { |
| 86 | smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base); |
| 87 | } |
| 88 | |
| 89 | dword = 0x43c6c643; |
| 90 | pci_write_config32(dev, 0x7c, dword); |
| 91 | |
| 92 | dword = 0x81001a00; |
| 93 | pci_write_config32(dev, 0x80, dword); |
| 94 | |
| 95 | dword = 0xd00012d2; |
| 96 | pci_write_config32(dev, 0x84, dword); |
| 97 | |
| 98 | } |
| 99 | |
| 100 | |
| 101 | |
| 102 | } |
| 103 | |
| 104 | /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# |
| 105 | */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0); |
| 106 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_mcp55, 0x1); |
| 107 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x2); |
| 108 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_mcp55, 0x3); |
| 109 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_mcp55, 0x4); |
| 110 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_mcp55, 0x6); |
| 111 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_mcp55, 0x7); |
| 112 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_mcp55, 0x8); |
| 113 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_mcp55, 0xc); |
| 114 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_mcp55, 0xd); |
| 115 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_mcp55, 0xe); |
| 116 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_mcp55, 0xf); |
| 117 | |
| 118 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa); |
| 119 | |
| 120 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22 |
| 121 | |
| 122 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23 |
| 123 | |
| 124 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23 |
| 125 | |
| 126 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20 |
| 127 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23 |
| 128 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21 |
| 129 | |
| 130 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22 |
| 131 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21 |
| 132 | |
| 133 | for(j=7; j>=2; j--) { |
| 134 | if(!bus_mcp55[j]) continue; |
| 135 | for(i=0;i<4;i++) { |
| 136 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); |
| 137 | } |
| 138 | } |
| 139 | |
| 140 | for(i=0;i<4;i++) { |
| 141 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4); |
| 142 | } |
| 143 | |
| 144 | |
| 145 | if(bus_pcix[0]) { |
| 146 | for(i=0;i<2;i++) { |
| 147 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 |
| 148 | } |
| 149 | |
| 150 | for(i=0;i<4;i++) { |
| 151 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4<<2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17 |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ |
| 156 | smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); |
| 157 | smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); |
| 158 | /* There is no extension information... */ |
| 159 | |
| 160 | /* Compute the checksums */ |
| 161 | mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); |
| 162 | mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); |
| 163 | printk_debug("Wrote the mp table end at: %p - %p\n", |
| 164 | mc, smp_next_mpe_entry(mc)); |
| 165 | return smp_next_mpe_entry(mc); |
| 166 | } |
| 167 | |
| 168 | unsigned long write_smp_table(unsigned long addr) |
| 169 | { |
| 170 | void *v; |
| 171 | v = smp_write_floating_table(addr); |
| 172 | return (unsigned long)smp_write_config_table(v); |
| 173 | } |