blob: 05d8fede53c98de9edde9a357344c5bfe60608c6 [file] [log] [blame]
bxshifaea4c52006-11-02 16:02:33 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
bxshifaea4c52006-11-02 16:02:33 +00003 *
4 * Copyright (C) 2006 AMD
5 * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
6 *
7 * Copyright (C) 2006 MSI
8 * Written by bxshi <bingxunshi@gmail.com> for MSI.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 */
24#include <console/console.h>
25#include <device/pci.h>
26#include <device/pci_ids.h>
27#include <string.h>
28#include <stdint.h>
29#if CONFIG_LOGICAL_CPUS==1
30#include <cpu/amd/dualcore.h>
31#endif
32
33#include <cpu/amd/amdk8_sysconf.h>
34
35#include "mb_sysconf.h"
36
37// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
38struct mb_sysconf_t mb_sysconf;
39
40static unsigned pci1234x[] =
41{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
42 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
43 0x0000ff0,
44 0x0000ff0,
45// 0x0000ff0,
46// 0x0000ff0,
47// 0x0000ff0,
48// 0x0000ff0,
49// 0x0000ff0,
50// 0x0000ff0
51};
52static unsigned hcdnx[] =
53{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
54 0x20202020,
55 0x20202020,
56// 0x20202020,
57// 0x20202020,
58// 0x20202020,
59// 0x20202020,
60// 0x20202020,
61// 0x20202020,
62};
63
64extern void get_sblk_pci1234(void);
65
66static unsigned get_bus_conf_done = 0;
67
68void get_bus_conf(void)
69{
70
71 unsigned apicid_base;
72
73 device_t dev;
74 int i;
75 struct mb_sysconf_t *m;
76
77 if(get_bus_conf_done==1) return; //do it only once
78
79 get_bus_conf_done = 1;
80
81 sysconf.mb = &mb_sysconf;
82
83 m = sysconf.mb;
84
85 sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
86
87 for(i=0;i<sysconf.hc_possible_num; i++) {
88 sysconf.pci1234[i] = pci1234x[i];
89 sysconf.hcdn[i] = hcdnx[i];
90 }
91
92 get_sblk_pci1234();
93
94 sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
95 m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780
96
97 m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff;
98 m->bus_bcm5780[0] = m->bus_bcm5785_0;
99
100 /* bcm5785 */
101 dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0));
102 if (dev) {
103 m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
104 dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0));
105 if(dev) {
106 m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
107#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
108 m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
109 m->bus_isa++;
110 printk_debug("bus_isa=%d\n",m->bus_isa);
111#endif
112 }
113 }
114 else {
115 printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn);
116 }
117
118 /* bcm5780 */
119 for(i = 1; i < 7; i++) {
120 dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0));
121 if(dev) {
122 m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
123#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
124 m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
125 m->bus_isa++;
126 printk_debug("bus_isa=%d\n",m->bus_isa);
127#endif
128
129 }
130 else {
131 printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1);
132 }
133 }
134
135
136/*I/O APICs: APIC ID Version State Address*/
137#if CONFIG_LOGICAL_CPUS==1
138 apicid_base = get_apicid_base(3);
139#else
140 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
141#endif
142 for(i=0;i<3;i++)
143 m->apicid_bcm5785[i] = apicid_base+i;
144}