Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 17 | * Foundation, Inc. |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <types.h> |
| 21 | #include <string.h> |
| 22 | #include <stdlib.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci_def.h> |
| 26 | #include <device/pci_ops.h> |
| 27 | #include <console/console.h> |
| 28 | #include <delay.h> |
| 29 | #include <pc80/mc146818rtc.h> |
| 30 | #include <arch/acpi.h> |
| 31 | #include <arch/io.h> |
| 32 | #include <arch/interrupt.h> |
| 33 | #include <boot/coreboot_tables.h> |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 34 | #include <smbios.h> |
| 35 | #include <device/pci.h> |
| 36 | #include <ec/google/chromeec/ec.h> |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 37 | |
| 38 | #include <cpu/x86/tsc.h> |
| 39 | #include <cpu/x86/cache.h> |
| 40 | #include <cpu/x86/mtrr.h> |
| 41 | #include <cpu/x86/msr.h> |
| 42 | #include <edid.h> |
| 43 | #include <drivers/intel/gma/i915.h> |
Ronald G. Minnich | 3a75e5e | 2013-10-28 15:01:54 -0700 | [diff] [blame] | 44 | #include <northbridge/intel/haswell/haswell.h> |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 45 | #include "mainboard.h" |
| 46 | |
| 47 | /* |
| 48 | * Here is the rough outline of how we bring up the display: |
| 49 | * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD |
| 50 | * 2. Source determines video mode by reading DPCD receiver capability field |
| 51 | * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD |
| 52 | * 0000Dh). |
| 53 | * 3. Sink replies DPCD receiver capability field. |
| 54 | * 4. Source starts EDID read thru I2C-over-AUX. |
| 55 | * 5. Sink replies EDID thru I2C-over-AUX. |
| 56 | * 6. Source determines link configuration, such as MAX_LINK_RATE and |
| 57 | * MAX_LANE_COUNT. Source also determines which type of eDP Authentication |
| 58 | * method to use and writes DPCD link configuration field (DPCD 00100h to |
| 59 | * 0010Ah) including eDP configuration set (DPCD 0010Ah). |
| 60 | * 7. Source starts link training. Sink does clock recovery and equalization. |
| 61 | * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh). |
| 62 | * 9. Sink replies DPCD link status field. If main link is not stable, Source |
| 63 | * repeats Step 7. |
| 64 | * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video |
| 65 | * parameters and recovers stream clock. |
| 66 | * 11. Source sends video data. |
| 67 | */ |
| 68 | |
| 69 | /* how many bytes do we need for the framebuffer? |
| 70 | * Well, this gets messy. To get an exact answer, we have |
| 71 | * to ask the panel, but we'd rather zero the memory |
| 72 | * and set up the gtt while the panel powers up. So, |
| 73 | * we take a reasonable guess, secure in the knowledge that the |
| 74 | * MRC has to overestimate the number of bytes used. |
| 75 | * 8 MiB is a very safe guess. There may be a better way later, but |
| 76 | * fact is, the initial framebuffer is only very temporary. And taking |
| 77 | * a little long is ok; this is done much faster than the AUX |
| 78 | * channel is ready for IO. |
| 79 | */ |
| 80 | #define FRAME_BUFFER_BYTES (8*MiB) |
| 81 | /* how many 4096-byte pages do we need for the framebuffer? |
| 82 | * There are hard ways to get this, and easy ways: |
| 83 | * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096 |
| 84 | * on this chip (and in fact every Intel graphics chip we've seen). |
| 85 | */ |
| 86 | #define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096)) |
| 87 | |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 88 | static int i915_init_done = 0; |
| 89 | |
| 90 | /* fill the palette. */ |
| 91 | static void palette(void) |
| 92 | { |
| 93 | int i; |
| 94 | unsigned long color = 0; |
| 95 | |
| 96 | for(i = 0; i < 256; i++, color += 0x010101){ |
| 97 | gtt_write(_LGC_PALETTE_A + (i<<2),color); |
| 98 | } |
| 99 | } |
| 100 | |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 101 | void mainboard_train_link(struct intel_dp *intel_dp) |
| 102 | { |
| 103 | u8 read_val; |
| 104 | u8 link_status[DP_LINK_STATUS_SIZE]; |
| 105 | |
| 106 | gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE); |
| 107 | gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011); |
| 108 | |
| 109 | intel_dp_get_training_pattern(intel_dp, &read_val); |
| 110 | intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); |
| 111 | intel_dp_get_lane_count(intel_dp, &read_val); |
| 112 | intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0); |
| 113 | intel_dp_get_link_status(intel_dp, link_status); |
| 114 | |
| 115 | gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2); |
| 116 | |
| 117 | intel_dp_get_training_pattern(intel_dp, &read_val); |
| 118 | intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); |
| 119 | intel_dp_get_link_status(intel_dp, link_status); |
| 120 | intel_dp_get_lane_align_status(intel_dp, &read_val); |
| 121 | intel_dp_get_training_pattern(intel_dp, &read_val); |
| 122 | intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); |
| 123 | } |
| 124 | |
| 125 | #define TEST_GFX 0 |
| 126 | |
| 127 | #if TEST_GFX |
| 128 | static void test_gfx(struct intel_dp *dp) |
| 129 | { |
| 130 | int i; |
| 131 | |
| 132 | /* This is a sanity test code which fills the screen with two bands -- |
| 133 | green and blue. It is very useful to ensure all the initializations |
| 134 | are made right. Thus, to be used only for testing, not otherwise |
| 135 | */ |
| 136 | for (i = 0; i < (dp->edid.va - 4); i++) { |
| 137 | u32 *l; |
| 138 | int j; |
| 139 | u32 tcolor = 0x0ff; |
| 140 | for (j = 0; j < (dp->edid.ha-4); j++) { |
| 141 | if (j == (dp->edid.ha/2)) { |
| 142 | tcolor = 0xff00; |
| 143 | } |
| 144 | l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor)); |
| 145 | memcpy(l,&tcolor,sizeof(tcolor)); |
| 146 | } |
| 147 | } |
| 148 | } |
| 149 | #else |
| 150 | static void test_gfx(struct intel_dp *dp) {} |
| 151 | #endif |
| 152 | |
| 153 | |
| 154 | void mainboard_set_port_clk_dp(struct intel_dp *intel_dp) |
| 155 | { |
| 156 | u32 ddi_pll_sel = 0; |
| 157 | |
| 158 | switch (intel_dp->link_bw) { |
| 159 | case DP_LINK_BW_1_62: |
| 160 | ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; |
| 161 | break; |
| 162 | case DP_LINK_BW_2_7: |
| 163 | ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; |
| 164 | break; |
| 165 | case DP_LINK_BW_5_4: |
| 166 | ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; |
| 167 | break; |
| 168 | default: |
| 169 | printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw); |
| 170 | return; |
| 171 | } |
| 172 | |
| 173 | gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel); |
| 174 | } |
| 175 | |
Ronald G. Minnich | 3a75e5e | 2013-10-28 15:01:54 -0700 | [diff] [blame] | 176 | int panel_lightup(struct intel_dp *dp, unsigned int init_fb) |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 177 | { |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 178 | int i; |
| 179 | int edid_ok; |
| 180 | int pixels = FRAME_BUFFER_BYTES/64; |
| 181 | |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 182 | void runio(struct intel_dp *dp); |
Ronald G. Minnich | 3a75e5e | 2013-10-28 15:01:54 -0700 | [diff] [blame] | 183 | |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 184 | dp->gen = 8; // This is gen 8 which we believe is Haswell |
| 185 | dp->is_haswell = 1; |
| 186 | dp->DP = 0x2; |
| 187 | /* These values are used for training the link */ |
| 188 | dp->lane_count = 2; |
| 189 | dp->link_bw = DP_LINK_BW_2_7; |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 190 | dp->pipe = PIPE_A; |
| 191 | dp->port = PORT_A; |
| 192 | dp->plane = PLANE_A; |
| 193 | dp->clock = 160000; |
| 194 | dp->pipe_bits_per_pixel = 32; |
| 195 | dp->type = INTEL_OUTPUT_EDP; |
| 196 | dp->output_reg = DP_A; |
| 197 | /* observed from YABEL. */ |
| 198 | dp->aux_clock_divider = 0xe1; |
| 199 | dp->precharge = 3; |
| 200 | |
| 201 | /* 1. Normal mode: Set the first page to zero and make |
| 202 | all GTT entries point to the same page |
| 203 | 2. Developer/Recovery mode: We do not zero out all |
| 204 | the pages pointed to by GTT in order to avoid wasting time */ |
Ronald G. Minnich | 3a75e5e | 2013-10-28 15:01:54 -0700 | [diff] [blame] | 205 | if (init_fb){ |
| 206 | set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 4096); |
| 207 | memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096); |
| 208 | } else { |
| 209 | set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0); |
| 210 | memset((void*)dp->graphics, 0, 4096); |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 211 | } |
| 212 | |
| 213 | dp->address = 0x50; |
| 214 | |
| 215 | if ( !intel_dp_get_dpcd(dp) ) |
| 216 | goto fail; |
| 217 | |
| 218 | intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL); |
| 219 | for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){ |
| 220 | if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ, |
| 221 | 0x50, &dp->rawedid[i]) < 0) |
| 222 | break; |
| 223 | dp->edidlen++; |
| 224 | } |
| 225 | |
| 226 | edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid); |
| 227 | printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); |
| 228 | |
Ronald G. Minnich | 3a75e5e | 2013-10-28 15:01:54 -0700 | [diff] [blame] | 229 | compute_display_params(dp); |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 230 | |
| 231 | intel_ddi_set_pipe_settings(dp); |
| 232 | |
| 233 | runio(dp); |
| 234 | |
| 235 | palette(); |
| 236 | |
David Hendricks | 7dbf9c6 | 2015-07-30 18:49:48 -0700 | [diff] [blame^] | 237 | pixels = dp->edid.mode.ha * (dp->edid.mode.va-4) * 4; |
| 238 | printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.mode.ha, dp->edid.mode.va); |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 239 | |
| 240 | test_gfx(dp); |
| 241 | |
Ronald G. Minnich | 3a75e5e | 2013-10-28 15:01:54 -0700 | [diff] [blame] | 242 | set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics); |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 243 | i915_init_done = 1; |
| 244 | return i915_init_done; |
| 245 | |
| 246 | fail: |
| 247 | printk(BIOS_SPEW, "Graphics could not be started;"); |
Ronald G. Minnich | 2120e0e2 | 2013-10-09 15:53:43 -0700 | [diff] [blame] | 248 | printk(BIOS_SPEW, "Returning.\n"); |
| 249 | return 0; |
| 250 | } |