Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | |
| 2 | config CPU_INTEL_HASWELL |
| 3 | bool |
| 4 | |
| 5 | if CPU_INTEL_HASWELL |
| 6 | |
| 7 | config CPU_SPECIFIC_OPTIONS |
| 8 | def_bool y |
| 9 | select SMP |
| 10 | select SSE2 |
| 11 | select UDELAY_LAPIC |
| 12 | select SMM_TSEG |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 13 | select SMM_MODULES |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 14 | select RELOCATABLE_MODULES |
Aaron Durbin | c0cbd6e | 2013-03-13 13:51:20 -0500 | [diff] [blame] | 15 | select DYNAMIC_CBMEM |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 16 | select CPU_MICROCODE_IN_CBFS |
| 17 | #select AP_IN_SIPI_WAIT |
| 18 | select TSC_SYNC_MFENCE |
Aaron Durbin | 6dccedd | 2012-12-03 16:17:40 -0600 | [diff] [blame] | 19 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 20 | |
| 21 | config BOOTBLOCK_CPU_INIT |
| 22 | string |
| 23 | default "cpu/intel/haswell/bootblock.c" |
| 24 | |
| 25 | config SERIAL_CPU_INIT |
| 26 | bool |
| 27 | default n |
| 28 | |
| 29 | config SMM_TSEG_SIZE |
| 30 | hex |
| 31 | default 0x800000 |
| 32 | |
Aaron Durbin | 8ce667e | 2013-02-15 21:45:06 -0600 | [diff] [blame] | 33 | config IED_REGION_SIZE |
| 34 | hex |
| 35 | default 0x400000 |
| 36 | |
| 37 | config SMM_RESERVED_SIZE |
| 38 | hex |
| 39 | default 0x100000 |
| 40 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 41 | config MICROCODE_INCLUDE_PATH |
| 42 | string |
| 43 | default "src/cpu/intel/haswell" |
| 44 | |
Aaron Durbin | b86113f | 2013-02-19 08:59:16 -0600 | [diff] [blame] | 45 | config RESET_ON_INVALID_RAMSTAGE_CACHE |
| 46 | bool "Reset the system on S3 wake when ramstage cache invalid." |
| 47 | default n |
| 48 | depends on RELOCATABLE_RAMSTAGE |
| 49 | help |
| 50 | The haswell romstage code caches the loaded ramstage program |
| 51 | in SMM space. On S3 wake the romstage will copy over a fresh |
| 52 | ramstage that was cached in the SMM space. This option determines |
| 53 | the action to take when the ramstage cache is invalid. If selected |
| 54 | the system will reset otherwise the ramstage will be reloaded from |
| 55 | cbfs. |
| 56 | |
Aaron Durbin | c46cc6f | 2013-04-29 16:57:10 -0500 | [diff] [blame] | 57 | config MONOTONIC_TIMER_MSR |
| 58 | def_bool n |
| 59 | depends on INTEL_LYNXPOINT_LP |
| 60 | select HAVE_MONOTONIC_TIMER |
| 61 | help |
| 62 | Provide a monotonic timer using the 24MHz MSR counter. |
| 63 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 64 | endif |