Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <arch/acpi.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <stdint.h> |
| 25 | #include <delay.h> |
| 26 | #include <cpu/intel/haswell/haswell.h> |
| 27 | #include <cpu/x86/msr.h> |
| 28 | #include <device/device.h> |
| 29 | #include <device/pci.h> |
| 30 | #include <device/pci_ids.h> |
| 31 | #include <device/hypertransport.h> |
| 32 | #include <stdlib.h> |
| 33 | #include <string.h> |
| 34 | #include <cpu/cpu.h> |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 35 | #include <cpu/x86/smm.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 36 | #include <boot/tables.h> |
| 37 | #include <cbmem.h> |
| 38 | #include "chip.h" |
| 39 | #include "haswell.h" |
| 40 | |
| 41 | static int bridge_revision_id = -1; |
| 42 | |
| 43 | int bridge_silicon_revision(void) |
| 44 | { |
| 45 | if (bridge_revision_id < 0) { |
| 46 | uint8_t stepping = cpuid_eax(1) & 0xf; |
| 47 | uint8_t bridge_id = pci_read_config16( |
| 48 | dev_find_slot(0, PCI_DEVFN(0, 0)), |
| 49 | PCI_DEVICE_ID) & 0xf0; |
| 50 | bridge_revision_id = bridge_id | stepping; |
| 51 | } |
| 52 | return bridge_revision_id; |
| 53 | } |
| 54 | |
| 55 | /* Reserve everything between A segment and 1MB: |
| 56 | * |
| 57 | * 0xa0000 - 0xbffff: legacy VGA |
| 58 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 59 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
| 60 | */ |
| 61 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
| 62 | static const int legacy_hole_size_k = 384; |
| 63 | |
| 64 | void cbmem_post_handling(void) |
| 65 | { |
| 66 | update_mrc_cache(); |
| 67 | } |
| 68 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 69 | static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 70 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 71 | u32 pciexbar_reg; |
| 72 | |
| 73 | *base = 0; |
| 74 | *len = 0; |
| 75 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 76 | pciexbar_reg = pci_read_config32(dev, index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 77 | |
| 78 | if (!(pciexbar_reg & (1 << 0))) |
| 79 | return 0; |
| 80 | |
| 81 | switch ((pciexbar_reg >> 1) & 3) { |
| 82 | case 0: // 256MB |
| 83 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); |
| 84 | *len = 256 * 1024 * 1024; |
| 85 | return 1; |
| 86 | case 1: // 128M |
| 87 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); |
| 88 | *len = 128 * 1024 * 1024; |
| 89 | return 1; |
| 90 | case 2: // 64M |
| 91 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); |
| 92 | *len = 64 * 1024 * 1024; |
| 93 | return 1; |
| 94 | } |
| 95 | |
| 96 | return 0; |
| 97 | } |
| 98 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 99 | static void pci_domain_set_resources(device_t dev) |
| 100 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 101 | assign_resources(dev->link_list); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | /* TODO We could determine how many PCIe busses we need in |
| 105 | * the bar. For now that number is hardcoded to a max of 64. |
| 106 | * See e7525/northbridge.c for an example. |
| 107 | */ |
| 108 | static struct device_operations pci_domain_ops = { |
| 109 | .read_resources = pci_domain_read_resources, |
| 110 | .set_resources = pci_domain_set_resources, |
| 111 | .enable_resources = NULL, |
| 112 | .init = NULL, |
| 113 | .scan_bus = pci_domain_scan_bus, |
| 114 | #if CONFIG_MMCONF_SUPPORT_DEFAULT |
| 115 | .ops_pci_bus = &pci_ops_mmconf, |
| 116 | #else |
| 117 | .ops_pci_bus = &pci_cf8_conf1, |
| 118 | #endif |
| 119 | }; |
| 120 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 121 | static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 122 | { |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 123 | u32 bar; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 124 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 125 | bar = pci_read_config32(dev, index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 126 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 127 | /* If not enabled don't report it. */ |
| 128 | if (!(bar & 0x1)) |
| 129 | return 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 130 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 131 | /* Knock down the enable bit. */ |
| 132 | *base = bar & ~1; |
| 133 | |
| 134 | return 1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 135 | } |
| 136 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 137 | /* There are special BARs that actually are programmed in the MCHBAR. These |
| 138 | * Intel special features, but they do consume resources that need to be |
| 139 | * accounted for. */ |
| 140 | static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, |
| 141 | u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 142 | { |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 143 | u32 bar; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 144 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 145 | bar = MCHBAR32(index); |
| 146 | |
| 147 | /* If not enabled don't report it. */ |
| 148 | if (!(bar & 0x1)) |
| 149 | return 0; |
| 150 | |
| 151 | /* Knock down the enable bit. */ |
| 152 | *base = bar & ~1; |
| 153 | |
| 154 | return 1; |
| 155 | } |
| 156 | |
| 157 | struct fixed_mmio_descriptor { |
| 158 | unsigned int index; |
| 159 | u32 size; |
| 160 | int (*get_resource)(device_t dev, unsigned int index, |
| 161 | u32 *base, u32 *size); |
| 162 | const char *description; |
| 163 | }; |
| 164 | |
| 165 | #define SIZE_KB(x) ((x)*1024) |
| 166 | struct fixed_mmio_descriptor mc_fixed_resources[] = { |
| 167 | { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, |
| 168 | { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, |
| 169 | { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, |
| 170 | { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, |
| 171 | { 0x5420, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, |
| 172 | { 0x5408, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, |
| 173 | }; |
| 174 | #undef SIZE_KB |
| 175 | |
| 176 | /* |
| 177 | * Add all known fixed MMIO ranges that hang off the host bridge/memory |
| 178 | * controller device. |
| 179 | */ |
| 180 | static void mc_add_fixed_mmio_resources(device_t dev) |
| 181 | { |
| 182 | int i; |
| 183 | |
| 184 | for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { |
| 185 | u32 base; |
| 186 | u32 size; |
| 187 | struct resource *resource; |
| 188 | unsigned int index; |
| 189 | |
| 190 | size = mc_fixed_resources[i].size; |
| 191 | index = mc_fixed_resources[i].index; |
| 192 | if (!mc_fixed_resources[i].get_resource(dev, index, |
| 193 | &base, &size)) |
| 194 | continue; |
| 195 | |
| 196 | resource = new_resource(dev, mc_fixed_resources[i].index); |
| 197 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
| 198 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 199 | IORESOURCE_ASSIGNED; |
| 200 | resource->base = base; |
| 201 | resource->size = size; |
| 202 | printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", |
| 203 | __func__, mc_fixed_resources[i].description, index, |
| 204 | (unsigned long)base, (unsigned long)(base + size - 1)); |
| 205 | } |
| 206 | } |
| 207 | |
| 208 | /* Host Memory Map: |
| 209 | * |
| 210 | * +--------------------------+ TOUUD |
| 211 | * | | |
| 212 | * +--------------------------+ 4GiB |
| 213 | * | PCI Address Space | |
| 214 | * +--------------------------+ TOLUD (also maps into MC address space) |
| 215 | * | iGD | |
| 216 | * +--------------------------+ BDSM |
| 217 | * | GTT | |
| 218 | * +--------------------------+ BGSM |
| 219 | * | TSEG | |
| 220 | * +--------------------------+ TSEGMB |
| 221 | * | Usage DRAM | |
| 222 | * +--------------------------+ 0 |
| 223 | * |
| 224 | * Some of the base registers above can be equal making the size of those |
| 225 | * regions 0. The reason is because the memory controller internally subtracts |
| 226 | * the base registers from each other to determine sizes of the regions. In |
| 227 | * other words, the memory map is in a fixed order no matter what. |
| 228 | */ |
| 229 | |
| 230 | struct map_entry { |
| 231 | int reg; |
| 232 | int is_64_bit; |
| 233 | int is_limit; |
| 234 | const char *description; |
| 235 | }; |
| 236 | |
| 237 | static void read_map_entry(device_t dev, struct map_entry *entry, |
| 238 | uint64_t *result) |
| 239 | { |
| 240 | uint64_t value; |
| 241 | uint64_t mask; |
| 242 | |
| 243 | /* All registers are on a 1MiB granularity. */ |
| 244 | mask = ((1ULL<<20)-1); |
| 245 | mask = ~mask; |
| 246 | |
| 247 | value = 0; |
| 248 | |
| 249 | if (entry->is_64_bit) { |
| 250 | value = pci_read_config32(dev, entry->reg + 4); |
| 251 | value <<= 32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 252 | } |
| 253 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 254 | value |= pci_read_config32(dev, entry->reg); |
| 255 | value &= mask; |
| 256 | |
| 257 | if (entry->is_limit) |
| 258 | value |= ~mask; |
| 259 | |
| 260 | *result = value; |
| 261 | } |
| 262 | |
| 263 | #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ |
| 264 | { \ |
| 265 | .reg = reg_, \ |
| 266 | .is_64_bit = is_64_, \ |
| 267 | .is_limit = is_limit_, \ |
| 268 | .description = desc_, \ |
| 269 | } |
| 270 | |
| 271 | #define MAP_ENTRY_BASE_64(reg_, desc_) \ |
| 272 | MAP_ENTRY(reg_, 1, 0, desc_) |
| 273 | #define MAP_ENTRY_LIMIT_64(reg_, desc_) \ |
| 274 | MAP_ENTRY(reg_, 1, 1, desc_) |
| 275 | #define MAP_ENTRY_BASE_32(reg_, desc_) \ |
| 276 | MAP_ENTRY(reg_, 0, 0, desc_) |
| 277 | |
| 278 | enum { |
| 279 | TOM_REG, |
| 280 | TOUUD_REG, |
| 281 | MESEG_BASE_REG, |
| 282 | MESEG_LIMIT_REG, |
| 283 | REMAP_BASE_REG, |
| 284 | REMAP_LIMIT_REG, |
| 285 | TOLUD_REG, |
| 286 | BGSM_REG, |
| 287 | BDSM_REG, |
| 288 | TSEG_REG, |
| 289 | // Must be last. |
| 290 | NUM_MAP_ENTRIES |
| 291 | }; |
| 292 | |
| 293 | static struct map_entry memory_map[NUM_MAP_ENTRIES] = { |
| 294 | [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), |
| 295 | [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), |
| 296 | [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), |
| 297 | [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), |
| 298 | [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), |
| 299 | [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), |
| 300 | [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), |
Aaron Durbin | 1570260 | 2012-12-21 22:18:58 -0600 | [diff] [blame] | 301 | [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), |
| 302 | [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 303 | [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), |
| 304 | }; |
| 305 | |
| 306 | static void mc_read_map_entries(device_t dev, uint64_t *values) |
| 307 | { |
| 308 | int i; |
| 309 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 310 | read_map_entry(dev, &memory_map[i], &values[i]); |
| 311 | } |
| 312 | } |
| 313 | |
| 314 | static void mc_report_map_entries(device_t dev, uint64_t *values) |
| 315 | { |
| 316 | int i; |
| 317 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 318 | printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", |
| 319 | memory_map[i].description, values[i]); |
| 320 | } |
| 321 | /* One can validate the BDSM and BGSM against the GGC. */ |
| 322 | printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); |
| 323 | } |
| 324 | |
| 325 | static void mc_add_dram_resources(device_t dev) |
| 326 | { |
| 327 | unsigned long base_k, size_k; |
| 328 | unsigned long index; |
| 329 | struct resource *resource; |
| 330 | uint64_t mc_values[NUM_MAP_ENTRIES]; |
| 331 | |
| 332 | /* Read in the MAP registers and report their values. */ |
| 333 | mc_read_map_entries(dev, &mc_values[0]); |
| 334 | mc_report_map_entries(dev, &mc_values[0]); |
| 335 | |
| 336 | /* |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 337 | * These are the host memory ranges that should be added: |
| 338 | * - 0 -> SMM_DEFAULT_BASE : cacheable |
| 339 | * - SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE : |
| 340 | * cacheable and reserved |
| 341 | * - SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 : cacheable |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 342 | * - 0xc0000 -> TSEG : cacheable |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 343 | * - TESG -> BGSM: cacheable with standard MTRRs and reserved |
| 344 | * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 345 | * - 4GiB -> TOUUD: cacheable |
| 346 | * |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 347 | * The default SMRAM space is reserved so that the range doesn't |
| 348 | * have to be saved during S3 Resume. Once marked reserved the OS |
| 349 | * cannot use the memory. This is a bit of an odd place to reserve |
| 350 | * the region, but the CPU devices don't have dev_ops->read_resources() |
| 351 | * called on them. |
| 352 | * |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 353 | * The range 0xa0000 -> 0xc0000 does not have any resources |
| 354 | * associated with it to handle legacy VGA memory. If this range |
| 355 | * is not omitted the mtrr code will setup the area as cacheable |
| 356 | * causing VGA access to not work. |
| 357 | * |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 358 | * The TSEG region is mapped as cacheable so that one can perform |
| 359 | * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes |
| 360 | * precedence over the existing MTRRs covering this region. |
| 361 | * |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 362 | * It should be noted that cacheable entry types need to be added in |
| 363 | * order. The reason is that the current MTRR code assumes this and |
| 364 | * falls over itself if it isn't. |
| 365 | * |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 366 | * The resource index starts low and should not meet or exceed |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 367 | * PCI_BASE_ADDRESS_0. |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 368 | */ |
| 369 | index = 0; |
| 370 | |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 371 | /* 0 - > SMM_DEFAULT_BASE */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 372 | base_k = 0; |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 373 | size_k = SMM_DEFAULT_BASE >> 10; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 374 | ram_resource(dev, index++, base_k, size_k); |
| 375 | |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 376 | /* SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE */ |
| 377 | resource = new_resource(dev, index++); |
| 378 | resource->base = SMM_DEFAULT_BASE; |
| 379 | resource->size = SMM_DEFAULT_SIZE; |
| 380 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
| 381 | IORESOURCE_CACHEABLE | IORESOURCE_STORED | |
| 382 | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; |
| 383 | |
| 384 | /* SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 */ |
| 385 | base_k = (SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE) >> 10; |
| 386 | size_k = (0xa0000 >> 10) - base_k; |
| 387 | ram_resource(dev, index++, base_k, size_k); |
| 388 | |
| 389 | /* 0xc0000 -> TSEG */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 390 | base_k = 0xc0000 >> 10; |
| 391 | size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; |
| 392 | ram_resource(dev, index++, base_k, size_k); |
| 393 | |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 394 | /* TSEG -> BGSM */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 395 | resource = new_resource(dev, index++); |
| 396 | resource->base = mc_values[TSEG_REG]; |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 397 | resource->size = mc_values[BGSM_REG] - resource->base; |
| 398 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
| 399 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 400 | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; |
| 401 | |
| 402 | /* BGSM -> TOLUD */ |
| 403 | resource = new_resource(dev, index++); |
| 404 | resource->base = mc_values[BGSM_REG]; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 405 | resource->size = mc_values[TOLUD_REG] - resource->base; |
| 406 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
| 407 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 408 | IORESOURCE_ASSIGNED; |
| 409 | |
| 410 | /* 4GiB -> TOUUD */ |
| 411 | base_k = 4096 * 1024; /* 4GiB */ |
| 412 | size_k = (unsigned long)(mc_values[TOUUD_REG] >> 10) - base_k; |
Aaron Durbin | 5c66f08 | 2013-01-08 10:10:33 -0600 | [diff] [blame] | 413 | if (size_k > 0) |
| 414 | ram_resource(dev, index++, base_k, size_k); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 415 | |
| 416 | mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); |
| 417 | #if CONFIG_CHROMEOS_RAMOOPS |
| 418 | mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, |
| 419 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); |
| 420 | #endif |
| 421 | |
| 422 | /* Leave some space for ACPI, PIRQ and MP tables */ |
| 423 | high_tables_size = HIGH_MEMORY_SIZE; |
| 424 | high_tables_base = mc_values[TSEG_REG] - high_tables_size; |
| 425 | } |
| 426 | |
| 427 | static void mc_read_resources(device_t dev) |
| 428 | { |
| 429 | /* Read standard PCI resources. */ |
| 430 | pci_dev_read_resources(dev); |
| 431 | |
| 432 | /* Add all fixed MMIO resources. */ |
| 433 | mc_add_fixed_mmio_resources(dev); |
| 434 | |
| 435 | /* Calculate and add DRAM resources. */ |
| 436 | mc_add_dram_resources(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 437 | } |
| 438 | |
| 439 | static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 440 | { |
| 441 | if (!vendor || !device) { |
| 442 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 443 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 444 | } else { |
| 445 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 446 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 447 | } |
| 448 | } |
| 449 | |
| 450 | static void northbridge_dmi_init(struct device *dev) |
| 451 | { |
| 452 | u32 reg32; |
| 453 | |
| 454 | /* Clear error status bits */ |
| 455 | DMIBAR32(0x1c4) = 0xffffffff; |
| 456 | DMIBAR32(0x1d0) = 0xffffffff; |
| 457 | |
| 458 | /* Steps prior to DMI ASPM */ |
| 459 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 460 | reg32 = DMIBAR32(0x250); |
| 461 | reg32 &= ~((1 << 22)|(1 << 20)); |
| 462 | reg32 |= (1 << 21); |
| 463 | DMIBAR32(0x250) = reg32; |
| 464 | } |
| 465 | |
| 466 | reg32 = DMIBAR32(0x238); |
| 467 | reg32 |= (1 << 29); |
| 468 | DMIBAR32(0x238) = reg32; |
| 469 | |
| 470 | if (bridge_silicon_revision() >= SNB_STEP_D0) { |
| 471 | reg32 = DMIBAR32(0x1f8); |
| 472 | reg32 |= (1 << 16); |
| 473 | DMIBAR32(0x1f8) = reg32; |
| 474 | } else if (bridge_silicon_revision() >= SNB_STEP_D1) { |
| 475 | reg32 = DMIBAR32(0x1f8); |
| 476 | reg32 &= ~(1 << 26); |
| 477 | reg32 |= (1 << 16); |
| 478 | DMIBAR32(0x1f8) = reg32; |
| 479 | |
| 480 | reg32 = DMIBAR32(0x1fc); |
| 481 | reg32 |= (1 << 12) | (1 << 23); |
| 482 | DMIBAR32(0x1fc) = reg32; |
| 483 | } |
| 484 | |
| 485 | /* Enable ASPM on SNB link, should happen before PCH link */ |
| 486 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 487 | reg32 = DMIBAR32(0xd04); |
| 488 | reg32 |= (1 << 4); |
| 489 | DMIBAR32(0xd04) = reg32; |
| 490 | } |
| 491 | |
| 492 | reg32 = DMIBAR32(0x88); |
| 493 | reg32 |= (1 << 1) | (1 << 0); |
| 494 | DMIBAR32(0x88) = reg32; |
| 495 | } |
| 496 | |
| 497 | static void northbridge_init(struct device *dev) |
| 498 | { |
| 499 | u8 bios_reset_cpl; |
| 500 | u32 bridge_type; |
| 501 | |
| 502 | northbridge_dmi_init(dev); |
| 503 | |
| 504 | bridge_type = MCHBAR32(0x5f10); |
| 505 | bridge_type &= ~0xff; |
| 506 | |
| 507 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
| 508 | /* Enable Power Aware Interrupt Routing */ |
| 509 | u8 pair = MCHBAR8(0x5418); |
| 510 | pair &= ~0xf; /* Clear 3:0 */ |
| 511 | pair |= 0x4; /* Fixed Priority */ |
| 512 | MCHBAR8(0x5418) = pair; |
| 513 | |
| 514 | /* 30h for IvyBridge */ |
| 515 | bridge_type |= 0x30; |
| 516 | } else { |
| 517 | /* 20h for Sandybridge */ |
| 518 | bridge_type |= 0x20; |
| 519 | } |
| 520 | MCHBAR32(0x5f10) = bridge_type; |
| 521 | |
| 522 | /* |
| 523 | * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU |
| 524 | * that BIOS has initialized memory and power management |
| 525 | */ |
| 526 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
| 527 | bios_reset_cpl |= 1; |
| 528 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 529 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 530 | |
| 531 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 532 | mdelay(1); |
| 533 | set_power_limits(28); |
| 534 | |
| 535 | /* |
| 536 | * CPUs with configurable TDP also need power limits set |
| 537 | * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. |
| 538 | */ |
| 539 | if (cpu_config_tdp_levels()) { |
| 540 | msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); |
| 541 | MCHBAR32(0x59A0) = msr.lo; |
| 542 | MCHBAR32(0x59A4) = msr.hi; |
| 543 | } |
| 544 | |
| 545 | /* Set here before graphics PM init */ |
| 546 | MCHBAR32(0x5500) = 0x00100001; |
| 547 | } |
| 548 | |
| 549 | static void northbridge_enable(device_t dev) |
| 550 | { |
| 551 | #if CONFIG_HAVE_ACPI_RESUME |
| 552 | switch (pci_read_config32(dev, SKPAD)) { |
| 553 | case 0xcafebabe: |
| 554 | printk(BIOS_DEBUG, "Normal boot.\n"); |
| 555 | acpi_slp_type=0; |
| 556 | break; |
| 557 | case 0xcafed00d: |
| 558 | printk(BIOS_DEBUG, "S3 Resume.\n"); |
| 559 | acpi_slp_type=3; |
| 560 | break; |
| 561 | default: |
| 562 | printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); |
| 563 | acpi_slp_type=0; |
| 564 | break; |
| 565 | } |
| 566 | #endif |
| 567 | } |
| 568 | |
| 569 | static struct pci_operations intel_pci_ops = { |
| 570 | .set_subsystem = intel_set_subsystem, |
| 571 | }; |
| 572 | |
| 573 | static struct device_operations mc_ops = { |
| 574 | .read_resources = mc_read_resources, |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 575 | .set_resources = pci_dev_set_resources, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 576 | .enable_resources = pci_dev_enable_resources, |
| 577 | .init = northbridge_init, |
| 578 | .enable = northbridge_enable, |
| 579 | .scan_bus = 0, |
| 580 | .ops_pci = &intel_pci_ops, |
| 581 | }; |
| 582 | |
Aaron Durbin | c1989c4 | 2012-12-11 17:13:17 -0600 | [diff] [blame] | 583 | static const struct pci_driver mc_driver_hsw_mobile __pci_driver = { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 584 | .ops = &mc_ops, |
| 585 | .vendor = PCI_VENDOR_ID_INTEL, |
Aaron Durbin | c1989c4 | 2012-12-11 17:13:17 -0600 | [diff] [blame] | 586 | .device = 0x0c04, /* Mobile Haswell */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 587 | }; |
| 588 | |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 589 | static const struct pci_driver mc_driver_hsw_ult __pci_driver = { |
| 590 | .ops = &mc_ops, |
| 591 | .vendor = PCI_VENDOR_ID_INTEL, |
| 592 | .device = 0x0a04, /* ULT Haswell */ |
| 593 | }; |
| 594 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 595 | static void cpu_bus_init(device_t dev) |
| 596 | { |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 597 | /* |
| 598 | * This calls into the gerneic initialize_cpus() which attempts to |
| 599 | * start APs on the APIC bus in the devicetree. No APs get started |
| 600 | * because there is only the BSP and placeholder (disabled) in the |
| 601 | * devicetree. initialize_cpus() also does SMM initialization by way |
| 602 | * of smm_init(). It will eventually call cpu_initialize(0) which calls |
| 603 | * dev_ops->init(). For Haswell the dev_ops->init() starts up the APs |
| 604 | * by way of intel_cores_init(). |
| 605 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 606 | initialize_cpus(dev->link_list); |
| 607 | } |
| 608 | |
| 609 | static void cpu_bus_noop(device_t dev) |
| 610 | { |
| 611 | } |
| 612 | |
| 613 | static struct device_operations cpu_bus_ops = { |
| 614 | .read_resources = cpu_bus_noop, |
| 615 | .set_resources = cpu_bus_noop, |
| 616 | .enable_resources = cpu_bus_noop, |
| 617 | .init = cpu_bus_init, |
| 618 | .scan_bus = 0, |
| 619 | }; |
| 620 | |
| 621 | static void enable_dev(device_t dev) |
| 622 | { |
| 623 | /* Set the operations if it is a special bus type */ |
| 624 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 625 | dev->ops = &pci_domain_ops; |
| 626 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 627 | dev->ops = &cpu_bus_ops; |
| 628 | } |
| 629 | } |
| 630 | |
| 631 | struct chip_operations northbridge_intel_haswell_ops = { |
| 632 | CHIP_NAME("Intel i7 (Haswell) integrated Northbridge") |
| 633 | .enable_dev = enable_dev, |
| 634 | }; |