blob: 2980622fc9f3574abda4ea19b33e5fc35a91535a [file] [log] [blame]
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001/*
2 * This file is part of the coreboot project.
3 *
Marshall Dawsone7d892c2016-10-08 14:49:41 -06004 * Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc.
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/*
17 * ROMSIG At ROMBASE + 0x20000:
zbaoc3b0b722016-02-19 13:47:31 +080018 * 0 4 8 C
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080019 * +------------+---------------+----------------+------------+
20 * | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
21 * +------------+---------------+----------------+------------+
zbaoc3b0b722016-02-19 13:47:31 +080022 * | PSPDIR ADDR|PSPDIR ADDR |<-- Field 0x14 could be either
23 * +------------+---------------+ 2nd PSP directory or PSP COMBO directory
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080024 * EC ROM should be 64K aligned.
25 *
Zheng Bao4fcc9f22015-11-20 12:29:04 +080026 * PSP directory (Where "PSPDIR ADDR" points)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080027 * +------------+---------------+----------------+------------+
28 * | 'PSP$' | Fletcher | Count | Reserved |
29 * +------------+---------------+----------------+------------+
30 * | 0 | size | Base address | Reserved | Pubkey
31 * +------------+---------------+----------------+------------+
32 * | 1 | size | Base address | Reserved | Bootloader
33 * +------------+---------------+----------------+------------+
34 * | 8 | size | Base address | Reserved | Smu Firmware
35 * +------------+---------------+----------------+------------+
36 * | 3 | size | Base address | Reserved | Recovery Firmware
37 * +------------+---------------+----------------+------------+
38 * | |
39 * | |
40 * | Other PSP Firmware |
41 * | |
42 * | |
43 * +------------+---------------+----------------+------------+
Zheng Bao4fcc9f22015-11-20 12:29:04 +080044 *
zbaoc3b0b722016-02-19 13:47:31 +080045 * PSP Combo directory
Zheng Bao4fcc9f22015-11-20 12:29:04 +080046 * +------------+---------------+----------------+------------+
zbao6e2f3d12016-02-19 13:34:59 +080047 * | 'PSP2' | Fletcher | Count |Look up mode|
Zheng Bao4fcc9f22015-11-20 12:29:04 +080048 * +------------+---------------+----------------+------------+
zbaoc3a08a92016-03-02 14:47:27 +080049 * | R e s e r v e d |
50 * +------------+---------------+----------------+------------+
zbao6e2f3d12016-02-19 13:34:59 +080051 * | ID-Sel | PSP ID | PSPDIR ADDR | | 2nd PSP directory
Zheng Bao4fcc9f22015-11-20 12:29:04 +080052 * +------------+---------------+----------------+------------+
zbao6e2f3d12016-02-19 13:34:59 +080053 * | ID-Sel | PSP ID | PSPDIR ADDR | | 3rd PSP directory
Zheng Bao4fcc9f22015-11-20 12:29:04 +080054 * +------------+---------------+----------------+------------+
55 * | |
56 * | Other PSP |
57 * | |
58 * +------------+---------------+----------------+------------+
59 *
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080060 */
61
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080062#include <fcntl.h>
63#include <errno.h>
64#include <stdio.h>
65#include <sys/stat.h>
66#include <sys/types.h>
67#include <unistd.h>
68#include <string.h>
69#include <stdlib.h>
70#include <getopt.h>
71
72#ifndef CONFIG_ROM_SIZE
73#define CONFIG_ROM_SIZE 0x400000
74#endif
75
Martin Roth60f15512016-11-08 09:55:01 -070076#define AMD_ROMSIG_OFFSET 0x20000
77#define MIN_ROM_KB 256
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080078
Martin Rothcd15bc82016-11-08 11:34:02 -070079#define ALIGN(val, by) (((val) + (by) - 1) & ~((by) - 1))
Marshall Dawson7c1e1422019-04-11 09:44:43 -060080#define _MAX(A, B) (((A) > (B)) ? (A) : (B))
81#define ERASE_ALIGNMENT 0x1000U
Marshall Dawson2794a862019-03-04 16:53:15 -070082#define TABLE_ALIGNMENT 0x1000U
83#define BLOB_ALIGNMENT 0x100U
Marshall Dawson24f73d42019-04-01 10:48:43 -060084#define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT)
Marshall Dawson7c1e1422019-04-11 09:44:43 -060085#define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080086
Marshall Dawsonef79fcc2019-04-01 10:16:41 -060087#define DEFAULT_SOFT_FUSE_CHAIN "0x1"
88
Marshall Dawson239286c2019-02-23 16:42:46 -070089#define EMBEDDED_FW_SIGNATURE 0x55aa55aa
Marshall Dawson24f73d42019-04-01 10:48:43 -060090#define PSP_COOKIE 0x50535024 /* 'PSP$' */
91#define PSPL2_COOKIE 0x324c5024 /* '2LP$' */
92#define PSP2_COOKIE 0x50535032 /* 'PSP2' */
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -060093#define BDT1_COOKIE 0x44484224 /* 'DHB$ */
94#define BDT2_COOKIE 0x324c4224 /* '2LB$ */
Marshall Dawson239286c2019-02-23 16:42:46 -070095
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080096/*
Marshall Dawson0e02ce82019-03-04 16:50:37 -070097 * Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP
98 * can support an optional "combo" implementation. If the PSP sees the
99 * PSP2 cookie, it interprets the table as a roadmap to additional PSP
100 * tables. Using this, support for multiple product generations may be
101 * built into one image. If the PSP$ cookie is found, the table is a
102 * normal directory table.
103 *
104 * Modern generations supporting the combo directories require the
105 * pointer to be at offset 0x14 of the Embedded Firmware Structure,
106 * regardless of the type of directory used. The --combo-capable
107 * argument enforces this placement.
108 *
109 * TODO: Future work may require fully implementing the PSP_COMBO feature.
zbaoc3b0b722016-02-19 13:47:31 +0800110 */
Marshall Dawson0e02ce82019-03-04 16:50:37 -0700111#define PSP_COMBO 0
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800112
Marshall Dawson239286c2019-02-23 16:42:46 -0700113typedef unsigned long long int uint64_t;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800114typedef unsigned int uint32_t;
115typedef unsigned char uint8_t;
116typedef unsigned short uint16_t;
117
118/*
119 * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3.
120 * The checksum field of the passed PDU does not need to be reset to zero.
121 *
122 * The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of
123 * Lawrence Livermore Labs. The Fletcher Checksum was proposed as an
124 * alternative to cyclical redundancy checks because it provides error-
125 * detection properties similar to cyclical redundancy checks but at the
126 * cost of a simple summation technique. Its characteristics were first
127 * published in IEEE Transactions on Communications in January 1982. One
128 * version has been adopted by ISO for use in the class-4 transport layer
129 * of the network protocol.
130 *
131 * This program expects:
132 * stdin: The input file to compute a checksum for. The input file
133 * not be longer than 256 bytes.
134 * stdout: Copied from the input file with the Fletcher's Checksum
135 * inserted 8 bytes after the beginning of the file.
136 * stderr: Used to print out error messages.
137 */
Marshall Dawson8a45a4d2019-02-24 07:18:44 -0700138static uint32_t fletcher32(const void *data, int length)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800139{
140 uint32_t c0;
141 uint32_t c1;
142 uint32_t checksum;
143 int index;
Marshall Dawson8a45a4d2019-02-24 07:18:44 -0700144 const uint16_t *pptr = data;
145
146 length /= 2;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800147
148 c0 = 0xFFFF;
149 c1 = 0xFFFF;
150
Marshall Dawsonb85ddc52019-07-23 07:24:30 -0600151 while (length) {
152 index = length >= 359 ? 359 : length;
153 length -= index;
154 do {
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800155 c0 += *(pptr++);
156 c1 += c0;
Marshall Dawsonb85ddc52019-07-23 07:24:30 -0600157 } while (--index);
158 c0 = (c0 & 0xFFFF) + (c0 >> 16);
159 c1 = (c1 & 0xFFFF) + (c1 >> 16);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800160 }
161
Marshall Dawson8a45a4d2019-02-24 07:18:44 -0700162 /* Sums[0,1] mod 64K + overflow */
163 c0 = (c0 & 0xFFFF) + (c0 >> 16);
164 c1 = (c1 & 0xFFFF) + (c1 >> 16);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800165 checksum = (c1 << 16) | c0;
166
167 return checksum;
168}
169
Martin Roth8806f7f2016-11-08 10:44:18 -0700170static void usage(void)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800171{
Martin Roth0e940622016-11-08 10:37:53 -0700172 printf("amdfwtool: Create AMD Firmware combination\n");
173 printf("Usage: amdfwtool [options] -f <size> -o <filename>\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600174 printf("-x | --xhci <FILE> Add XHCI blob\n");
175 printf("-i | --imc <FILE> Add IMC blob\n");
176 printf("-g | --gec <FILE> Add GEC blob\n");
Martin Roth0e940622016-11-08 10:37:53 -0700177
178 printf("\nPSP options:\n");
Marshall Dawson67d868d2019-02-28 11:43:40 -0700179 printf("-A | --combo-capable Place PSP directory pointer at Embedded Firmware\n");
180 printf(" offset able to support combo directory\n");
Marshall Dawson24f73d42019-04-01 10:48:43 -0600181 printf("-M | --multilevel Generate primary and secondary tables\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600182 printf("-p | --pubkey <FILE> Add pubkey\n");
183 printf("-b | --bootloader <FILE> Add bootloader\n");
Marshall Dawsondbae6322019-03-04 10:31:03 -0700184 printf("-S | --subprogram <number> Sets subprogram field for the next firmware\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600185 printf("-s | --smufirmware <FILE> Add smufirmware\n");
186 printf("-r | --recovery <FILE> Add recovery\n");
187 printf("-k | --rtmpubkey <FILE> Add rtmpubkey\n");
188 printf("-c | --secureos <FILE> Add secureos\n");
189 printf("-n | --nvram <FILE> Add nvram\n");
190 printf("-d | --securedebug <FILE> Add securedebug\n");
191 printf("-t | --trustlets <FILE> Add trustlets\n");
192 printf("-u | --trustletkey <FILE> Add trustletkey\n");
193 printf("-w | --smufirmware2 <FILE> Add smufirmware2\n");
194 printf("-m | --smuscs <FILE> Add smuscs\n");
Marshall Dawsonef79fcc2019-04-01 10:16:41 -0600195 printf("-T | --soft-fuse <HEX_VAL> Override default soft fuse values\n");
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600196 printf("-z | --abl-image <FILE> Add AGESA Binary\n");
197 printf("-J | --sec-gasket <FILE> Add security gasket\n");
198 printf("-B | --mp2-fw <FILE> Add MP2 firmware\n");
199 printf("-N | --secdebug <FILE> Add secure unlock image\n");
200 printf("-U | --token-unlock Reserve space for debug token\n");
201 printf("-K | --drv-entry-pts <FILE> Add PSP driver entry points\n");
202 printf("-L | --ikek <FILE> Add Wrapped iKEK\n");
203 printf("-Y | --s0i3drv <FILE> Add s0i3 driver\n");
Martin Rothd3ce8c82019-07-13 20:13:07 -0600204 printf("-Z | --verstage <FILE> Add verstage\n");
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600205 printf("\nBIOS options:\n");
206 printf("-I | --instance <number> Sets instance field for the next BIOS firmware\n");
207 printf("-a | --apcb <FILE> Add AGESA PSP customization block\n");
208 printf("-Q | --apob-base <HEX_VAL> Destination for AGESA PSP output block\n");
209 printf("-F | --apob-nv-base <HEX_VAL> Location of S3 resume data\n");
210 printf("-H | --apob-nv-size <HEX_VAL> Size of S3 resume data\n");
211 printf("-y | --pmu-inst <FILE> Add PMU firmware instruction portion\n");
212 printf("-G | --pmu-data <FILE> Add PMU firmware data portion\n");
Martin Rothec933132019-07-13 20:03:34 -0600213 printf("-O | --ucode <FILE> Add microcode patch\n");
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600214 printf("-X | --mp2-config <FILE> Add MP2 configuration\n");
215 printf("-V | --bios-bin <FILE> Add compressed image; auto source address\n");
216 printf("-e | --bios-bin-src <HEX_VAL> Address in flash of source if -V not used\n");
217 printf("-v | --bios-bin-dest <HEX_VAL> Destination for uncompressed BIOS\n");
218 printf("-j | --bios-uncomp-size <HEX> Uncompressed size of BIOS image\n");
Martin Roth0e940622016-11-08 10:37:53 -0700219 printf("\n-o | --output <filename> output filename\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600220 printf("-f | --flashsize <HEX_VAL> ROM size in bytes\n");
221 printf(" size must be larger than %dKB\n",
Martin Roth0e940622016-11-08 10:37:53 -0700222 MIN_ROM_KB);
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600223 printf(" and must a multiple of 1024\n");
Martin Roth0d3b1182017-10-03 14:16:04 -0600224 printf("-l | --location Location of Directory\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600225 printf("-h | --help show this help\n");
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800226}
227
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600228typedef enum _amd_bios_type {
229 AMD_BIOS_APCB = 0x60,
230 AMD_BIOS_APOB = 0x61,
231 AMD_BIOS_BIN = 0x62,
232 AMD_BIOS_APOB_NV = 0x63,
233 AMD_BIOS_PMUI = 0x64,
234 AMD_BIOS_PMUD = 0x65,
235 AMD_BIOS_UCODE = 0x66,
236 AMD_BIOS_APCB_BK = 0x68,
237 AMD_BIOS_MP2_CFG = 0x6a,
238 AMD_BIOS_L2_PTR = 0x70,
239 AMD_BIOS_INVALID,
240} amd_bios_type;
241
242#define BDT_LVL1 0x1
243#define BDT_LVL2 0x2
244#define BDT_BOTH (BDT_LVL1 | BDT_LVL2)
245typedef struct _amd_bios_entry {
246 amd_bios_type type;
247 int region_type;
248 int reset;
249 int copy;
250 int ro;
251 int zlib;
252 int inst;
253 int subpr;
254 uint64_t src;
255 uint64_t dest;
256 size_t size;
257 char *filename;
258 int level;
259} amd_bios_entry;
260
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800261typedef enum _amd_fw_type {
262 AMD_FW_PSP_PUBKEY = 0,
263 AMD_FW_PSP_BOOTLOADER = 1,
264 AMD_FW_PSP_SMU_FIRMWARE = 8,
265 AMD_FW_PSP_RECOVERY = 3,
266 AMD_FW_PSP_RTM_PUBKEY = 5,
267 AMD_FW_PSP_SECURED_OS = 2,
268 AMD_FW_PSP_NVRAM = 4,
269 AMD_FW_PSP_SECURED_DEBUG = 9,
270 AMD_FW_PSP_TRUSTLETS = 12,
271 AMD_FW_PSP_TRUSTLETKEY = 13,
272 AMD_FW_PSP_SMU_FIRMWARE2 = 18,
273 AMD_PSP_FUSE_CHAIN = 11,
274 AMD_FW_PSP_SMUSCS = 95,
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600275 AMD_DEBUG_UNLOCK = 0x13,
276 AMD_WRAPPED_IKEK = 0x21,
277 AMD_TOKEN_UNLOCK = 0x22,
278 AMD_SEC_GASKET = 0x24,
279 AMD_MP2_FW = 0x25,
280 AMD_DRIVER_ENTRIES = 0x28,
281 AMD_S0I3_DRIVER = 0x2d,
282 AMD_ABL0 = 0x30,
283 AMD_ABL1 = 0x31,
284 AMD_ABL2 = 0x32,
285 AMD_ABL3 = 0x33,
286 AMD_ABL4 = 0x34,
287 AMD_ABL5 = 0x35,
288 AMD_ABL6 = 0x36,
289 AMD_ABL7 = 0x37,
290 AMD_FW_PSP_WHITELIST = 0x3a,
Marshall Dawson24f73d42019-04-01 10:48:43 -0600291 AMD_FW_L2_PTR = 0x40,
Martin Rothd3ce8c82019-07-13 20:13:07 -0600292 AMD_FW_PSP_VERSTAGE = 0x52,
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800293 AMD_FW_IMC,
294 AMD_FW_GEC,
295 AMD_FW_XHCI,
zbaoc3a08a92016-03-02 14:47:27 +0800296 AMD_FW_INVALID,
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800297} amd_fw_type;
298
Marshall Dawson24f73d42019-04-01 10:48:43 -0600299#define PSP_LVL1 0x1
300#define PSP_LVL2 0x2
301#define PSP_BOTH (PSP_LVL1 | PSP_LVL2)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800302typedef struct _amd_fw_entry {
303 amd_fw_type type;
Marshall Dawsondbae6322019-03-04 10:31:03 -0700304 uint8_t subprog;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800305 char *filename;
Marshall Dawson24f73d42019-04-01 10:48:43 -0600306 int level;
Marshall Dawsonef79fcc2019-04-01 10:16:41 -0600307 uint64_t other;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800308} amd_fw_entry;
309
Martin Roth8806f7f2016-11-08 10:44:18 -0700310static amd_fw_entry amd_psp_fw_table[] = {
Marshall Dawson24f73d42019-04-01 10:48:43 -0600311 { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH },
312 { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH },
313 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH },
314 { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 },
315 { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH },
316 { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 },
317 { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 },
318 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH },
319 { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 },
320 { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 },
321 { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 },
322 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH },
323 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH },
324 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH },
325 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH },
326 { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH },
327 { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600328 { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 },
329 { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH },
330 { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH },
331 { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH },
332 { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH },
333 { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 },
334 { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 },
335 { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 },
336 { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 },
337 { .type = AMD_ABL0, .level = PSP_BOTH },
338 { .type = AMD_ABL1, .level = PSP_BOTH },
339 { .type = AMD_ABL2, .level = PSP_BOTH },
340 { .type = AMD_ABL3, .level = PSP_BOTH },
341 { .type = AMD_ABL4, .level = PSP_BOTH },
342 { .type = AMD_ABL5, .level = PSP_BOTH },
343 { .type = AMD_ABL6, .level = PSP_BOTH },
344 { .type = AMD_ABL7, .level = PSP_BOTH },
Marshall Dawson24f73d42019-04-01 10:48:43 -0600345 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH },
346 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600347 { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 },
Martin Rothd3ce8c82019-07-13 20:13:07 -0600348 { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH },
zbaoc3a08a92016-03-02 14:47:27 +0800349 { .type = AMD_FW_INVALID },
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800350};
351
Martin Roth8806f7f2016-11-08 10:44:18 -0700352static amd_fw_entry amd_fw_table[] = {
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800353 { .type = AMD_FW_XHCI },
354 { .type = AMD_FW_IMC },
355 { .type = AMD_FW_GEC },
zbaoc3a08a92016-03-02 14:47:27 +0800356 { .type = AMD_FW_INVALID },
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800357};
358
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600359static amd_bios_entry amd_bios_table[] = {
360 { .type = AMD_BIOS_APCB, .level = BDT_BOTH },
361 { .type = AMD_BIOS_APCB_BK, .level = BDT_BOTH },
362 { .type = AMD_BIOS_APOB, .level = BDT_BOTH },
363 { .type = AMD_BIOS_BIN,
364 .reset = 1, .copy = 1, .zlib = 1, .level = BDT_BOTH },
365 { .type = AMD_BIOS_APOB_NV, .level = BDT_LVL2 },
366 { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 0, .level = BDT_BOTH },
367 { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH },
368 { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 0, .level = BDT_BOTH },
369 { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 0, .level = BDT_BOTH },
370 { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 1, .level = BDT_BOTH },
371 { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 1, .level = BDT_BOTH },
372 { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 1, .level = BDT_BOTH },
373 { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 1, .level = BDT_BOTH },
374 { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 },
375 { .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 },
376 { .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 },
377 { .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 },
378 { .type = AMD_BIOS_INVALID },
379};
380
Marshall Dawson239286c2019-02-23 16:42:46 -0700381typedef struct _embedded_firmware {
382 uint32_t signature; /* 0x55aa55aa */
383 uint32_t imc_entry;
384 uint32_t gec_entry;
385 uint32_t xhci_entry;
386 uint32_t psp_entry;
387 uint32_t comboable;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600388 uint32_t bios0_entry; /* todo: add way to select correct entry */
389 uint32_t bios1_entry;
Marshall Dawson94f24922019-09-28 08:49:09 -0600390 uint32_t bios2_entry;
391 uint32_t reserved[0x2c]; /* 0x24 - 0x4f */
Marshall Dawson239286c2019-02-23 16:42:46 -0700392} __attribute__((packed, aligned(16))) embedded_firmware;
393
394typedef struct _psp_directory_header {
395 uint32_t cookie;
396 uint32_t checksum;
397 uint32_t num_entries;
398 uint32_t reserved;
399} __attribute__((packed, aligned(16))) psp_directory_header;
400
401typedef struct _psp_directory_entry {
Marshall Dawsondbae6322019-03-04 10:31:03 -0700402 uint8_t type;
403 uint8_t subprog;
404 uint16_t rsvd;
Marshall Dawson239286c2019-02-23 16:42:46 -0700405 uint32_t size;
406 uint64_t addr; /* or a value in some cases */
407} __attribute__((packed)) psp_directory_entry;
408
409typedef struct _psp_directory_table {
410 psp_directory_header header;
411 psp_directory_entry entries[];
412} __attribute__((packed)) psp_directory_table;
413
Marshall Dawson2794a862019-03-04 16:53:15 -0700414#define MAX_PSP_ENTRIES 0x1f
415
Marshall Dawson239286c2019-02-23 16:42:46 -0700416typedef struct _psp_combo_header {
417 uint32_t cookie;
418 uint32_t checksum;
419 uint32_t num_entries;
420 uint32_t lookup;
421 uint64_t reserved[2];
422} __attribute__((packed, aligned(16))) psp_combo_header;
423
424typedef struct _psp_combo_entry {
425 uint32_t id_sel;
426 uint32_t id;
427 uint64_t lvl2_addr;
428} __attribute__((packed)) psp_combo_entry;
429
430typedef struct _psp_combo_directory {
431 psp_combo_header header;
432 psp_combo_entry entries[];
433} __attribute__((packed)) psp_combo_directory;
434
Marshall Dawson2794a862019-03-04 16:53:15 -0700435#define MAX_COMBO_ENTRIES 1
436
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600437typedef struct _bios_directory_hdr {
438 uint32_t cookie;
439 uint32_t checksum;
440 uint32_t num_entries;
441 uint32_t reserved;
442} __attribute__((packed, aligned(16))) bios_directory_hdr;
443
444typedef struct _bios_directory_entry {
445 uint8_t type;
446 uint8_t region_type;
447 int reset:1;
448 int copy:1;
449 int ro:1;
450 int compressed:1;
451 int inst:4;
452 uint8_t subprog; /* b[7:3] reserved */
453 uint32_t size;
454 uint64_t source;
455 uint64_t dest;
456} __attribute__((packed)) bios_directory_entry;
457
458typedef struct _bios_directory_table {
459 bios_directory_hdr header;
460 bios_directory_entry entries[];
461} bios_directory_table;
462
463#define MAX_BIOS_ENTRIES 0x1f
464
Marshall Dawson2794a862019-03-04 16:53:15 -0700465typedef struct _context {
466 char *rom; /* target buffer, size of flash device */
467 uint32_t rom_size; /* size of flash device */
468 uint32_t current; /* pointer within flash & proxy buffer */
469} context;
470
471#define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1)
472#define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset))
473#define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current)
474#define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset)))
475#define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current)
476#define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom))
477#define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current)
478
Marshall Dawson24f73d42019-04-01 10:48:43 -0600479static void *new_psp_dir(context *ctx, int multi)
Marshall Dawson2794a862019-03-04 16:53:15 -0700480{
481 void *ptr;
482
Marshall Dawson24f73d42019-04-01 10:48:43 -0600483 /*
484 * Force both onto boundary when multi. Primary table is after
485 * updatable table, so alignment ensures primary can stay intact
486 * if secondary is reprogrammed.
487 */
488 if (multi)
489 ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT);
490 else
491 ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
492
Marshall Dawson2794a862019-03-04 16:53:15 -0700493 ptr = BUFF_CURRENT(*ctx);
494 ctx->current += sizeof(psp_directory_header)
495 + MAX_PSP_ENTRIES * sizeof(psp_directory_entry);
496 return ptr;
497}
498
Martin Rothec933132019-07-13 20:03:34 -0600499#if PSP_COMBO
Marshall Dawson2794a862019-03-04 16:53:15 -0700500static void *new_combo_dir(context *ctx)
501{
502 void *ptr;
503
504 ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
505 ptr = BUFF_CURRENT(*ctx);
506 ctx->current += sizeof(psp_combo_header)
507 + MAX_COMBO_ENTRIES * sizeof(psp_combo_entry);
508 return ptr;
509}
Martin Rothec933132019-07-13 20:03:34 -0600510#endif
Marshall Dawson2794a862019-03-04 16:53:15 -0700511
Marshall Dawsona378c222019-03-04 16:52:07 -0700512static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800513{
Marshall Dawson24f73d42019-04-01 10:48:43 -0600514 psp_combo_directory *cdir = directory;
515 psp_directory_table *dir = directory;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600516 bios_directory_table *bdir = directory;
Marshall Dawson24f73d42019-04-01 10:48:43 -0600517
518 if (!count)
519 return;
520
521 switch (cookie) {
522 case PSP2_COOKIE:
Marshall Dawsona378c222019-03-04 16:52:07 -0700523 /* caller is responsible for lookup mode */
Marshall Dawsona378c222019-03-04 16:52:07 -0700524 cdir->header.cookie = cookie;
525 cdir->header.num_entries = count;
526 cdir->header.reserved[0] = 0;
527 cdir->header.reserved[1] = 0;
528 /* checksum everything that comes after the Checksum field */
529 cdir->header.checksum = fletcher32(&cdir->header.num_entries,
530 count * sizeof(psp_combo_entry)
531 + sizeof(cdir->header.num_entries)
532 + sizeof(cdir->header.lookup)
533 + 2 * sizeof(cdir->header.reserved[0]));
Marshall Dawson24f73d42019-04-01 10:48:43 -0600534 break;
535 case PSP_COOKIE:
536 case PSPL2_COOKIE:
Marshall Dawsona378c222019-03-04 16:52:07 -0700537 dir->header.cookie = cookie;
538 dir->header.num_entries = count;
539 dir->header.reserved = 0;
540 /* checksum everything that comes after the Checksum field */
541 dir->header.checksum = fletcher32(&dir->header.num_entries,
Marshall Dawson8a45a4d2019-02-24 07:18:44 -0700542 count * sizeof(psp_directory_entry)
Marshall Dawsona378c222019-03-04 16:52:07 -0700543 + sizeof(dir->header.num_entries)
544 + sizeof(dir->header.reserved));
Marshall Dawson24f73d42019-04-01 10:48:43 -0600545 break;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600546 case BDT1_COOKIE:
547 case BDT2_COOKIE:
548 bdir->header.cookie = cookie;
549 bdir->header.num_entries = count;
550 bdir->header.reserved = 0;
551 /* checksum everything that comes after the Checksum field */
552 bdir->header.checksum = fletcher32(&bdir->header.num_entries,
553 count * sizeof(bios_directory_entry)
554 + sizeof(bdir->header.num_entries)
555 + sizeof(bdir->header.reserved));
556 break;
Marshall Dawsona378c222019-03-04 16:52:07 -0700557 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800558}
559
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700560static ssize_t copy_blob(void *dest, const char *src_file, size_t room)
561{
562 int fd;
563 struct stat fd_stat;
564 ssize_t bytes;
565
566 fd = open(src_file, O_RDONLY);
567 if (fd < 0) {
568 printf("Error: %s\n", strerror(errno));
569 return -1;
570 }
571
572 if (fstat(fd, &fd_stat)) {
573 printf("fstat error: %s\n", strerror(errno));
Jacob Garber967f8622019-07-02 10:35:10 -0600574 close(fd);
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700575 return -2;
576 }
577
578 if (fd_stat.st_size > room) {
579 printf("Error: %s will not fit. Exiting.\n", src_file);
Jacob Garber967f8622019-07-02 10:35:10 -0600580 close(fd);
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700581 return -3;
582 }
583
584 bytes = read(fd, dest, (size_t)fd_stat.st_size);
585 close(fd);
586 if (bytes != (ssize_t)fd_stat.st_size) {
587 printf("Error while reading %s\n", src_file);
588 return -4;
589 }
590
591 return bytes;
592}
593
Marshall Dawson2794a862019-03-04 16:53:15 -0700594static void integrate_firmwares(context *ctx,
Marshall Dawson239286c2019-02-23 16:42:46 -0700595 embedded_firmware *romsig,
Marshall Dawson2794a862019-03-04 16:53:15 -0700596 amd_fw_entry *fw_table)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800597{
Richard Spiegel137484d2018-01-17 10:23:19 -0700598 ssize_t bytes;
zbaoc3a08a92016-03-02 14:47:27 +0800599 int i;
Marshall Dawson2794a862019-03-04 16:53:15 -0700600
601 ctx->current += sizeof(embedded_firmware);
602 ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800603
Martin Rothcd15bc82016-11-08 11:34:02 -0700604 for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
zbaoc3a08a92016-03-02 14:47:27 +0800605 if (fw_table[i].filename != NULL) {
zbaoc3a08a92016-03-02 14:47:27 +0800606 switch (fw_table[i].type) {
607 case AMD_FW_IMC:
Marshall Dawson2794a862019-03-04 16:53:15 -0700608 ctx->current = ALIGN(ctx->current, 0x10000U);
609 romsig->imc_entry = RUN_CURRENT(*ctx);
zbaoc3a08a92016-03-02 14:47:27 +0800610 break;
611 case AMD_FW_GEC:
Marshall Dawson2794a862019-03-04 16:53:15 -0700612 romsig->gec_entry = RUN_CURRENT(*ctx);
zbaoc3a08a92016-03-02 14:47:27 +0800613 break;
614 case AMD_FW_XHCI:
Marshall Dawson2794a862019-03-04 16:53:15 -0700615 romsig->xhci_entry = RUN_CURRENT(*ctx);
zbaoc3a08a92016-03-02 14:47:27 +0800616 break;
617 default:
618 /* Error */
619 break;
620 }
621
Marshall Dawson2794a862019-03-04 16:53:15 -0700622 bytes = copy_blob(BUFF_CURRENT(*ctx),
623 fw_table[i].filename, BUFF_ROOM(*ctx));
Marshall Dawson02bd7732019-03-13 14:43:17 -0600624 if (bytes < 0) {
Marshall Dawson2794a862019-03-04 16:53:15 -0700625 free(ctx->rom);
Martin Roth60f15512016-11-08 09:55:01 -0700626 exit(1);
627 }
628
Marshall Dawson2794a862019-03-04 16:53:15 -0700629 ctx->current = ALIGN(ctx->current + bytes,
630 BLOB_ALIGNMENT);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800631 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800632 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800633}
634
Marshall Dawson2794a862019-03-04 16:53:15 -0700635static void integrate_psp_firmwares(context *ctx,
Marshall Dawson239286c2019-02-23 16:42:46 -0700636 psp_directory_table *pspdir,
Marshall Dawson24f73d42019-04-01 10:48:43 -0600637 psp_directory_table *pspdir2,
638 amd_fw_entry *fw_table,
639 uint32_t cookie)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800640{
Richard Spiegel137484d2018-01-17 10:23:19 -0700641 ssize_t bytes;
Marshall Dawsonc38c0c92019-02-23 16:41:35 -0700642 unsigned int i, count;
Marshall Dawson24f73d42019-04-01 10:48:43 -0600643 int level;
644
645 /* This function can create a primary table, a secondary table, or a
646 * flattened table which contains all applicable types. These if-else
647 * statements infer what the caller intended. If a 2nd-level cookie
648 * is passed, clearly a 2nd-level table is intended. However, a
649 * 1st-level cookie may indicate level 1 or flattened. If the caller
650 * passes a pointer to a 2nd-level table, then assume not flat.
651 */
652 if (cookie == PSPL2_COOKIE)
653 level = PSP_LVL2;
654 else if (pspdir2)
655 level = PSP_LVL1;
656 else
657 level = PSP_BOTH;
Marshall Dawson2794a862019-03-04 16:53:15 -0700658
659 ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800660
Marshall Dawsonc38c0c92019-02-23 16:41:35 -0700661 for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
Marshall Dawson24f73d42019-04-01 10:48:43 -0600662 if (!(fw_table[i].level & level))
663 continue;
664
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600665 if (fw_table[i].type == AMD_TOKEN_UNLOCK) {
666 if (!fw_table[i].other)
667 continue;
668 ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT);
669 pspdir->entries[count].type = fw_table[i].type;
670 pspdir->entries[count].size = 4096; /* TODO: doc? */
671 pspdir->entries[count].addr = RUN_CURRENT(*ctx);
672 pspdir->entries[count].subprog = fw_table[i].subprog;
673 pspdir->entries[count].rsvd = 0;
674 ctx->current = ALIGN(ctx->current + 4096, 0x100U);
675 count++;
676 } else if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) {
Marshall Dawson239286c2019-02-23 16:42:46 -0700677 pspdir->entries[count].type = fw_table[i].type;
Marshall Dawsondbae6322019-03-04 10:31:03 -0700678 pspdir->entries[count].subprog = fw_table[i].subprog;
679 pspdir->entries[count].rsvd = 0;
Marshall Dawson239286c2019-02-23 16:42:46 -0700680 pspdir->entries[count].size = 0xFFFFFFFF;
Marshall Dawsonef79fcc2019-04-01 10:16:41 -0600681 pspdir->entries[count].addr = fw_table[i].other;
Marshall Dawsonc38c0c92019-02-23 16:41:35 -0700682 count++;
Marshall Dawson7c1e1422019-04-11 09:44:43 -0600683 } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) {
684 if (fw_table[i].filename == NULL)
685 continue;
686 /* TODO: Add a way to reserve for NVRAM without
687 * requiring a filename. This isn't a feature used
688 * by coreboot systems, so priority is very low.
689 */
690 ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT);
691 bytes = copy_blob(BUFF_CURRENT(*ctx),
692 fw_table[i].filename, BUFF_ROOM(*ctx));
693 if (bytes <= 0) {
694 free(ctx->rom);
695 exit(1);
696 }
697
698 pspdir->entries[count].type = fw_table[i].type;
699 pspdir->entries[count].subprog = fw_table[i].subprog;
700 pspdir->entries[count].rsvd = 0;
701 pspdir->entries[count].size = ALIGN(bytes,
702 ERASE_ALIGNMENT);
703 pspdir->entries[count].addr = RUN_CURRENT(*ctx);
704
705 ctx->current = ALIGN(ctx->current + bytes,
706 BLOB_ERASE_ALIGNMENT);
707 count++;
zbaoc3a08a92016-03-02 14:47:27 +0800708 } else if (fw_table[i].filename != NULL) {
Marshall Dawson2794a862019-03-04 16:53:15 -0700709 bytes = copy_blob(BUFF_CURRENT(*ctx),
710 fw_table[i].filename, BUFF_ROOM(*ctx));
Marshall Dawson02bd7732019-03-13 14:43:17 -0600711 if (bytes < 0) {
Marshall Dawson2794a862019-03-04 16:53:15 -0700712 free(ctx->rom);
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700713 exit(1);
714 }
715
Marshall Dawson239286c2019-02-23 16:42:46 -0700716 pspdir->entries[count].type = fw_table[i].type;
Marshall Dawsondbae6322019-03-04 10:31:03 -0700717 pspdir->entries[count].subprog = fw_table[i].subprog;
718 pspdir->entries[count].rsvd = 0;
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700719 pspdir->entries[count].size = (uint32_t)bytes;
Marshall Dawson2794a862019-03-04 16:53:15 -0700720 pspdir->entries[count].addr = RUN_CURRENT(*ctx);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800721
Marshall Dawson2794a862019-03-04 16:53:15 -0700722 ctx->current = ALIGN(ctx->current + bytes,
723 BLOB_ALIGNMENT);
Marshall Dawsonc38c0c92019-02-23 16:41:35 -0700724 count++;
zbaoc3a08a92016-03-02 14:47:27 +0800725 } else {
726 /* This APU doesn't have this firmware. */
727 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800728 }
Marshall Dawson2794a862019-03-04 16:53:15 -0700729
Marshall Dawson24f73d42019-04-01 10:48:43 -0600730 if (pspdir2) {
731 pspdir->entries[count].type = AMD_FW_L2_PTR;
732 pspdir->entries[count].subprog = 0;
733 pspdir->entries[count].rsvd = 0;
734 pspdir->entries[count].size = sizeof(pspdir2->header)
735 + pspdir2->header.num_entries
736 * sizeof(psp_directory_entry);
737
738 pspdir->entries[count].addr = BUFF_TO_RUN(*ctx, pspdir2);
739 count++;
740 }
741
Marshall Dawson2794a862019-03-04 16:53:15 -0700742 if (count > MAX_PSP_ENTRIES) {
743 printf("Error: PSP entries exceed max allowed items\n");
744 free(ctx->rom);
745 exit(1);
746 }
747
Marshall Dawson24f73d42019-04-01 10:48:43 -0600748 fill_dir_header(pspdir, count, cookie);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800749}
750
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600751static void *new_bios_dir(context *ctx, int multi)
752{
753 void *ptr;
754
755 /*
756 * Force both onto boundary when multi. Primary table is after
757 * updatable table, so alignment ensures primary can stay intact
758 * if secondary is reprogrammed.
759 */
760 if (multi)
761 ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT);
762 else
763 ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
764 ptr = BUFF_CURRENT(*ctx);
765 ctx->current += sizeof(bios_directory_hdr)
766 + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry);
767 return ptr;
768}
769
770static int locate_bdt2_bios(bios_directory_table *level2,
771 uint64_t *source, uint32_t *size)
772{
773 int i;
774
775 *source = 0;
776 *size = 0;
777 if (!level2)
778 return 0;
779
780 for (i = 0 ; i < level2->header.num_entries ; i++) {
781 if (level2->entries[i].type == AMD_BIOS_BIN) {
782 *source = level2->entries[i].source;
783 *size = level2->entries[i].size;
784 return 1;
785 }
786 }
787 return 0;
788}
789
790static int have_bios_tables(amd_bios_entry *table)
791{
792 int i;
793
794 for (i = 0 ; table[i].type != AMD_BIOS_INVALID; i++) {
795 if (table[i].level & BDT_LVL1 && table[i].filename)
796 return 1;
797 }
798 return 0;
799}
800
801static void integrate_bios_firmwares(context *ctx,
802 bios_directory_table *biosdir,
803 bios_directory_table *biosdir2,
804 amd_bios_entry *fw_table,
805 uint32_t cookie)
806{
807 ssize_t bytes;
Martin Rothec933132019-07-13 20:03:34 -0600808 unsigned int i, count;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600809 int level;
810
811 /* This function can create a primary table, a secondary table, or a
812 * flattened table which contains all applicable types. These if-else
813 * statements infer what the caller intended. If a 2nd-level cookie
814 * is passed, clearly a 2nd-level table is intended. However, a
815 * 1st-level cookie may indicate level 1 or flattened. If the caller
816 * passes a pointer to a 2nd-level table, then assume not flat.
817 */
818 if (cookie == BDT2_COOKIE)
819 level = BDT_LVL2;
820 else if (biosdir2)
821 level = BDT_LVL1;
822 else
823 level = BDT_BOTH;
824
825 ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT);
826
827 for (i = 0, count = 0; fw_table[i].type != AMD_BIOS_INVALID; i++) {
828 if (!(fw_table[i].level & level))
829 continue;
830 if (fw_table[i].filename == NULL && (
831 fw_table[i].type != AMD_BIOS_APOB &&
832 fw_table[i].type != AMD_BIOS_APOB_NV &&
833 fw_table[i].type != AMD_BIOS_L2_PTR &&
834 fw_table[i].type != AMD_BIOS_BIN))
835 continue;
836 /* APOB_NV needs a size, else no S3 and skip item */
837 if (fw_table[i].type == AMD_BIOS_APOB_NV && !fw_table[i].size)
838 continue;
839
840 /* BIOS Directory items may have additional requirements */
841
842 /* APOB_NV must have a size if it has a source */
843 if (fw_table[i].type == AMD_BIOS_APOB_NV && fw_table[i].src) {
844 if (!fw_table[i].size) {
845 printf("Error: APOB NV address provided, but no size\n");
846 free(ctx->rom);
847 exit(1);
848 }
849 }
850
851 /* APOB_DATA needs destination */
852 if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) {
853 printf("Error: APOB destination not provided\n");
854 free(ctx->rom);
855 exit(1);
856 }
857
858 /* BIOS binary must have destination and uncompressed size. If
859 * no filename given, then user must provide a source address.
860 */
861 if (fw_table[i].type == AMD_BIOS_BIN) {
862 if (!fw_table[i].dest || !fw_table[i].size) {
863 printf("Error: BIOS binary destination and uncompressed size are required\n");
864 free(ctx->rom);
865 exit(1);
866 }
867 if (!fw_table[i].filename && !fw_table[i].src) {
868 printf("Error: BIOS binary assumed outside amdfw.rom but no source address given\n");
869 free(ctx->rom);
870 exit(1);
871 }
872 }
873
874 biosdir->entries[count].type = fw_table[i].type;
875 biosdir->entries[count].region_type = fw_table[i].region_type;
876 biosdir->entries[count].dest = fw_table[i].dest ?
877 fw_table[i].dest : (uint64_t)-1;
878 biosdir->entries[count].reset = fw_table[i].reset;
879 biosdir->entries[count].copy = fw_table[i].copy;
880 biosdir->entries[count].ro = fw_table[i].ro;
881 biosdir->entries[count].compressed = fw_table[i].zlib;
882 biosdir->entries[count].inst = fw_table[i].inst;
883 biosdir->entries[count].subprog = fw_table[i].subpr;
884
885 switch (fw_table[i].type) {
886 case AMD_BIOS_APOB:
887 biosdir->entries[count].size = fw_table[i].size;
888 biosdir->entries[count].source = fw_table[i].src;
889 break;
890 case AMD_BIOS_APOB_NV:
891 if (fw_table[i].src) {
892 /* If source is given, use that and its size */
893 biosdir->entries[count].source = fw_table[i].src;
894 biosdir->entries[count].size = fw_table[i].size;
895 } else {
896 /* Else reserve size bytes within amdfw.rom */
897 ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT);
898 biosdir->entries[count].source = RUN_CURRENT(*ctx);
899 biosdir->entries[count].size = ALIGN(
900 fw_table[i].size, ERASE_ALIGNMENT);
901 memset(BUFF_CURRENT(*ctx), 0xff,
902 biosdir->entries[count].size);
903 ctx->current = ctx->current
904 + biosdir->entries[count].size;
905 }
906 break;
907 case AMD_BIOS_BIN:
908 /* Don't make a 2nd copy, point to the same one */
909 if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2,
910 &biosdir->entries[count].source,
911 &biosdir->entries[count].size))
912 break;
913
914 /* level 2, or level 1 and no copy found in level 2 */
915 biosdir->entries[count].source = fw_table[i].src;
916 biosdir->entries[count].dest = fw_table[i].dest;
917 biosdir->entries[count].size = fw_table[i].size;
918
919 if (!fw_table[i].filename)
920 break;
921
922 bytes = copy_blob(BUFF_CURRENT(*ctx),
923 fw_table[i].filename, BUFF_ROOM(*ctx));
924 if (bytes <= 0) {
925 free(ctx->rom);
926 exit(1);
927 }
928
929 biosdir->entries[count].source = RUN_CURRENT(*ctx);
930
931 ctx->current = ALIGN(ctx->current + bytes, 0x100U);
932 break;
933 default: /* everything else is copied from input */
934 if (fw_table[i].type == AMD_BIOS_APCB ||
935 fw_table[i].type == AMD_BIOS_APCB_BK)
936 ctx->current = ALIGN(
937 ctx->current, ERASE_ALIGNMENT);
938
939 bytes = copy_blob(BUFF_CURRENT(*ctx),
940 fw_table[i].filename, BUFF_ROOM(*ctx));
941 if (bytes <= 0) {
942 free(ctx->rom);
943 exit(1);
944 }
945
946 biosdir->entries[count].size = (uint32_t)bytes;
947 biosdir->entries[count].source = RUN_CURRENT(*ctx);
948
949 ctx->current = ALIGN(ctx->current + bytes, 0x100U);
950 break;
951 }
952
953 count++;
954 }
955
956 if (biosdir2) {
957 biosdir->entries[count].type = AMD_BIOS_L2_PTR;
958 biosdir->entries[count].size =
959 + MAX_BIOS_ENTRIES
960 * sizeof(bios_directory_entry);
961 biosdir->entries[count].source =
962 BUFF_TO_RUN(*ctx, biosdir2);
963 biosdir->entries[count].subprog = 0;
964 biosdir->entries[count].inst = 0;
965 biosdir->entries[count].copy = 0;
966 biosdir->entries[count].compressed = 0;
967 biosdir->entries[count].dest = -1;
968 biosdir->entries[count].reset = 0;
969 biosdir->entries[count].ro = 0;
970 count++;
971 }
972
973 if (count > MAX_BIOS_ENTRIES) {
974 printf("Error: BIOS entries exceeds max allowed items\n");
975 free(ctx->rom);
976 exit(1);
977 }
978
979 fill_dir_header(biosdir, count, cookie);
980}
Martin Rothd3ce8c82019-07-13 20:13:07 -0600981// Unused values: CDEPqR
982static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:";
Marc Jones90099b62016-09-20 21:05:45 -0600983
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800984static struct option long_options[] = {
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600985 {"xhci", required_argument, 0, 'x' },
986 {"imc", required_argument, 0, 'i' },
987 {"gec", required_argument, 0, 'g' },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600988 /* PSP Directory Table items */
Marshall Dawson67d868d2019-02-28 11:43:40 -0700989 {"combo-capable", no_argument, 0, 'A' },
Marshall Dawson24f73d42019-04-01 10:48:43 -0600990 {"multilevel", no_argument, 0, 'M' },
Marshall Dawsondbae6322019-03-04 10:31:03 -0700991 {"subprogram", required_argument, 0, 'S' },
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600992 {"pubkey", required_argument, 0, 'p' },
993 {"bootloader", required_argument, 0, 'b' },
994 {"smufirmware", required_argument, 0, 's' },
995 {"recovery", required_argument, 0, 'r' },
996 {"rtmpubkey", required_argument, 0, 'k' },
997 {"secureos", required_argument, 0, 'c' },
998 {"nvram", required_argument, 0, 'n' },
999 {"securedebug", required_argument, 0, 'd' },
1000 {"trustlets", required_argument, 0, 't' },
1001 {"trustletkey", required_argument, 0, 'u' },
1002 {"smufirmware2", required_argument, 0, 'w' },
1003 {"smuscs", required_argument, 0, 'm' },
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001004 {"soft-fuse", required_argument, 0, 'T' },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001005 {"abl-image", required_argument, 0, 'z' },
1006 {"sec-gasket", required_argument, 0, 'J' },
1007 {"mp2-fw", required_argument, 0, 'B' },
1008 {"drv-entry-pts", required_argument, 0, 'K' },
1009 {"ikek", required_argument, 0, 'L' },
1010 {"s0i3drv", required_argument, 0, 'Y' },
1011 {"secdebug", required_argument, 0, 'N' },
1012 {"token-unlock", no_argument, 0, 'U' },
1013 {"whitelist", required_argument, 0, 'W' },
Martin Rothd3ce8c82019-07-13 20:13:07 -06001014 {"verstage", required_argument, 0, 'Z' },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001015 /* BIOS Directory Table items */
1016 {"instance", required_argument, 0, 'I' },
1017 {"apcb", required_argument, 0, 'a' },
1018 {"apob-base", required_argument, 0, 'Q' },
1019 {"bios-bin", required_argument, 0, 'V' },
1020 {"bios-bin-src", required_argument, 0, 'e' },
1021 {"bios-bin-dest", required_argument, 0, 'v' },
1022 {"bios-uncomp-size", required_argument, 0, 'j' },
1023 {"pmu-inst", required_argument, 0, 'y' },
1024 {"pmu-data", required_argument, 0, 'G' },
1025 {"ucode", required_argument, 0, 'O' },
1026 {"mp2-config", required_argument, 0, 'X' },
1027 {"apob-nv-base", required_argument, 0, 'F' },
1028 {"apob-nv-size", required_argument, 0, 'H' },
1029 /* other */
Marshall Dawsonf4b9b412017-03-17 16:30:51 -06001030 {"output", required_argument, 0, 'o' },
1031 {"flashsize", required_argument, 0, 'f' },
Martin Roth0d3b1182017-10-03 14:16:04 -06001032 {"location", required_argument, 0, 'l' },
Marshall Dawsonf4b9b412017-03-17 16:30:51 -06001033 {"help", no_argument, 0, 'h' },
Marshall Dawsonf4b9b412017-03-17 16:30:51 -06001034 {NULL, 0, 0, 0 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001035};
1036
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001037static void register_fw_fuse(char *str)
1038{
1039 int i;
1040
1041 for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
1042 if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN)
1043 continue;
1044
1045 amd_psp_fw_table[i].other = strtoull(str, NULL, 16);
1046 return;
1047 }
1048}
1049
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001050static void register_fw_token_unlock(void)
1051{
1052 int i;
1053
1054 for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
1055 if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK)
1056 continue;
1057
1058 amd_psp_fw_table[i].other = 1;
1059 return;
1060 }
1061}
1062
Marshall Dawsondbae6322019-03-04 10:31:03 -07001063static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[])
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001064{
Martin Roth8806f7f2016-11-08 10:44:18 -07001065 unsigned int i;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001066
Martin Rothcd15bc82016-11-08 11:34:02 -07001067 for (i = 0; i < sizeof(amd_fw_table) / sizeof(amd_fw_entry); i++) {
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001068 if (amd_fw_table[i].type == type) {
1069 amd_fw_table[i].filename = filename;
1070 return;
1071 }
1072 }
1073
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001074 for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
Marshall Dawsondbae6322019-03-04 10:31:03 -07001075 if (amd_psp_fw_table[i].type != type)
1076 continue;
1077
1078 if (amd_psp_fw_table[i].subprog == sub) {
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001079 amd_psp_fw_table[i].filename = filename;
1080 return;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001081 }
1082 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001083}
1084
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001085static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[])
1086{
1087 int i;
1088
1089 for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) {
1090 if (amd_bios_table[i].type == type
1091 && amd_bios_table[i].inst == ins
1092 && amd_bios_table[i].subpr == sub) {
1093 amd_bios_table[i].filename = name;
1094 return;
1095 }
1096 }
1097}
1098
Martin Rothec933132019-07-13 20:03:34 -06001099static void register_fw_addr(amd_bios_type type, char *src_str,
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001100 char *dst_str, char *size_str)
1101{
1102 int i;
1103 for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) {
1104 if (amd_bios_table[i].type != type)
1105 continue;
1106
1107 if (src_str)
1108 amd_bios_table[i].src = strtoull(src_str, NULL, 16);
1109 if (dst_str)
1110 amd_bios_table[i].dest = strtoull(dst_str, NULL, 16);
1111 if (size_str)
1112 amd_bios_table[i].size = strtoul(size_str, NULL, 16);
1113
1114 return;
1115 }
1116}
1117
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001118int main(int argc, char **argv)
1119{
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001120 int c;
Martin Roth31d95a22016-11-08 11:22:12 -07001121 int retval = 0;
Martin Roth60f15512016-11-08 09:55:01 -07001122 char *tmp;
Martin Roth8806f7f2016-11-08 10:44:18 -07001123 char *rom = NULL;
Marshall Dawson239286c2019-02-23 16:42:46 -07001124 embedded_firmware *amd_romsig;
1125 psp_directory_table *pspdir;
Marshall Dawson67d868d2019-02-28 11:43:40 -07001126 int comboable = 0;
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001127 int fuse_defined = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001128 int targetfd;
Martin Roth8806f7f2016-11-08 10:44:18 -07001129 char *output = NULL;
Marshall Dawson2794a862019-03-04 16:53:15 -07001130 context ctx = {
1131 .rom_size = CONFIG_ROM_SIZE,
1132 };
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001133 /* Values cleared after each firmware or parameter, regardless if N/A */
1134 uint8_t sub = 0, instance = 0;
1135 int abl_image = 0;
Martin Roth0d3b1182017-10-03 14:16:04 -06001136 uint32_t dir_location = 0;
1137 uint32_t romsig_offset;
Martin Roth60f15512016-11-08 09:55:01 -07001138 uint32_t rom_base_address;
Marshall Dawson24f73d42019-04-01 10:48:43 -06001139 int multi = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001140
1141 while (1) {
1142 int optindex = 0;
1143
1144 c = getopt_long(argc, argv, optstring, long_options, &optindex);
1145
1146 if (c == -1)
1147 break;
1148
1149 switch (c) {
1150 case 'x':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001151 register_fw_filename(AMD_FW_XHCI, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001152 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001153 break;
1154 case 'i':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001155 register_fw_filename(AMD_FW_IMC, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001156 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001157 break;
1158 case 'g':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001159 register_fw_filename(AMD_FW_GEC, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001160 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001161 break;
Marshall Dawson67d868d2019-02-28 11:43:40 -07001162 case 'A':
1163 comboable = 1;
1164 break;
Marshall Dawson24f73d42019-04-01 10:48:43 -06001165 case 'M':
1166 multi = 1;
1167 break;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001168 case 'U':
1169 register_fw_token_unlock();
1170 sub = instance = 0;
1171 break;
Marshall Dawsondbae6322019-03-04 10:31:03 -07001172 case 'S':
1173 sub = (uint8_t)strtoul(optarg, &tmp, 16);
1174 break;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001175 case 'I':
1176 instance = strtoul(optarg, &tmp, 16);
1177 break;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001178 case 'p':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001179 register_fw_filename(AMD_FW_PSP_PUBKEY, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001180 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001181 break;
1182 case 'b':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001183 register_fw_filename(AMD_FW_PSP_BOOTLOADER,
1184 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001185 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001186 break;
1187 case 's':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001188 register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE,
1189 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001190 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001191 break;
1192 case 'r':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001193 register_fw_filename(AMD_FW_PSP_RECOVERY, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001194 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001195 break;
1196 case 'k':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001197 register_fw_filename(AMD_FW_PSP_RTM_PUBKEY,
1198 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001199 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001200 break;
1201 case 'c':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001202 register_fw_filename(AMD_FW_PSP_SECURED_OS,
1203 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001204 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001205 break;
1206 case 'n':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001207 register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001208 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001209 break;
1210 case 'd':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001211 register_fw_filename(AMD_FW_PSP_SECURED_DEBUG,
1212 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001213 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001214 break;
1215 case 't':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001216 register_fw_filename(AMD_FW_PSP_TRUSTLETS, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001217 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001218 break;
1219 case 'u':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001220 register_fw_filename(AMD_FW_PSP_TRUSTLETKEY,
1221 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001222 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001223 break;
1224 case 'w':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001225 register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE2,
1226 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001227 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001228 break;
1229 case 'm':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001230 register_fw_filename(AMD_FW_PSP_SMUSCS, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001231 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001232 break;
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001233 case 'T':
1234 register_fw_fuse(optarg);
1235 fuse_defined = 1;
1236 sub = 0;
1237 break;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001238 case 'a':
1239 register_bdt_data(AMD_BIOS_APCB, sub, instance, optarg);
1240 register_bdt_data(AMD_BIOS_APCB_BK, sub,
1241 instance, optarg);
1242 sub = instance = 0;
1243 break;
1244 case 'Q':
1245 /* APOB destination */
1246 register_fw_addr(AMD_BIOS_APOB, 0, optarg, 0);
1247 sub = instance = 0;
1248 break;
1249 case 'F':
1250 /* APOB NV source */
1251 register_fw_addr(AMD_BIOS_APOB_NV, optarg, 0, 0);
1252 sub = instance = 0;
1253 break;
1254 case 'H':
1255 /* APOB NV size */
1256 register_fw_addr(AMD_BIOS_APOB_NV, 0, 0, optarg);
1257 sub = instance = 0;
1258 break;
1259 case 'V':
1260 register_bdt_data(AMD_BIOS_BIN, sub, instance, optarg);
1261 sub = instance = 0;
1262 break;
1263 case 'e':
1264 /* BIOS source */
1265 register_fw_addr(AMD_BIOS_BIN, optarg, 0, 0);
1266 sub = instance = 0;
1267 break;
1268 case 'v':
1269 /* BIOS destination */
1270 register_fw_addr(AMD_BIOS_BIN, 0, optarg, 0);
1271 sub = instance = 0;
1272 break;
1273 case 'j':
1274 /* BIOS destination size */
1275 register_fw_addr(AMD_BIOS_BIN, 0, 0, optarg);
1276 sub = instance = 0;
1277 break;
1278 case 'y':
1279 register_bdt_data(AMD_BIOS_PMUI, sub, instance, optarg);
1280 sub = instance = 0;
1281 break;
1282 case 'G':
1283 register_bdt_data(AMD_BIOS_PMUD, sub, instance, optarg);
1284 sub = instance = 0;
1285 break;
1286 case 'O':
1287 register_bdt_data(AMD_BIOS_UCODE, sub,
1288 instance, optarg);
1289 sub = instance = 0;
1290 break;
1291 case 'J':
1292 register_fw_filename(AMD_SEC_GASKET, sub, optarg);
1293 sub = instance = 0;
1294 break;
1295 case 'B':
1296 register_fw_filename(AMD_MP2_FW, sub, optarg);
1297 sub = instance = 0;
1298 break;
1299 case 'z':
1300 register_fw_filename(AMD_ABL0 + abl_image++,
1301 sub, optarg);
1302 sub = instance = 0;
1303 break;
1304 case 'X':
1305 register_bdt_data(AMD_BIOS_MP2_CFG, sub,
1306 instance, optarg);
1307 sub = instance = 0;
1308 break;
1309 case 'K':
1310 register_fw_filename(AMD_DRIVER_ENTRIES, sub, optarg);
1311 sub = instance = 0;
1312 break;
1313 case 'L':
1314 register_fw_filename(AMD_WRAPPED_IKEK, sub, optarg);
1315 sub = instance = 0;
1316 break;
1317 case 'Y':
1318 register_fw_filename(AMD_S0I3_DRIVER, sub, optarg);
1319 sub = instance = 0;
1320 break;
1321 case 'N':
1322 register_fw_filename(AMD_DEBUG_UNLOCK, sub, optarg);
1323 sub = instance = 0;
1324 break;
1325 case 'W':
1326 register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg);
1327 sub = instance = 0;
1328 break;
Martin Rothd3ce8c82019-07-13 20:13:07 -06001329 case 'Z':
1330 register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg);
1331 sub = instance = 0;
1332 break;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001333 case 'o':
1334 output = optarg;
1335 break;
Martin Roth60f15512016-11-08 09:55:01 -07001336 case 'f':
Marshall Dawson2794a862019-03-04 16:53:15 -07001337 ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16);
Martin Roth60f15512016-11-08 09:55:01 -07001338 if (*tmp != '\0') {
1339 printf("Error: ROM size specified"
1340 " incorrectly (%s)\n\n", optarg);
Martin Roth31d95a22016-11-08 11:22:12 -07001341 retval = 1;
Martin Roth60f15512016-11-08 09:55:01 -07001342 }
1343 break;
Martin Roth0d3b1182017-10-03 14:16:04 -06001344 case 'l':
1345 dir_location = (uint32_t)strtoul(optarg, &tmp, 16);
1346 if (*tmp != '\0') {
1347 printf("Error: Directory Location specified"
1348 " incorrectly (%s)\n\n", optarg);
1349 retval = 1;
1350 }
1351 break;
1352
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001353 case 'h':
1354 usage();
Martin Roth31d95a22016-11-08 11:22:12 -07001355 return 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001356 default:
1357 break;
1358 }
1359 }
1360
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001361 if (!fuse_defined)
1362 register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN);
1363
Martin Roth8806f7f2016-11-08 10:44:18 -07001364 if (!output) {
Martin Roth31d95a22016-11-08 11:22:12 -07001365 printf("Error: Output value is not specified.\n\n");
1366 retval = 1;
1367 }
1368
Marshall Dawson2794a862019-03-04 16:53:15 -07001369 if (ctx.rom_size % 1024 != 0) {
Martin Roth60f15512016-11-08 09:55:01 -07001370 printf("Error: ROM Size (%d bytes) should be a multiple of"
Marshall Dawson2794a862019-03-04 16:53:15 -07001371 " 1024 bytes.\n\n", ctx.rom_size);
Martin Roth31d95a22016-11-08 11:22:12 -07001372 retval = 1;
Martin Roth60f15512016-11-08 09:55:01 -07001373 }
1374
Marshall Dawson2794a862019-03-04 16:53:15 -07001375 if (ctx.rom_size < MIN_ROM_KB * 1024) {
Martin Roth31d95a22016-11-08 11:22:12 -07001376 printf("Error: ROM Size (%dKB) must be at least %dKB.\n\n",
Marshall Dawson2794a862019-03-04 16:53:15 -07001377 ctx.rom_size / 1024, MIN_ROM_KB);
Martin Roth31d95a22016-11-08 11:22:12 -07001378 retval = 1;
1379 }
1380
1381 if (retval) {
1382 usage();
1383 return retval;
Martin Roth60f15512016-11-08 09:55:01 -07001384 }
1385
Marshall Dawson2794a862019-03-04 16:53:15 -07001386 printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024);
Martin Roth60f15512016-11-08 09:55:01 -07001387
Marshall Dawson2794a862019-03-04 16:53:15 -07001388 rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1;
Martin Roth0d3b1182017-10-03 14:16:04 -06001389 if (dir_location && (dir_location < rom_base_address)) {
1390 printf("Error: Directory location outside of ROM.\n\n");
1391 return 1;
1392 }
1393
1394 switch (dir_location) {
1395 case 0: /* Fall through */
1396 case 0xFFFA0000: /* Fall through */
1397 case 0xFFF20000: /* Fall through */
1398 case 0xFFE20000: /* Fall through */
1399 case 0xFFC20000: /* Fall through */
1400 case 0xFF820000: /* Fall through */
1401 case 0xFF020000: /* Fall through */
1402 break;
1403 default:
1404 printf("Error: Invalid Directory location.\n");
1405 printf(" Valid locations are 0xFFFA0000, 0xFFF20000,\n");
1406 printf(" 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n");
1407 return 1;
1408 }
1409
Marshall Dawson2794a862019-03-04 16:53:15 -07001410 ctx.rom = malloc(ctx.rom_size);
1411 if (!ctx.rom) {
1412 printf("Error: Failed to allocate memory\n");
Martin Roth31d95a22016-11-08 11:22:12 -07001413 return 1;
Marshall Dawson2794a862019-03-04 16:53:15 -07001414 }
1415 memset(ctx.rom, 0xFF, ctx.rom_size);
Martin Roth60f15512016-11-08 09:55:01 -07001416
Martin Roth0d3b1182017-10-03 14:16:04 -06001417 if (dir_location)
Marshall Dawson2794a862019-03-04 16:53:15 -07001418 romsig_offset = ctx.current = dir_location - rom_base_address;
Martin Roth0d3b1182017-10-03 14:16:04 -06001419 else
Marshall Dawson2794a862019-03-04 16:53:15 -07001420 romsig_offset = ctx.current = AMD_ROMSIG_OFFSET;
1421 printf(" AMDFWTOOL Using firmware directory location of 0x%08x\n",
1422 RUN_CURRENT(ctx));
Martin Roth0d3b1182017-10-03 14:16:04 -06001423
Marshall Dawson2794a862019-03-04 16:53:15 -07001424 amd_romsig = BUFF_OFFSET(ctx, romsig_offset);
Marshall Dawson239286c2019-02-23 16:42:46 -07001425 amd_romsig->signature = EMBEDDED_FW_SIGNATURE;
1426 amd_romsig->imc_entry = 0;
1427 amd_romsig->gec_entry = 0;
1428 amd_romsig->xhci_entry = 0;
Martin Roth60f15512016-11-08 09:55:01 -07001429
Marshall Dawson2794a862019-03-04 16:53:15 -07001430 integrate_firmwares(&ctx, amd_romsig, amd_fw_table);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001431
Marshall Dawson2794a862019-03-04 16:53:15 -07001432 ctx.current = ALIGN(ctx.current, 0x10000U); /* todo: is necessary? */
1433
Marshall Dawson24f73d42019-04-01 10:48:43 -06001434 if (multi) {
1435 /* Do 2nd PSP directory followed by 1st */
1436 psp_directory_table *pspdir2 = new_psp_dir(&ctx, multi);
1437 integrate_psp_firmwares(&ctx, pspdir2, 0,
1438 amd_psp_fw_table, PSPL2_COOKIE);
1439
1440 pspdir = new_psp_dir(&ctx, multi);
1441 integrate_psp_firmwares(&ctx, pspdir, pspdir2,
1442 amd_psp_fw_table, PSP_COOKIE);
1443 } else {
1444 /* flat: PSP 1 cookie and no pointer to 2nd table */
1445 pspdir = new_psp_dir(&ctx, multi);
1446 integrate_psp_firmwares(&ctx, pspdir, 0,
1447 amd_psp_fw_table, PSP_COOKIE);
1448 }
Marshall Dawson2794a862019-03-04 16:53:15 -07001449
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001450 if (comboable)
Marshall Dawson2794a862019-03-04 16:53:15 -07001451 amd_romsig->comboable = BUFF_TO_RUN(ctx, pspdir);
Marshall Dawson67d868d2019-02-28 11:43:40 -07001452 else
Marshall Dawson2794a862019-03-04 16:53:15 -07001453 amd_romsig->psp_entry = BUFF_TO_RUN(ctx, pspdir);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001454
zbaoc3a08a92016-03-02 14:47:27 +08001455#if PSP_COMBO
Marshall Dawson2794a862019-03-04 16:53:15 -07001456 psp_combo_directory *combo_dir = new_combo_dir(&ctx);
1457 amd_romsig->comboable = BUFF_TO_RUN(ctx, combo_dir);
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001458 /* 0 -Compare PSP ID, 1 -Compare chip family ID */
1459 combo_dir->entries[0].id_sel = 0;
1460 /* TODO: PSP ID. Documentation is needed. */
1461 combo_dir->entries[0].id = 0x10220B00;
Marshall Dawson2794a862019-03-04 16:53:15 -07001462 combo_dir->entries[0].lvl2_addr = BUFF_TO_RUN(ctx, pspdir);
Zheng Bao4fcc9f22015-11-20 12:29:04 +08001463
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001464 combo_dir->header.lookup = 1;
Marshall Dawsona378c222019-03-04 16:52:07 -07001465 fill_dir_header(combo_dir, 1, PSP2_COOKIE);
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001466#endif
Zheng Bao4fcc9f22015-11-20 12:29:04 +08001467
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001468 if (have_bios_tables(amd_bios_table)) {
1469 bios_directory_table *biosdir;
1470 if (multi) {
1471 /* Do 2nd level BIOS directory followed by 1st */
1472 bios_directory_table *biosdir2 =
1473 new_bios_dir(&ctx, multi);
1474 integrate_bios_firmwares(&ctx, biosdir2, 0,
1475 amd_bios_table, BDT2_COOKIE);
1476
1477 biosdir = new_bios_dir(&ctx, multi);
1478 integrate_bios_firmwares(&ctx, biosdir, biosdir2,
1479 amd_bios_table, BDT1_COOKIE);
1480 } else {
1481 /* flat: BDT1 cookie and no pointer to 2nd table */
1482 biosdir = new_bios_dir(&ctx, multi);
1483 integrate_bios_firmwares(&ctx, biosdir, 0,
1484 amd_bios_table, BDT1_COOKIE);
1485 }
1486 amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir);
1487 }
1488
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001489 targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666);
Martin Roth31d95a22016-11-08 11:22:12 -07001490 if (targetfd >= 0) {
Marshall Dawson2794a862019-03-04 16:53:15 -07001491 write(targetfd, amd_romsig, ctx.current - romsig_offset);
Martin Roth31d95a22016-11-08 11:22:12 -07001492 close(targetfd);
1493 } else {
1494 printf("Error: could not open file: %s\n", output);
1495 retval = 1;
1496 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001497
Martin Roth31d95a22016-11-08 11:22:12 -07001498 free(rom);
1499 return retval;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001500}