Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <string.h> |
| 22 | #include <arch/hlt.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <arch/romcc_io.h> |
| 25 | #include <cbmem.h> |
| 26 | #include <arch/cbfs.h> |
| 27 | #include <cbfs.h> |
| 28 | #include <ip_checksum.h> |
| 29 | #include <pc80/mc146818rtc.h> |
Duncan Laurie | 7b508dd | 2012-04-09 12:30:43 -0700 | [diff] [blame] | 30 | #include <device/pci_def.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 31 | #include "raminit.h" |
| 32 | #include "pei_data.h" |
| 33 | #include "sandybridge.h" |
| 34 | |
| 35 | /* Management Engine is in the southbridge */ |
| 36 | #include "southbridge/intel/bd82x6x/me.h" |
| 37 | #if CONFIG_CHROMEOS |
| 38 | #include <vendorcode/google/chromeos/chromeos.h> |
| 39 | #endif |
| 40 | #if 0 |
| 41 | #include <fdt/libfdt.h> |
| 42 | #endif |
| 43 | |
| 44 | /* |
| 45 | * MRC scrambler seed offsets should be reserved in |
| 46 | * mainboard cmos.layout and not covered by checksum. |
| 47 | */ |
| 48 | #if CONFIG_USE_OPTION_TABLE |
| 49 | #include "option_table.h" |
| 50 | #define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) |
| 51 | #define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) |
| 52 | #define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3) |
| 53 | #else |
| 54 | #define CMOS_OFFSET_MRC_SEED 112 |
| 55 | #define CMOS_OFFSET_MRC_SEED_S3 116 |
| 56 | #define CMOS_OFFSET_MRC_SEED_CHK 120 |
| 57 | #endif |
| 58 | |
| 59 | #define MRC_DATA_ALIGN 0x1000 |
| 60 | #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) |
| 61 | |
| 62 | struct mrc_data_container { |
| 63 | u32 mrc_signature; // "MRCD" |
| 64 | u32 mrc_data_size; // Actual total size of this structure |
| 65 | u32 mrc_checksum; // IP style checksum |
| 66 | u32 reserved; // For header alignment |
| 67 | u8 mrc_data[0]; // Variable size, platform/run time dependent. |
| 68 | } __attribute__ ((packed)); |
| 69 | |
| 70 | static void save_mrc_data(struct pei_data *pei_data) |
| 71 | { |
| 72 | u16 c1, c2, checksum; |
| 73 | |
| 74 | #if CONFIG_EARLY_CBMEM_INIT |
| 75 | struct mrc_data_container *mrcdata; |
| 76 | int output_len = ALIGN(pei_data->mrc_output_len, 16); |
| 77 | |
| 78 | /* Save the MRC S3 restore data to cbmem */ |
| 79 | cbmem_initialize(); |
| 80 | mrcdata = cbmem_add |
| 81 | (CBMEM_ID_MRCDATA, |
| 82 | output_len + sizeof(struct mrc_data_container)); |
| 83 | |
| 84 | printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", |
| 85 | pei_data->mrc_output, mrcdata, output_len); |
| 86 | |
| 87 | mrcdata->mrc_signature = MRC_DATA_SIGNATURE; |
| 88 | mrcdata->mrc_data_size = output_len; |
| 89 | mrcdata->reserved = 0; |
| 90 | memcpy(mrcdata->mrc_data, pei_data->mrc_output, |
| 91 | pei_data->mrc_output_len); |
| 92 | |
| 93 | /* Zero the unused space in aligned buffer. */ |
| 94 | if (output_len > pei_data->mrc_output_len) |
| 95 | memset(mrcdata->mrc_data+pei_data->mrc_output_len, 0, |
| 96 | output_len - pei_data->mrc_output_len); |
| 97 | |
| 98 | mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, |
| 99 | mrcdata->mrc_data_size); |
| 100 | #endif |
| 101 | |
| 102 | /* Save the MRC seed values to CMOS */ |
| 103 | cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); |
| 104 | printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n", |
| 105 | pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
| 106 | |
| 107 | cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); |
| 108 | printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", |
| 109 | pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
| 110 | |
| 111 | /* Save a simple checksum of the seed values */ |
| 112 | c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, |
| 113 | sizeof(u32)); |
| 114 | c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, |
| 115 | sizeof(u32)); |
| 116 | checksum = add_ip_checksums(sizeof(u32), c1, c2); |
| 117 | |
| 118 | cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK); |
| 119 | cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1); |
| 120 | } |
| 121 | |
| 122 | #if CONFIG_CHROMEOS |
| 123 | static void prepare_mrc_cache(struct pei_data *pei_data) |
| 124 | { |
Stefan Reinauer | 6ea86b1 | 2012-04-27 22:54:10 +0200 | [diff] [blame] | 125 | #if 0 |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 126 | const struct fdt_header *fdt_header; |
| 127 | const struct fdt_property *fdtp; |
| 128 | int offset, len; |
| 129 | const char *compatible = "chromeos,flashmap"; |
| 130 | const char *subnode = "rw-mrc-cache"; |
| 131 | const char *property = "reg"; |
| 132 | u32 *data; |
| 133 | struct mrc_data_container *mrc_cache, *mrc_next; |
| 134 | u8 *mrc_region, *region_ptr; |
| 135 | u16 c1, c2, checksum, seed_checksum; |
| 136 | u32 region_size, entry_id = 0; |
| 137 | u64 flashrom_base = 0; |
| 138 | |
| 139 | // preset just in case there is an error |
| 140 | pei_data->mrc_input = NULL; |
| 141 | pei_data->mrc_input_len = 0; |
| 142 | |
| 143 | /* Read scrambler seeds from CMOS */ |
| 144 | pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED); |
| 145 | printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n", |
| 146 | pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
| 147 | |
| 148 | pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3); |
| 149 | printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", |
| 150 | pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
| 151 | |
| 152 | /* Compute seed checksum and compare */ |
| 153 | c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, |
| 154 | sizeof(u32)); |
| 155 | c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, |
| 156 | sizeof(u32)); |
| 157 | checksum = add_ip_checksums(sizeof(u32), c1, c2); |
| 158 | |
| 159 | seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); |
| 160 | seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8; |
| 161 | |
| 162 | if (checksum != seed_checksum) { |
| 163 | printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__); |
| 164 | pei_data->scrambler_seed = 0; |
| 165 | pei_data->scrambler_seed_s3 = 0; |
| 166 | return; |
| 167 | } |
| 168 | |
| 169 | fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT); |
| 170 | |
| 171 | if (!fdt_header) { |
| 172 | printk(BIOS_ERR, "%s: no FDT found!\n", __func__); |
| 173 | return; |
| 174 | } |
| 175 | |
| 176 | offset = fdt_node_offset_by_compatible(fdt_header, 0, compatible); |
| 177 | if (offset < 0) { |
| 178 | printk(BIOS_ERR, "%s: no %s node found!\n", |
| 179 | __func__, compatible); |
| 180 | return; |
| 181 | } |
| 182 | |
| 183 | if (fdt_get_base_addr(fdt_header, offset, &flashrom_base) < 0) { |
| 184 | printk(BIOS_ERR, "%s: no base address in node name!\n", |
| 185 | __func__); |
| 186 | return; |
| 187 | } |
| 188 | |
| 189 | offset = fdt_subnode_offset(fdt_header, offset, subnode); |
| 190 | if (offset < 0) { |
| 191 | printk(BIOS_ERR, "%s: no %s found!\n", __func__, subnode); |
| 192 | return; |
| 193 | } |
| 194 | |
| 195 | fdtp = fdt_get_property(fdt_header, offset, property, &len); |
| 196 | if (!fdtp || (len != 8)) { |
| 197 | printk(BIOS_ERR, "%s: property %s at %p, len %d!\n", |
| 198 | __func__, property, fdtp, len); |
| 199 | return; |
| 200 | } |
| 201 | |
| 202 | data = (u32 *)fdtp->data; |
| 203 | |
| 204 | // Calculate actual address of the MRC cache in memory |
| 205 | region_size = fdt32_to_cpu(data[1]); |
| 206 | mrc_region = region_ptr = (u8*) |
| 207 | ((unsigned long)flashrom_base + fdt32_to_cpu(data[0])); |
| 208 | mrc_cache = mrc_next = (struct mrc_data_container *)mrc_region; |
| 209 | |
| 210 | if (!mrc_cache || mrc_cache->mrc_signature != MRC_DATA_SIGNATURE) { |
| 211 | printk(BIOS_ERR, "%s: invalid MRC data\n", __func__); |
| 212 | return; |
| 213 | } |
| 214 | |
| 215 | if (mrc_cache->mrc_data_size == -1UL) { |
| 216 | printk(BIOS_ERR, "%s: MRC cache not initialized?\n", __func__); |
| 217 | return; |
| 218 | } else { |
| 219 | /* MRC data blocks are aligned within the region */ |
| 220 | u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; |
| 221 | if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { |
| 222 | mrc_size &= ~(MRC_DATA_ALIGN - 1UL); |
| 223 | mrc_size += MRC_DATA_ALIGN; |
| 224 | } |
| 225 | |
| 226 | /* Search for the last filled entry in the region */ |
| 227 | while (mrc_next && |
| 228 | mrc_next->mrc_signature == MRC_DATA_SIGNATURE) { |
| 229 | entry_id++; |
| 230 | mrc_cache = mrc_next; |
| 231 | /* Stay in the mrcdata region defined in fdt */ |
| 232 | if ((entry_id * mrc_size) > region_size) |
| 233 | break; |
| 234 | region_ptr += mrc_size; |
| 235 | mrc_next = (struct mrc_data_container *)region_ptr; |
| 236 | } |
| 237 | entry_id--; |
| 238 | } |
| 239 | |
| 240 | /* Verify checksum */ |
| 241 | if (mrc_cache->mrc_checksum != |
| 242 | compute_ip_checksum(mrc_cache->mrc_data, |
| 243 | mrc_cache->mrc_data_size)) { |
| 244 | printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); |
| 245 | return; |
| 246 | } |
| 247 | |
| 248 | pei_data->mrc_input = mrc_cache->mrc_data; |
| 249 | pei_data->mrc_input_len = mrc_cache->mrc_data_size; |
| 250 | |
| 251 | printk(BIOS_DEBUG, "%s: at %p, entry %u size %x checksum %04x\n", |
| 252 | __func__, pei_data->mrc_input, entry_id, |
| 253 | pei_data->mrc_input_len, mrc_cache->mrc_checksum); |
Stefan Reinauer | 6ea86b1 | 2012-04-27 22:54:10 +0200 | [diff] [blame] | 254 | #else |
| 255 | printk(BIOS_ERR, "MRC cache handling code has to be redone."); |
| 256 | #endif |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 257 | } |
| 258 | #endif |
| 259 | |
| 260 | static const char* ecc_decoder[] = { |
| 261 | "inactive", |
| 262 | "active on IO", |
| 263 | "disabled on IO", |
| 264 | "active" |
| 265 | }; |
| 266 | |
| 267 | /* |
| 268 | * Dump in the log memory controller configuration as read from the memory |
| 269 | * controller registers. |
| 270 | */ |
| 271 | static void report_memory_config(void) |
| 272 | { |
| 273 | u32 addr_decoder_common, addr_decode_ch[2]; |
| 274 | int i; |
| 275 | |
| 276 | addr_decoder_common = MCHBAR32(0x5000); |
| 277 | addr_decode_ch[0] = MCHBAR32(0x5004); |
| 278 | addr_decode_ch[1] = MCHBAR32(0x5008); |
| 279 | |
| 280 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
| 281 | (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); |
| 282 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
| 283 | addr_decoder_common & 3, |
| 284 | (addr_decoder_common >> 2) & 3, |
| 285 | (addr_decoder_common >> 4) & 3); |
| 286 | |
| 287 | for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { |
| 288 | u32 ch_conf = addr_decode_ch[i]; |
| 289 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", |
| 290 | i, ch_conf); |
| 291 | printk(BIOS_DEBUG, " ECC %s\n", |
| 292 | ecc_decoder[(ch_conf >> 24) & 3]); |
| 293 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 294 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
| 295 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 296 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
| 297 | printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", |
| 298 | ((ch_conf >> 0) & 0xff) * 256, |
| 299 | ((ch_conf >> 19) & 1) ? 16 : 8, |
| 300 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 301 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
| 302 | printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", |
| 303 | ((ch_conf >> 8) & 0xff) * 256, |
| 304 | ((ch_conf >> 20) & 1) ? 16 : 8, |
| 305 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 306 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 307 | } |
| 308 | } |
| 309 | |
| 310 | /** |
| 311 | * Find PEI executable in coreboot filesystem and execute it. |
| 312 | * |
| 313 | * @param pei_data: configuration data for UEFI PEI reference code |
| 314 | */ |
| 315 | void sdram_initialize(struct pei_data *pei_data) |
| 316 | { |
| 317 | struct sys_info sysinfo; |
| 318 | const char *target = "mrc.bin"; |
| 319 | unsigned long entry; |
| 320 | |
| 321 | /* Wait for ME to be ready */ |
| 322 | intel_early_me_init(); |
| 323 | intel_early_me_uma_size(); |
| 324 | |
| 325 | printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); |
| 326 | |
| 327 | memset(&sysinfo, 0, sizeof(sysinfo)); |
| 328 | |
| 329 | sysinfo.boot_path = pei_data->boot_mode; |
| 330 | |
| 331 | #if CONFIG_CHROMEOS |
| 332 | /* |
| 333 | * Do not pass MRC data in for recovery mode boot, |
| 334 | * Always pass it in for S3 resume. |
| 335 | */ |
| 336 | if (!recovery_mode_enabled() || pei_data->boot_mode == 2) |
| 337 | prepare_mrc_cache(pei_data); |
| 338 | |
| 339 | /* If MRC data is not found we cannot continue S3 resume. */ |
| 340 | if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { |
| 341 | outb(0x6, 0xcf9); |
| 342 | hlt(); |
| 343 | } |
| 344 | #endif |
| 345 | |
| 346 | /* Locate and call UEFI System Agent binary. */ |
| 347 | entry = (unsigned long)cbfs_find_file(target, 0xab); |
| 348 | if (entry) { |
| 349 | int rv; |
| 350 | asm volatile ( |
| 351 | "call *%%ecx\n\t" |
| 352 | :"=a" (rv) : "c" (entry), "a" (pei_data)); |
| 353 | if (rv) { |
| 354 | printk(BIOS_ERR, "MRC returned %d\n", rv); |
| 355 | die("Nonzero MRC return value\n"); |
| 356 | } |
| 357 | } else { |
| 358 | die("UEFI PEI System Agent not found.\n"); |
| 359 | } |
| 360 | |
| 361 | /* For reference print the System Agent version |
| 362 | * after executing the UEFI PEI stage. |
| 363 | */ |
| 364 | u32 version = MCHBAR32(0x5034); |
| 365 | printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", |
| 366 | version >> 24 , (version >> 16) & 0xff, |
| 367 | (version >> 8) & 0xff, version & 0xff); |
| 368 | |
Duncan Laurie | 7b508dd | 2012-04-09 12:30:43 -0700 | [diff] [blame] | 369 | /* Send ME init done for SandyBridge here. This is done |
| 370 | * inside the SystemAgent binary on IvyBridge. */ |
| 371 | if (BASE_REV_SNB == |
| 372 | (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK)) |
| 373 | intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); |
| 374 | else |
| 375 | intel_early_me_status(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 376 | |
| 377 | report_memory_config(); |
| 378 | |
| 379 | /* S3 resume: don't save scrambler seed or MRC data */ |
| 380 | if (pei_data->boot_mode != 2) |
| 381 | save_mrc_data(pei_data); |
| 382 | } |
| 383 | |
| 384 | struct cbmem_entry *get_cbmem_toc(void) |
| 385 | { |
| 386 | return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); |
| 387 | } |
| 388 | |
| 389 | unsigned long get_top_of_ram(void) |
| 390 | { |
| 391 | /* Base of TSEG is top of usable DRAM */ |
| 392 | u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); |
| 393 | return (unsigned long) tom; |
| 394 | } |