Uwe Hermann | 95aa53a | 2009-10-13 19:21:44 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; either version 2 of the License, or |
| 9 | ## (at your option) any later version. |
| 10 | ## |
| 11 | ## This program is distributed in the hope that it will be useful, |
| 12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | ## GNU General Public License for more details. |
| 15 | ## |
| 16 | ## You should have received a copy of the GNU General Public License |
| 17 | ## along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Uwe Hermann | 95aa53a | 2009-10-13 19:21:44 +0000 | [diff] [blame] | 19 | ## |
| 20 | |
| 21 | chip northbridge/intel/i440bx # Northbridge |
Elyes HAOUAS | 7a3ca74 | 2014-07-23 10:32:34 +0200 | [diff] [blame^] | 22 | device cpu_cluster 0 on # APIC cluster |
| 23 | chip cpu/intel/slot_1 # CPU |
| 24 | device lapic 0 on end # APIC |
| 25 | end |
| 26 | end |
| 27 | device domain 0 on # PCI domain |
| 28 | device pci 0.0 on end # Host bridge |
| 29 | device pci 1.0 on end # PCI/AGP bridge |
| 30 | chip southbridge/intel/i82371eb # Southbridge |
| 31 | device pci 7.0 on # ISA bridge |
| 32 | chip superio/winbond/w83977tf # Super I/O |
| 33 | device pnp 3f0.0 on # Floppy |
| 34 | io 0x60 = 0x3f0 |
| 35 | irq 0x70 = 6 |
| 36 | drq 0x74 = 2 |
| 37 | end |
| 38 | device pnp 3f0.1 on # Parallel port |
| 39 | io 0x60 = 0x378 |
| 40 | irq 0x70 = 7 |
| 41 | drq 0x74 = 3 |
| 42 | end |
| 43 | device pnp 3f0.2 on # COM1 |
| 44 | io 0x60 = 0x3f8 |
| 45 | irq 0x70 = 4 |
| 46 | end |
| 47 | device pnp 3f0.3 on # COM2 / IR |
| 48 | io 0x60 = 0x2f8 |
| 49 | irq 0x70 = 3 |
| 50 | end |
| 51 | device pnp 3f0.5 on # PS/2 keyboard |
| 52 | io 0x60 = 0x60 |
| 53 | io 0x62 = 0x64 |
| 54 | irq 0x70 = 1 # PS/2 keyboard interrupt |
| 55 | irq 0x72 = 12 # PS/2 mouse interrupt |
| 56 | end |
| 57 | device pnp 3f0.7 off # GPIO 1 |
| 58 | end |
| 59 | device pnp 3f0.8 off # GPIO 2 |
| 60 | end |
| 61 | device pnp 3f0.9 off # GPIO 3 |
| 62 | end |
| 63 | device pnp 3f0.a off # ACPI |
| 64 | end |
| 65 | end |
| 66 | end |
| 67 | device pci 7.1 on end # IDE |
| 68 | device pci 7.2 on end # USB |
| 69 | device pci 7.3 on end # ACPI |
| 70 | device pci 14.0 on end # Onboard audio (Ensoniq ES1371) |
| 71 | register "ide0_enable" = "1" |
| 72 | register "ide1_enable" = "1" |
| 73 | register "ide_legacy_enable" = "1" |
| 74 | # Enable UDMA/33 for higher speed if your IDE device(s) support it. |
| 75 | register "ide0_drive0_udma33_enable" = "1" |
| 76 | register "ide0_drive1_udma33_enable" = "1" |
| 77 | register "ide1_drive0_udma33_enable" = "1" |
| 78 | register "ide1_drive1_udma33_enable" = "1" |
| 79 | end |
| 80 | end |
Uwe Hermann | 95aa53a | 2009-10-13 19:21:44 +0000 | [diff] [blame] | 81 | end |