blob: 57e35eeb3ce1e76e869f4c90b7d0287edbe3a598 [file] [log] [blame]
Lee Leahy102f6252016-07-25 07:41:54 -07001/*
2 * This file is part of the coreboot project.
3 *
Lee Leahy94b971a2017-03-06 08:59:23 -08004 * Copyright (C) 2016-2017 Intel Corp.
Lee Leahy102f6252016-07-25 07:41:54 -07005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
Kyösti Mälkki6e2d0c12019-06-28 10:08:51 +030016#include <arch/cpu.h>
Kyösti Mälkkia963acd2019-08-16 20:34:25 +030017#include <arch/romstage.h>
Arthur Heymans84e22e32019-05-25 09:57:27 +020018#include <arch/symbols.h>
Lee Leahy102f6252016-07-25 07:41:54 -070019#include <console/console.h>
Lee Leahyf26fc0f2016-07-25 10:14:07 -070020#include <cbmem.h>
21#include "../chip.h"
22#include <cpu/x86/cache.h>
Lee Leahy102f6252016-07-25 07:41:54 -070023#include <fsp/util.h>
Lee Leahy16bc9ba2017-04-01 20:33:58 -070024#include <soc/iomap.h>
Lee Leahyf26fc0f2016-07-25 10:14:07 -070025#include <soc/pci_devs.h>
26#include <soc/pm.h>
Lee Leahy102f6252016-07-25 07:41:54 -070027#include <soc/romstage.h>
Lee Leahyf26fc0f2016-07-25 10:14:07 -070028#include <soc/reg_access.h>
Lee Leahy16bc9ba2017-04-01 20:33:58 -070029#include <soc/storage_test.h>
Lee Leahy102f6252016-07-25 07:41:54 -070030
Kyösti Mälkkicd7a70f2019-08-17 20:51:08 +030031static struct postcar_frame early_mtrrs;
32
Arthur Heymansbe291e82019-01-06 07:35:11 +010033asmlinkage void car_stage_c_entry(void)
Lee Leahy102f6252016-07-25 07:41:54 -070034{
Lee Leahyf26fc0f2016-07-25 10:14:07 -070035 bool s3wake;
Lee Leahyf26fc0f2016-07-25 10:14:07 -070036
Lee Leahy102f6252016-07-25 07:41:54 -070037 post_code(0x20);
38 console_init();
Lee Leahyf26fc0f2016-07-25 10:14:07 -070039
Julius Wernercd49cce2019-03-05 16:53:33 -080040 if (CONFIG(STORAGE_TEST)) {
Lee Leahy16bc9ba2017-04-01 20:33:58 -070041 uint32_t bar;
Elyes HAOUAS6f01f432018-12-05 10:56:30 +010042 pci_devfn_t dev;
Lee Leahy16bc9ba2017-04-01 20:33:58 -070043 uint32_t previous_bar;
44 uint16_t previous_command;
45
46 /* Enable the SD/MMC controller and run the test. Restore
47 * the BAR and command registers upon completion.
48 */
49 dev = PCI_DEV(0, SD_MMC_DEV, SD_MMC_FUNC);
50 bar = storage_test_init(dev, &previous_bar, &previous_command);
51 storage_test(bar, 1);
52 storage_test_complete(dev, previous_bar, previous_command);
53 }
54
Lee Leahyf26fc0f2016-07-25 10:14:07 -070055 /* Initialize DRAM */
56 s3wake = fill_power_state() == ACPI_S3;
57 fsp_memory_init(s3wake);
58
59 /* Disable the ROM shadow 0x000e0000 - 0x000fffff */
60 disable_rom_shadow();
61
62 /* Initialize the PCIe bridges */
63 pcie_init();
64
Kyösti Mälkkicd7a70f2019-08-17 20:51:08 +030065 prepare_and_run_postcar(&early_mtrrs);
66 /* We do not return here. */
67}
68
Arthur Heymans84e22e32019-05-25 09:57:27 +020069static struct chipset_power_state power_state;
Lee Leahyf26fc0f2016-07-25 10:14:07 -070070
71struct chipset_power_state *get_power_state(void)
72{
Arthur Heymans84e22e32019-05-25 09:57:27 +020073 return &power_state;
Lee Leahyf26fc0f2016-07-25 10:14:07 -070074}
75
76int fill_power_state(void)
77{
Arthur Heymans84e22e32019-05-25 09:57:27 +020078 power_state.prev_sleep_state = 0;
79 printk(BIOS_SPEW, "prev_sleep_state %d\n",
80 power_state.prev_sleep_state);
81 return power_state.prev_sleep_state;
Lee Leahyf26fc0f2016-07-25 10:14:07 -070082}
83
Andrey Petrovf796c6e2016-11-18 14:57:51 -080084void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
Lee Leahyf26fc0f2016-07-25 10:14:07 -070085{
Lee Leahy44ec92a2016-09-28 17:16:44 -070086 FSPM_ARCH_UPD *aupd;
Lee Leahyf26fc0f2016-07-25 10:14:07 -070087 const struct soc_intel_quark_config *config;
Lee Leahy70bb0572017-03-13 16:37:20 -070088 void *rmu_data;
89 size_t rmu_data_len;
Lee Leahy44ec92a2016-09-28 17:16:44 -070090 FSP_M_CONFIG *upd;
Lee Leahyf26fc0f2016-07-25 10:14:07 -070091
92 /* Clear SMI and wake events */
93 clear_smi_and_wake_events();
94
95 /* Locate the RMU data file in flash */
Lee Leahy70bb0572017-03-13 16:37:20 -070096 rmu_data = locate_rmu_file(&rmu_data_len);
97 if (!rmu_data)
Keith Short1835bf02019-05-16 11:46:27 -060098 die_with_post_code(POST_INVALID_CBFS,
99 "Microcode file (rmu.bin) not found.");
Lee Leahyf26fc0f2016-07-25 10:14:07 -0700100
101 /* Locate the configuration data from devicetree.cb */
Kyösti Mälkki8950cfb2019-07-13 22:16:25 +0300102 config = config_of_path(LPC_DEV_FUNC);
Lee Leahyf26fc0f2016-07-25 10:14:07 -0700103
104 /* Update the architectural UPD values. */
105 aupd = &fspm_upd->FspmArchUpd;
106 aupd->BootLoaderTolumSize = cbmem_overhead_size();
107 aupd->StackBase = (void *)(CONFIG_FSP_ESRAM_LOC - aupd->StackSize);
108 aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION;
109
110 /* Display the ESRAM layout */
Julius Wernercd49cce2019-03-05 16:53:33 -0800111 if (CONFIG(DISPLAY_ESRAM_LAYOUT)) {
Lee Leahyf26fc0f2016-07-25 10:14:07 -0700112 printk(BIOS_SPEW, "\nESRAM Layout:\n\n");
113 printk(BIOS_SPEW,
114 "+-------------------+ 0x80080000 - ESRAM end\n");
115 printk(BIOS_SPEW, "| FSP binary |\n");
116 printk(BIOS_SPEW,
117 "+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n",
118 CONFIG_FSP_ESRAM_LOC);
119 printk(BIOS_SPEW, "| FSP stack |\n");
120 printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
121 aupd->StackBase);
122 printk(BIOS_SPEW, "| |\n");
123 printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
124 _car_relocatable_data_end);
125 printk(BIOS_SPEW, "| coreboot data |\n");
126 printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
127 _car_stack_end);
128 printk(BIOS_SPEW, "| coreboot stack |\n");
129 printk(BIOS_SPEW,
130 "+-------------------+ 0x80000000 - ESRAM start\n\n");
131 }
132
133 /* Update the UPD data for MemoryInit */
134 upd = &fspm_upd->FspmConfig;
135 upd->AddrMode = config->AddrMode;
136 upd->ChanMask = config->ChanMask;
137 upd->ChanWidth = config->ChanWidth;
138 upd->DramDensity = config->DramDensity;
139 upd->DramRonVal = config->DramRonVal;
140 upd->DramRttNomVal = config->DramRttNomVal;
141 upd->DramRttWrVal = config->DramRttWrVal;
142 upd->DramSpeed = config->DramSpeed;
143 upd->DramType = config->DramType;
144 upd->DramWidth = config->DramWidth;
145 upd->EccScrubBlkSize = config->EccScrubBlkSize;
146 upd->EccScrubInterval = config->EccScrubInterval;
147 upd->Flags = config->Flags;
148 upd->FspReservedMemoryLength = config->FspReservedMemoryLength;
149 upd->RankMask = config->RankMask;
Lee Leahy70bb0572017-03-13 16:37:20 -0700150 upd->RmuBaseAddress = (uintptr_t)rmu_data;
151 upd->RmuLength = rmu_data_len;
Kyösti Mälkkie613d702019-02-12 14:16:21 +0200152 upd->SerialPortWriteChar = !!console_log_level(BIOS_SPEW)
Lee Leahy5e07a7e2016-08-06 09:51:35 -0700153 ? (uintptr_t)fsp_write_line : 0;
Julius Wernercd49cce2019-03-05 16:53:33 -0800154 upd->SmmTsegSize = CONFIG(HAVE_SMI_HANDLER) ?
Lee Leahyf26fc0f2016-07-25 10:14:07 -0700155 config->SmmTsegSize : 0;
156 upd->SocRdOdtVal = config->SocRdOdtVal;
157 upd->SocWrRonVal = config->SocWrRonVal;
158 upd->SocWrSlewRate = config->SocWrSlewRate;
159 upd->SrInt = config->SrInt;
160 upd->SrTemp = config->SrTemp;
161 upd->tCL = config->tCL;
162 upd->tFAW = config->tFAW;
163 upd->tRAS = config->tRAS;
164 upd->tRRD = config->tRRD;
165 upd->tWTR = config->tWTR;
166}