blob: c19c0cf93c66c4c4785d5674ab505a9e1650c6c7 [file] [log] [blame]
Andrey Petrov2e410752020-03-20 12:08:32 -07001/* SPDX-License-Identifier: GPL-2.0-only */
Andrey Petrov2e410752020-03-20 12:08:32 -07002
3#include <arch/ioapic.h>
Andrey Petrov2e410752020-03-20 12:08:32 -07004#include <console/console.h>
5#include <cpu/x86/lapic.h>
6#include <device/pci.h>
7#include <fsp/api.h>
Andrey Petrov4e48ac02020-04-30 14:08:19 -07008#include <intelblocks/p2sb.h>
Andrey Petrov8670e822020-03-30 12:25:06 -07009#include <soc/cpu.h>
Andrey Petrov2e410752020-03-20 12:08:32 -070010#include <soc/ramstage.h>
11#include <soc/pm.h>
12
13/* C620 IOAPIC has 120 redirection entries */
14#define C620_IOAPIC_REDIR_ENTRIES 120
15
Andrey Petrov2e410752020-03-20 12:08:32 -070016void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
17{
18 /* not implemented yet */
19}
20
21static struct device_operations pci_domain_ops = {
22 .read_resources = &pci_domain_read_resources,
23 .set_resources = &pci_domain_set_resources,
24 .scan_bus = &pci_domain_scan_bus,
25};
26
Andrey Petrov2e410752020-03-20 12:08:32 -070027static struct device_operations cpu_bus_ops = {
Nico Huber2f8ba692020-04-05 14:05:24 +020028 .read_resources = noop_read_resources,
29 .set_resources = noop_set_resources,
Andrey Petrov8670e822020-03-30 12:25:06 -070030 .init = cpx_init_cpus,
Andrey Petrov2e410752020-03-20 12:08:32 -070031};
32
33static void chip_enable_dev(struct device *dev)
34{
35 /* Set the operations if it is a special bus type */
36 if (dev->path.type == DEVICE_PATH_DOMAIN) {
37 dev->ops = &pci_domain_ops;
38 } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
39 dev->ops = &cpu_bus_ops;
40 }
41}
42
43static void pch_enable_ioapic(const struct device *dev)
44{
45 uint32_t reg32;
46
47 set_ioapic_id((void *)IO_APIC_ADDR, 2);
48
49 /* affirm full set of redirection table entries ("write once") */
50 reg32 = io_apic_read((void *)IO_APIC_ADDR, 1);
51
52 reg32 &= ~0x00ff0000;
53 reg32 |= (C620_IOAPIC_REDIR_ENTRIES - 1) << 16;
54
55 io_apic_write((void *)IO_APIC_ADDR, 1, reg32);
56
57 /*
58 * Select Boot Configuration register (0x03) and
59 * use Processor System Bus (0x01) to deliver interrupts.
60 */
61 io_apic_write((void *)IO_APIC_ADDR, 3, 1);
62}
63
64struct pci_operations soc_pci_ops = {
65 .set_subsystem = pci_dev_set_subsystem,
66};
67
68static void chip_final(void *data)
69{
Andrey Petrov4e48ac02020-04-30 14:08:19 -070070 p2sb_hide();
Andrey Petrov2e410752020-03-20 12:08:32 -070071}
72
73static void chip_init(void *data)
74{
75 printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
76 fsp_silicon_init(false);
77 pch_enable_ioapic(NULL);
78 setup_lapic();
Andrey Petrov4e48ac02020-04-30 14:08:19 -070079 p2sb_unhide();
Andrey Petrov2e410752020-03-20 12:08:32 -070080}
81
82struct chip_operations soc_intel_xeon_sp_cpx_ops = {
83 CHIP_NAME("Intel Cooperlake-SP")
84 .enable_dev = chip_enable_dev,
85 .init = chip_init,
86 .final = chip_final
87};