Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011-2013 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
| 5 | * |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation, either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | /** |
| 21 | * @file ddr3_util.h |
| 22 | * |
| 23 | * \brief Utilities for decoding DDR3 SPDs |
| 24 | */ |
| 25 | |
| 26 | #include <console/console.h> |
| 27 | #include <device/device.h> |
| 28 | #include <device/dram/ddr3.h> |
| 29 | |
| 30 | /** |
| 31 | * \brief Checks if the DIMM is Registered based on byte[3] of the SPD |
| 32 | * |
| 33 | * Tells if the DIMM type is registered or not. |
| 34 | * |
| 35 | * @param type DIMM type. This is byte[3] of the SPD. |
| 36 | */ |
| 37 | int dimm_is_registered(enum spd_dimm_type type) |
| 38 | { |
| 39 | if ((type == SPD_DIMM_TYPE_RDIMM) |
| 40 | | (type == SPD_DIMM_TYPE_MINI_RDIMM) |
| 41 | | (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) |
| 42 | return 1; |
| 43 | |
| 44 | return 0; |
| 45 | } |
| 46 | |
| 47 | /** |
| 48 | * \brief Decode the raw SPD data |
| 49 | * |
| 50 | * Decodes a raw SPD data from a DDR3 DIMM, and organizes it into a |
| 51 | * @ref dimm_attr structure. The SPD data must first be read in a contiguous |
| 52 | * array, and passed to this function. |
| 53 | * |
| 54 | * @param dimm pointer to @ref dimm_attr stucture where the decoded data is to |
| 55 | * be stored |
| 56 | * @param spd array of raw data previously read from the SPD. |
| 57 | * |
| 58 | * @return @ref spd_status enumerator |
| 59 | * SPD_STATUS_OK -- decoding was successful |
| 60 | * SPD_STATUS_INVALID -- invalid SPD or not a DDR3 SPD |
| 61 | * SPD_STATUS_CRC_ERROR -- CRC did not verify |
| 62 | * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was |
| 63 | * detected. |
| 64 | */ |
| 65 | int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) |
| 66 | { |
| 67 | int nCRC, i, ret; |
| 68 | u16 crc, spd_crc; |
| 69 | u8 *ptr = spd; |
| 70 | u8 ftb_divisor, ftb_dividend, capacity_shift, bus_width, sdram_width; |
| 71 | u8 reg8; |
| 72 | u32 mtb; /* medium time base */ |
| 73 | unsigned int val, param; |
| 74 | |
| 75 | ret = SPD_STATUS_OK; |
| 76 | |
| 77 | /* Don't assume we memset 0 dimm struct. Clear all our flags */ |
| 78 | dimm->flags.raw = 0; |
| 79 | /* Make sure that the SPD dump is indeed from a DDR3 module */ |
| 80 | if (spd[2] != SPD_MEMORY_TYPE_SDRAM_DDR3) { |
| 81 | printram("Not a DDR3 SPD!\n"); |
| 82 | dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; |
| 83 | return SPD_STATUS_INVALID; |
| 84 | } |
| 85 | dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3; |
| 86 | |
| 87 | /* Find the number of bytes covered by CRC */ |
| 88 | if (spd[0] & 0x80) { |
| 89 | nCRC = 117; |
| 90 | } else { |
| 91 | nCRC = 126; |
| 92 | } |
| 93 | |
| 94 | /* Compute the CRC */ |
| 95 | crc = 0; |
| 96 | while (--nCRC >= 0) { |
| 97 | crc = crc ^ (int)*ptr++ << 8; |
| 98 | for (i = 0; i < 8; ++i) |
| 99 | if (crc & 0x8000) { |
| 100 | crc = crc << 1 ^ 0x1021; |
| 101 | } else { |
| 102 | crc = crc << 1; |
| 103 | } |
| 104 | } |
| 105 | /* Compare with the CRC in the SPD */ |
| 106 | spd_crc = (spd[127] << 8) + spd[126]; |
| 107 | /* Verify the CRC is correct */ |
| 108 | if (crc != spd_crc) { |
| 109 | printram("ERROR: SPD CRC failed!!!"); |
| 110 | ret = SPD_STATUS_CRC_ERROR; |
| 111 | }; |
| 112 | |
| 113 | printram(" Revision: %x\n", spd[1]); |
| 114 | printram(" Type : %x\n", spd[2]); |
| 115 | printram(" Key : %x\n", spd[3]); |
| 116 | |
| 117 | reg8 = spd[4]; |
| 118 | /* Number of memory banks */ |
| 119 | val = (reg8 >> 4) & 0x07; |
| 120 | if (val > 0x03) { |
| 121 | printram(" Invalid number of memory banks\n"); |
| 122 | ret = SPD_STATUS_INVALID_FIELD; |
| 123 | } |
| 124 | param = 1 << (val + 3); |
| 125 | printram(" Banks : %u\n", param); |
| 126 | /* SDRAM capacity */ |
| 127 | capacity_shift = reg8 & 0x0f; |
| 128 | if (capacity_shift > 0x06) { |
| 129 | printram(" Invalid module capacity\n"); |
| 130 | ret = SPD_STATUS_INVALID_FIELD; |
| 131 | } |
| 132 | if (capacity_shift < 0x02) { |
| 133 | printram(" Capacity: %u Mb\n", 256 << capacity_shift); |
| 134 | } else { |
| 135 | printram(" Capacity: %u Gb\n", 1 << (capacity_shift - 2)); |
| 136 | } |
| 137 | |
| 138 | reg8 = spd[5]; |
| 139 | /* Row address bits */ |
| 140 | val = (reg8 >> 3) & 0x07; |
| 141 | if (val > 0x04) { |
| 142 | printram(" Invalid row address bits\n"); |
| 143 | ret = SPD_STATUS_INVALID_FIELD; |
| 144 | } |
| 145 | dimm->row_bits = val + 12; |
| 146 | /* Column address bits */ |
| 147 | val = reg8 & 0x07; |
| 148 | if (val > 0x03) { |
| 149 | printram(" Invalid column address bits\n"); |
| 150 | ret = SPD_STATUS_INVALID_FIELD; |
| 151 | } |
| 152 | dimm->col_bits = val + 9; |
| 153 | |
| 154 | /* Module nominal voltage */ |
| 155 | reg8 = spd[6]; |
| 156 | printram(" Supported voltages:"); |
| 157 | if (reg8 & (1 << 2)) { |
| 158 | dimm->flags.operable_1_25V = 1; |
| 159 | printram(" 1.25V"); |
| 160 | } |
| 161 | if (reg8 & (1 << 1)) { |
| 162 | dimm->flags.operable_1_35V = 1; |
| 163 | printram(" 1.35V"); |
| 164 | } |
| 165 | if (!(reg8 & (1 << 0))) { |
| 166 | dimm->flags.operable_1_50V = 1; |
| 167 | printram(" 1.5V"); |
| 168 | } |
| 169 | printram("\n"); |
| 170 | |
| 171 | /* Module organization */ |
| 172 | reg8 = spd[7]; |
| 173 | /* Number of ranks */ |
| 174 | val = (reg8 >> 3) & 0x07; |
| 175 | if (val > 3) { |
| 176 | printram(" Invalid number of ranks\n"); |
| 177 | ret = SPD_STATUS_INVALID_FIELD; |
| 178 | } |
| 179 | dimm->ranks = val + 1; |
| 180 | /* SDRAM device width */ |
| 181 | val = (reg8 & 0x07); |
| 182 | if (val > 3) { |
| 183 | printram(" Invalid SDRAM width\n"); |
| 184 | ret = SPD_STATUS_INVALID_FIELD; |
| 185 | } |
| 186 | sdram_width = (4 << val); |
| 187 | printram(" SDRAM width : %u\n", sdram_width); |
| 188 | |
| 189 | /* Memory bus width */ |
| 190 | reg8 = spd[8]; |
| 191 | /* Bus extension */ |
| 192 | val = (reg8 >> 3) & 0x03; |
| 193 | if (val > 1) { |
| 194 | printram(" Invalid bus extension\n"); |
| 195 | ret = SPD_STATUS_INVALID_FIELD; |
| 196 | } |
| 197 | dimm->flags.is_ecc = val ? 1 : 0; |
| 198 | printram(" Bus extension : %u bits\n", val ? 8 : 0); |
| 199 | /* Bus width */ |
| 200 | val = reg8 & 0x07; |
| 201 | if (val > 3) { |
| 202 | printram(" Invalid bus width\n"); |
| 203 | ret = SPD_STATUS_INVALID_FIELD; |
| 204 | } |
| 205 | bus_width = 8 << val; |
| 206 | printram(" Bus width : %u\n", bus_width); |
| 207 | |
| 208 | /* We have all the info we need to compute the dimm size */ |
| 209 | /* Capacity is 256Mbit multiplied by the power of 2 specified in |
| 210 | * capacity_shift |
| 211 | * The rest is the JEDEC formula */ |
| 212 | dimm->size_mb = ((1 << (capacity_shift + (25 - 20))) * bus_width |
| 213 | * dimm->ranks) / sdram_width; |
| 214 | |
| 215 | /* Fine Timebase (FTB) Dividend/Divisor */ |
| 216 | /* Dividend */ |
| 217 | ftb_dividend = (spd[9] >> 4) & 0x0f; |
| 218 | /* Divisor */ |
| 219 | ftb_divisor = spd[9] & 0x0f; |
| 220 | |
| 221 | /* Medium Timebase = |
| 222 | * Medium Timebase (MTB) Dividend / |
| 223 | * Medium Timebase (MTB) Divisor */ |
| 224 | mtb = (((u32) spd[10]) << 8) / spd[11]; |
| 225 | |
| 226 | /* SDRAM Minimum Cycle Time (tCKmin) */ |
| 227 | dimm->tCK = spd[12] * mtb; |
| 228 | /* CAS Latencies Supported */ |
| 229 | dimm->cas_supported = (spd[15] << 8) + spd[14]; |
| 230 | /* Minimum CAS Latency Time (tAAmin) */ |
| 231 | dimm->tAA = spd[16] * mtb; |
| 232 | /* Minimum Write Recovery Time (tWRmin) */ |
| 233 | dimm->tWR = spd[17] * mtb; |
| 234 | /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ |
| 235 | dimm->tRCD = spd[18] * mtb; |
| 236 | /* Minimum Row Active to Row Active Delay Time (tRRDmin) */ |
| 237 | dimm->tRRD = spd[19] * mtb; |
| 238 | /* Minimum Row Precharge Delay Time (tRPmin) */ |
| 239 | dimm->tRP = spd[20] * mtb; |
| 240 | /* Minimum Active to Precharge Delay Time (tRASmin) */ |
| 241 | dimm->tRAS = (((spd[21] & 0x0f) << 8) + spd[22]) * mtb; |
| 242 | /* Minimum Active to Active/Refresh Delay Time (tRCmin) */ |
| 243 | dimm->tRC = (((spd[21] & 0xf0) << 4) + spd[23]) * mtb; |
| 244 | /* Minimum Refresh Recovery Delay Time (tRFCmin) */ |
| 245 | dimm->tRFC = ((spd[25] << 8) + spd[24]) * mtb; |
| 246 | /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */ |
| 247 | dimm->tWTR = spd[26] * mtb; |
| 248 | /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ |
| 249 | dimm->tRTP = spd[27] * mtb; |
| 250 | /* Minimum Four Activate Window Delay Time (tFAWmin) */ |
| 251 | dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb; |
| 252 | |
| 253 | /* SDRAM Optional Features */ |
| 254 | reg8 = spd[30]; |
| 255 | printram(" Optional features :"); |
| 256 | if (reg8 & 0x80) { |
| 257 | dimm->flags.dll_off_mode = 1; |
| 258 | printram(" DLL-Off_mode"); |
| 259 | } |
| 260 | if (reg8 & 0x02) { |
| 261 | dimm->flags.rzq7_supported = 1; |
| 262 | printram(" RZQ/7"); |
| 263 | } |
| 264 | if (reg8 & 0x01) { |
| 265 | dimm->flags.rzq6_supported = 1; |
| 266 | printram(" RZQ/6"); |
| 267 | } |
| 268 | printram("\n"); |
| 269 | |
| 270 | /* SDRAM Thermal and Refresh Options */ |
| 271 | reg8 = spd[31]; |
| 272 | printram(" Thermal features :"); |
| 273 | if (reg8 & 0x80) { |
| 274 | dimm->flags.pasr = 1; |
| 275 | printram(" PASR"); |
| 276 | } |
| 277 | if (reg8 & 0x08) { |
| 278 | dimm->flags.odts = 1; |
| 279 | printram(" ODTS"); |
| 280 | } |
| 281 | if (reg8 & 0x04) { |
| 282 | dimm->flags.asr = 1; |
| 283 | printram(" ASR"); |
| 284 | } |
| 285 | if (reg8 & 0x02) { |
| 286 | dimm->flags.ext_temp_range = 1; |
| 287 | printram(" ext_temp_refresh"); |
| 288 | } |
| 289 | if (reg8 & 0x01) { |
| 290 | dimm->flags.ext_temp_refresh = 1; |
| 291 | printram(" ext_temp_range"); |
| 292 | } |
| 293 | printram("\n"); |
| 294 | |
| 295 | /* Module Thermal Sensor */ |
| 296 | reg8 = spd[32]; |
| 297 | if (reg8 & 0x80) |
| 298 | dimm->flags.therm_sensor = 1; |
| 299 | printram(" Thermal sensor : %s\n", |
| 300 | dimm->flags.therm_sensor ? "yes" : "no"); |
| 301 | |
| 302 | /* SDRAM Device Type */ |
| 303 | reg8 = spd[33]; |
| 304 | printram(" Standard SDRAM : %s\n", (reg8 & 0x80) ? "no" : "yes"); |
| 305 | |
| 306 | if (spd[63] & 0x01) { |
| 307 | dimm->flags.pins_mirrored = 1; |
| 308 | printram(" DIMM Rank1 Address bits mirrorred!!!\n"); |
| 309 | } |
| 310 | |
| 311 | return ret; |
| 312 | } |
| 313 | |
| 314 | /* |
| 315 | * The information printed below has a more informational character, and is not |
| 316 | * necessarily tied in to RAM init debugging. Hence, we stop using printram(), |
| 317 | * and use the standard printk()'s below. |
| 318 | */ |
| 319 | |
| 320 | static void print_ns(const char *msg, u32 val) |
| 321 | { |
| 322 | u32 mant, fp; |
| 323 | mant = val / 256; |
| 324 | fp = (val % 256) * 1000 / 256; |
| 325 | |
| 326 | printk(BIOS_INFO, "%s%3u.%.3u ns\n", msg, mant, fp); |
| 327 | } |
| 328 | |
| 329 | /** |
| 330 | * \brief Print the info in DIMM |
| 331 | * |
| 332 | * Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is |
| 333 | * selected, or for a purely informative output. |
| 334 | * |
| 335 | * @param dimm pointer to already decoded @ref dimm_attr stucture |
| 336 | */ |
| 337 | void dram_print_spd_ddr3(const dimm_attr * dimm) |
| 338 | { |
| 339 | u16 val16; |
| 340 | int i; |
| 341 | |
| 342 | printk(BIOS_INFO, " Row addr bits : %u\n", dimm->row_bits); |
| 343 | printk(BIOS_INFO, " Column addr bits : %u\n", dimm->col_bits); |
| 344 | printk(BIOS_INFO, " Number of ranks : %u\n", dimm->ranks); |
| 345 | printk(BIOS_INFO, " DIMM Capacity : %u MB\n", dimm->size_mb); |
| 346 | |
| 347 | /* CAS Latencies Supported */ |
| 348 | val16 = dimm->cas_supported; |
| 349 | printk(BIOS_INFO, " CAS latencies :"); |
| 350 | i = 0; |
| 351 | do { |
| 352 | if (val16 & 1) |
| 353 | printk(BIOS_INFO, " %u", i + 4); |
| 354 | i++; |
| 355 | val16 >>= 1; |
| 356 | } while (val16); |
| 357 | printk(BIOS_INFO, "\n"); |
| 358 | |
| 359 | print_ns(" tCKmin : ", dimm->tCK); |
| 360 | print_ns(" tAAmin : ", dimm->tAA); |
| 361 | print_ns(" tWRmin : ", dimm->tWR); |
| 362 | print_ns(" tRCDmin : ", dimm->tRCD); |
| 363 | print_ns(" tRRDmin : ", dimm->tRRD); |
| 364 | print_ns(" tRPmin : ", dimm->tRP); |
| 365 | print_ns(" tRASmin : ", dimm->tRAS); |
| 366 | print_ns(" tRCmin : ", dimm->tRC); |
| 367 | print_ns(" tRFCmin : ", dimm->tRFC); |
| 368 | print_ns(" tWTRmin : ", dimm->tWTR); |
| 369 | print_ns(" tRTPmin : ", dimm->tRTP); |
| 370 | print_ns(" tFAWmin : ", dimm->tFAW); |
| 371 | |
| 372 | } |