Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corporation. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <bootstate.h> |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 19 | #include <chip.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 20 | #include <console/console.h> |
| 21 | #include <console/post_codes.h> |
| 22 | #include <cpu/x86/smm.h> |
| 23 | #include <reg_script.h> |
| 24 | #include <spi-generic.h> |
| 25 | #include <stdlib.h> |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 26 | #include <soc/lpc.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 27 | #include <soc/pci_devs.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 28 | #include <soc/pcr.h> |
| 29 | #include <soc/pm.h> |
| 30 | #include <soc/pmc.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 31 | #include <soc/spi.h> |
| 32 | #include <soc/systemagent.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 33 | #include <device/pci.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 34 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 35 | static void pch_finalize_script(void) |
| 36 | { |
| 37 | device_t dev; |
| 38 | uint32_t reg32, hsfs; |
| 39 | void *spibar = get_spi_bar(); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 40 | u16 tcobase; |
| 41 | u16 tcocnt; |
| 42 | uint8_t *pmcbase; |
| 43 | u32 pmsyncreg; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 44 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 45 | /* Set SPI opcode menu */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 46 | write16(spibar + SPIBAR_PREOP, SPI_OPPREFIX); |
| 47 | write16(spibar + SPIBAR_OPTYPE, SPI_OPTYPE); |
| 48 | write32(spibar + SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER); |
| 49 | write32(spibar + SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 50 | /* Lock SPIBAR */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 51 | hsfs = read32(spibar + SPIBAR_HSFS); |
| 52 | hsfs |= SPIBAR_HSFS_FLOCKDN; |
| 53 | write32(spibar + SPIBAR_HSFS, hsfs); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 54 | |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 55 | /*TCO Lock down */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 56 | tcobase = pmc_tco_regs(); |
| 57 | tcocnt = inw(tcobase + TCO1_CNT); |
| 58 | tcocnt |= TCO_LOCK; |
| 59 | outw(tcocnt, tcobase + TCO1_CNT); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 60 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 61 | /* Lock down ABASE and sleep stretching policy */ |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 62 | dev = PCH_DEV_PMC; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 63 | reg32 = pci_read_config32(dev, GEN_PMCON_B); |
| 64 | reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); |
| 65 | pci_write_config32(dev, GEN_PMCON_B, reg32); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 66 | |
| 67 | /* PMSYNC */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 68 | pmcbase = pmc_mmio_regs(); |
| 69 | pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); |
| 70 | pmsyncreg |= PMSYNC_LOCK; |
| 71 | write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); |
| 72 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 73 | |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 74 | static void soc_lockdown(void) |
| 75 | { |
| 76 | u8 reg8; |
| 77 | device_t dev; |
| 78 | const struct device *dev1 = dev_find_slot(0, PCH_DEVFN_LPC); |
| 79 | const struct soc_intel_skylake_config *config = dev1->chip_info; |
| 80 | |
| 81 | /* Global SMI Lock */ |
| 82 | if (config->LockDownConfigGlobalSmi == 0) { |
| 83 | dev = PCH_DEV_PMC; |
| 84 | reg8 = pci_read_config8(dev, GEN_PMCON_A); |
| 85 | reg8 |= SMI_LOCK; |
| 86 | pci_write_config8(dev, GEN_PMCON_A, reg8); |
| 87 | } |
| 88 | |
| 89 | /* Bios Interface Lock */ |
| 90 | if (config->LockDownConfigBiosInterface == 0) { |
| 91 | pci_write_config8(PCH_DEV_LPC, BIOS_CNTL, |
| 92 | pci_read_config8(PCH_DEV_LPC, |
| 93 | BIOS_CNTL) | LPC_BC_BILD); |
| 94 | /* Reads back for posted write to take effect */ |
| 95 | pci_read_config8(PCH_DEV_LPC, BIOS_CNTL); |
| 96 | pci_write_config32(PCH_DEV_SPI, SPIBAR_BIOS_CNTL, |
| 97 | pci_read_config32(PCH_DEV_SPI, |
| 98 | SPIBAR_BIOS_CNTL) | |
| 99 | SPIBAR_BC_BILD); |
| 100 | /* Reads back for posted write to take effect */ |
| 101 | pci_read_config32(PCH_DEV_SPI, SPIBAR_BIOS_CNTL); |
| 102 | /* GCS reg of DMI */ |
| 103 | pcr_andthenor8(PID_DMI, R_PCH_PCR_DMI_GCS, 0xFF, |
| 104 | B_PCH_PCR_DMI_GCS_BILD); |
| 105 | } |
| 106 | |
| 107 | /* Bios Lock */ |
| 108 | if (config->LockDownConfigBiosLock == 0) { |
| 109 | pci_write_config8(PCH_DEV_LPC, BIOS_CNTL, |
| 110 | pci_read_config8(PCH_DEV_LPC, |
| 111 | BIOS_CNTL) | LPC_BC_LE); |
| 112 | pci_write_config8(PCH_DEV_SPI, BIOS_CNTL, |
| 113 | pci_read_config8(PCH_DEV_SPI, |
| 114 | BIOS_CNTL) | SPIBAR_BC_LE); |
| 115 | } |
| 116 | |
| 117 | /* SPIEiss */ |
| 118 | if (config->LockDownConfigSpiEiss == 0) { |
| 119 | pci_write_config8(PCH_DEV_LPC, BIOS_CNTL, |
| 120 | pci_read_config8(PCH_DEV_LPC, |
| 121 | BIOS_CNTL) | LPC_BC_EISS); |
| 122 | pci_write_config8(PCH_DEV_SPI, BIOS_CNTL, |
| 123 | pci_read_config8(PCH_DEV_SPI, |
| 124 | SPIBAR_BIOS_CNTL) | |
| 125 | SPIBAR_BC_EISS); |
| 126 | } |
| 127 | } |
| 128 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 129 | static void soc_finalize(void *unused) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 130 | { |
| 131 | printk(BIOS_DEBUG, "Finalizing chipset.\n"); |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 132 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 133 | pch_finalize_script(); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 134 | |
Rizwan Qureshi | e64f794 | 2015-11-19 16:01:54 +0530 | [diff] [blame] | 135 | soc_lockdown(); |
| 136 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 137 | /* Indicate finalize step with post code */ |
| 138 | post_code(POST_OS_BOOT); |
| 139 | } |
| 140 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 141 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); |
| 142 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); |