Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2013 Google Inc. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but without any warranty; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /* This file is derived from the flashrom project. */ |
| 24 | #include <stdint.h> |
| 25 | #include <stdlib.h> |
| 26 | #include <string.h> |
| 27 | #include <bootstate.h> |
| 28 | #include <delay.h> |
| 29 | #include <arch/io.h> |
| 30 | #include <console/console.h> |
| 31 | #include <device/pci_ids.h> |
| 32 | #include <spi_flash.h> |
| 33 | |
| 34 | #include <soc/lpc.h> |
| 35 | #include <soc/pci_devs.h> |
| 36 | |
| 37 | #ifdef __SMM__ |
| 38 | #define pci_read_config_byte(dev, reg, targ)\ |
| 39 | *(targ) = pci_read_config8(dev, reg) |
| 40 | #define pci_read_config_word(dev, reg, targ)\ |
| 41 | *(targ) = pci_read_config16(dev, reg) |
| 42 | #define pci_read_config_dword(dev, reg, targ)\ |
| 43 | *(targ) = pci_read_config32(dev, reg) |
| 44 | #define pci_write_config_byte(dev, reg, val)\ |
| 45 | pci_write_config8(dev, reg, val) |
| 46 | #define pci_write_config_word(dev, reg, val)\ |
| 47 | pci_write_config16(dev, reg, val) |
| 48 | #define pci_write_config_dword(dev, reg, val)\ |
| 49 | pci_write_config32(dev, reg, val) |
| 50 | #else /* !__SMM__ */ |
| 51 | #include <device/device.h> |
| 52 | #include <device/pci.h> |
| 53 | #define pci_read_config_byte(dev, reg, targ)\ |
| 54 | *(targ) = pci_read_config8(dev, reg) |
| 55 | #define pci_read_config_word(dev, reg, targ)\ |
| 56 | *(targ) = pci_read_config16(dev, reg) |
| 57 | #define pci_read_config_dword(dev, reg, targ)\ |
| 58 | *(targ) = pci_read_config32(dev, reg) |
| 59 | #define pci_write_config_byte(dev, reg, val)\ |
| 60 | pci_write_config8(dev, reg, val) |
| 61 | #define pci_write_config_word(dev, reg, val)\ |
| 62 | pci_write_config16(dev, reg, val) |
| 63 | #define pci_write_config_dword(dev, reg, val)\ |
| 64 | pci_write_config32(dev, reg, val) |
| 65 | #endif /* !__SMM__ */ |
| 66 | |
| 67 | typedef struct spi_slave ich_spi_slave; |
| 68 | |
| 69 | static int ichspi_lock = 0; |
| 70 | |
| 71 | typedef struct ich9_spi_regs { |
| 72 | uint32_t bfpr; |
| 73 | uint16_t hsfs; |
| 74 | uint16_t hsfc; |
| 75 | uint32_t faddr; |
| 76 | uint32_t _reserved0; |
| 77 | uint32_t fdata[16]; |
| 78 | uint32_t frap; |
| 79 | uint32_t freg[5]; |
| 80 | uint32_t _reserved1[3]; |
| 81 | uint32_t pr[5]; |
| 82 | uint32_t _reserved2[2]; |
| 83 | uint8_t ssfs; |
| 84 | uint8_t ssfc[3]; |
| 85 | uint16_t preop; |
| 86 | uint16_t optype; |
| 87 | uint8_t opmenu[8]; |
| 88 | uint32_t bbar; |
| 89 | uint8_t _reserved3[12]; |
| 90 | uint32_t fdoc; |
| 91 | uint32_t fdod; |
| 92 | uint8_t _reserved4[8]; |
| 93 | uint32_t afc; |
| 94 | uint32_t lvscc; |
| 95 | uint32_t uvscc; |
| 96 | uint8_t _reserved5[4]; |
| 97 | uint32_t fpb; |
| 98 | uint8_t _reserved6[28]; |
| 99 | uint32_t srdl; |
| 100 | uint32_t srdc; |
| 101 | uint32_t srd; |
| 102 | } __attribute__((packed)) ich9_spi_regs; |
| 103 | |
| 104 | typedef struct ich_spi_controller { |
| 105 | int locked; |
| 106 | |
| 107 | uint8_t *opmenu; |
| 108 | int menubytes; |
| 109 | uint16_t *preop; |
| 110 | uint16_t *optype; |
| 111 | uint32_t *addr; |
| 112 | uint8_t *data; |
| 113 | unsigned databytes; |
| 114 | uint8_t *status; |
| 115 | uint16_t *control; |
| 116 | uint32_t *bbar; |
| 117 | } ich_spi_controller; |
| 118 | |
| 119 | static ich_spi_controller cntlr; |
| 120 | |
| 121 | enum { |
| 122 | SPIS_SCIP = 0x0001, |
| 123 | SPIS_GRANT = 0x0002, |
| 124 | SPIS_CDS = 0x0004, |
| 125 | SPIS_FCERR = 0x0008, |
| 126 | SSFS_AEL = 0x0010, |
| 127 | SPIS_LOCK = 0x8000, |
| 128 | SPIS_RESERVED_MASK = 0x7ff0, |
| 129 | SSFS_RESERVED_MASK = 0x7fe2 |
| 130 | }; |
| 131 | |
| 132 | enum { |
| 133 | SPIC_SCGO = 0x000002, |
| 134 | SPIC_ACS = 0x000004, |
| 135 | SPIC_SPOP = 0x000008, |
| 136 | SPIC_DBC = 0x003f00, |
| 137 | SPIC_DS = 0x004000, |
| 138 | SPIC_SME = 0x008000, |
| 139 | SSFC_SCF_MASK = 0x070000, |
| 140 | SSFC_RESERVED = 0xf80000 |
| 141 | }; |
| 142 | |
| 143 | enum { |
| 144 | HSFS_FDONE = 0x0001, |
| 145 | HSFS_FCERR = 0x0002, |
| 146 | HSFS_AEL = 0x0004, |
| 147 | HSFS_BERASE_MASK = 0x0018, |
| 148 | HSFS_BERASE_SHIFT = 3, |
| 149 | HSFS_SCIP = 0x0020, |
| 150 | HSFS_FDOPSS = 0x2000, |
| 151 | HSFS_FDV = 0x4000, |
| 152 | HSFS_FLOCKDN = 0x8000 |
| 153 | }; |
| 154 | |
| 155 | enum { |
| 156 | HSFC_FGO = 0x0001, |
| 157 | HSFC_FCYCLE_MASK = 0x0006, |
| 158 | HSFC_FCYCLE_SHIFT = 1, |
| 159 | HSFC_FDBC_MASK = 0x3f00, |
| 160 | HSFC_FDBC_SHIFT = 8, |
| 161 | HSFC_FSMIE = 0x8000 |
| 162 | }; |
| 163 | |
| 164 | enum { |
| 165 | SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, |
| 166 | SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, |
| 167 | SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, |
| 168 | SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 |
| 169 | }; |
| 170 | |
| 171 | #if CONFIG_DEBUG_SPI_FLASH |
| 172 | |
| 173 | static u8 readb_(const void *addr) |
| 174 | { |
| 175 | u8 v = read8((unsigned long)addr); |
| 176 | printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", |
| 177 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 178 | return v; |
| 179 | } |
| 180 | |
| 181 | static u16 readw_(const void *addr) |
| 182 | { |
| 183 | u16 v = read16((unsigned long)addr); |
| 184 | printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", |
| 185 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 186 | return v; |
| 187 | } |
| 188 | |
| 189 | static u32 readl_(const void *addr) |
| 190 | { |
| 191 | u32 v = read32((unsigned long)addr); |
| 192 | printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", |
| 193 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 194 | return v; |
| 195 | } |
| 196 | |
| 197 | static void writeb_(u8 b, const void *addr) |
| 198 | { |
| 199 | write8(addr, b); |
| 200 | printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", |
| 201 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 202 | } |
| 203 | |
| 204 | static void writew_(u16 b, const void *addr) |
| 205 | { |
| 206 | write16(addr, b); |
| 207 | printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", |
| 208 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 209 | } |
| 210 | |
| 211 | static void writel_(u32 b, const void *addr) |
| 212 | { |
| 213 | write32(addr, b); |
| 214 | printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", |
| 215 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 216 | } |
| 217 | |
| 218 | #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ |
| 219 | |
| 220 | #define readb_(a) read8(a) |
| 221 | #define readw_(a) read16(a) |
| 222 | #define readl_(a) read32(a) |
| 223 | #define writeb_(val, addr) write8(addr, val) |
| 224 | #define writew_(val, addr) write16(addr, val) |
| 225 | #define writel_(val, addr) write32(addr, val) |
| 226 | |
| 227 | #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ |
| 228 | |
| 229 | static void write_reg(const void *value, void *dest, uint32_t size) |
| 230 | { |
| 231 | const uint8_t *bvalue = value; |
| 232 | uint8_t *bdest = dest; |
| 233 | |
| 234 | while (size >= 4) { |
| 235 | writel_(*(const uint32_t *)bvalue, bdest); |
| 236 | bdest += 4; bvalue += 4; size -= 4; |
| 237 | } |
| 238 | while (size) { |
| 239 | writeb_(*bvalue, bdest); |
| 240 | bdest++; bvalue++; size--; |
| 241 | } |
| 242 | } |
| 243 | |
| 244 | static void read_reg(const void *src, void *value, uint32_t size) |
| 245 | { |
| 246 | const uint8_t *bsrc = src; |
| 247 | uint8_t *bvalue = value; |
| 248 | |
| 249 | while (size >= 4) { |
| 250 | *(uint32_t *)bvalue = readl_(bsrc); |
| 251 | bsrc += 4; bvalue += 4; size -= 4; |
| 252 | } |
| 253 | while (size) { |
| 254 | *bvalue = readb_(bsrc); |
| 255 | bsrc++; bvalue++; size--; |
| 256 | } |
| 257 | } |
| 258 | |
| 259 | static void ich_set_bbar(uint32_t minaddr) |
| 260 | { |
| 261 | const uint32_t bbar_mask = 0x00ffff00; |
| 262 | uint32_t ichspi_bbar; |
| 263 | |
| 264 | minaddr &= bbar_mask; |
| 265 | ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; |
| 266 | ichspi_bbar |= minaddr; |
| 267 | writel_(ichspi_bbar, cntlr.bbar); |
| 268 | } |
| 269 | |
| 270 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) |
| 271 | { |
| 272 | ich_spi_slave *slave = malloc(sizeof(*slave)); |
| 273 | |
| 274 | if (!slave) { |
| 275 | printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); |
| 276 | return NULL; |
| 277 | } |
| 278 | |
| 279 | memset(slave, 0, sizeof(*slave)); |
| 280 | |
| 281 | slave->bus = bus; |
| 282 | slave->cs = cs; |
| 283 | return slave; |
| 284 | } |
| 285 | |
| 286 | static ich9_spi_regs *spi_regs(void) |
| 287 | { |
| 288 | device_t dev; |
| 289 | uint32_t sbase; |
| 290 | |
| 291 | #ifdef __SMM__ |
| 292 | dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); |
| 293 | #else |
| 294 | dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); |
| 295 | #endif |
| 296 | pci_read_config_dword(dev, SBASE, &sbase); |
| 297 | sbase &= ~0x1ff; |
| 298 | |
| 299 | return (void *)sbase; |
| 300 | } |
| 301 | |
| 302 | void spi_init(void) |
| 303 | { |
| 304 | ich9_spi_regs *ich9_spi = spi_regs(); |
| 305 | |
| 306 | ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; |
| 307 | cntlr.opmenu = ich9_spi->opmenu; |
| 308 | cntlr.menubytes = sizeof(ich9_spi->opmenu); |
| 309 | cntlr.optype = &ich9_spi->optype; |
| 310 | cntlr.addr = &ich9_spi->faddr; |
| 311 | cntlr.data = (uint8_t *)ich9_spi->fdata; |
| 312 | cntlr.databytes = sizeof(ich9_spi->fdata); |
| 313 | cntlr.status = &ich9_spi->ssfs; |
| 314 | cntlr.control = (uint16_t *)ich9_spi->ssfc; |
| 315 | cntlr.bbar = &ich9_spi->bbar; |
| 316 | cntlr.preop = &ich9_spi->preop; |
| 317 | ich_set_bbar(0); |
| 318 | } |
| 319 | |
| 320 | #ifndef __SMM__ |
| 321 | static void spi_init_cb(void *unused) |
| 322 | { |
| 323 | spi_init(); |
| 324 | } |
| 325 | |
| 326 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); |
| 327 | #endif |
| 328 | |
| 329 | int spi_claim_bus(struct spi_slave *slave) |
| 330 | { |
| 331 | /* Handled by ICH automatically. */ |
| 332 | return 0; |
| 333 | } |
| 334 | |
| 335 | void spi_release_bus(struct spi_slave *slave) |
| 336 | { |
| 337 | /* Handled by ICH automatically. */ |
| 338 | } |
| 339 | |
| 340 | typedef struct spi_transaction { |
| 341 | const uint8_t *out; |
| 342 | uint32_t bytesout; |
| 343 | uint8_t *in; |
| 344 | uint32_t bytesin; |
| 345 | uint8_t type; |
| 346 | uint8_t opcode; |
| 347 | uint32_t offset; |
| 348 | } spi_transaction; |
| 349 | |
| 350 | static inline void spi_use_out(spi_transaction *trans, unsigned bytes) |
| 351 | { |
| 352 | trans->out += bytes; |
| 353 | trans->bytesout -= bytes; |
| 354 | } |
| 355 | |
| 356 | static inline void spi_use_in(spi_transaction *trans, unsigned bytes) |
| 357 | { |
| 358 | trans->in += bytes; |
| 359 | trans->bytesin -= bytes; |
| 360 | } |
| 361 | |
| 362 | static void spi_setup_type(spi_transaction *trans) |
| 363 | { |
| 364 | trans->type = 0xFF; |
| 365 | |
| 366 | /* Try to guess spi type from read/write sizes. */ |
| 367 | if (trans->bytesin == 0) { |
| 368 | if (trans->bytesout > 4) |
| 369 | /* |
| 370 | * If bytesin = 0 and bytesout > 4, we presume this is |
| 371 | * a write data operation, which is accompanied by an |
| 372 | * address. |
| 373 | */ |
| 374 | trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; |
| 375 | else |
| 376 | trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; |
| 377 | return; |
| 378 | } |
| 379 | |
| 380 | if (trans->bytesout == 1) { /* and bytesin is > 0 */ |
| 381 | trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; |
| 382 | return; |
| 383 | } |
| 384 | |
| 385 | if (trans->bytesout == 4) { /* and bytesin is > 0 */ |
| 386 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 387 | } |
| 388 | |
| 389 | /* Fast read command is called with 5 bytes instead of 4 */ |
| 390 | if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { |
| 391 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 392 | --trans->bytesout; |
| 393 | } |
| 394 | } |
| 395 | |
| 396 | static int spi_setup_opcode(spi_transaction *trans) |
| 397 | { |
| 398 | uint16_t optypes; |
| 399 | uint8_t opmenu[cntlr.menubytes]; |
| 400 | |
| 401 | trans->opcode = trans->out[0]; |
| 402 | spi_use_out(trans, 1); |
| 403 | if (!ichspi_lock) { |
| 404 | /* The lock is off, so just use index 0. */ |
| 405 | writeb_(trans->opcode, cntlr.opmenu); |
| 406 | optypes = readw_(cntlr.optype); |
| 407 | optypes = (optypes & 0xfffc) | (trans->type & 0x3); |
| 408 | writew_(optypes, cntlr.optype); |
| 409 | return 0; |
| 410 | } else { |
| 411 | /* The lock is on. See if what we need is on the menu. */ |
| 412 | uint8_t optype; |
| 413 | uint16_t opcode_index; |
| 414 | |
| 415 | /* Write Enable is handled as atomic prefix */ |
| 416 | if (trans->opcode == SPI_OPCODE_WREN) |
| 417 | return 0; |
| 418 | |
| 419 | read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); |
| 420 | for (opcode_index = 0; opcode_index < cntlr.menubytes; |
| 421 | opcode_index++) { |
| 422 | if (opmenu[opcode_index] == trans->opcode) |
| 423 | break; |
| 424 | } |
| 425 | |
| 426 | if (opcode_index == cntlr.menubytes) { |
| 427 | printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", |
| 428 | trans->opcode); |
| 429 | return -1; |
| 430 | } |
| 431 | |
| 432 | optypes = readw_(cntlr.optype); |
| 433 | optype = (optypes >> (opcode_index * 2)) & 0x3; |
| 434 | if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && |
| 435 | optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && |
| 436 | trans->bytesout >= 3) { |
| 437 | /* We guessed wrong earlier. Fix it up. */ |
| 438 | trans->type = optype; |
| 439 | } |
| 440 | if (optype != trans->type) { |
| 441 | printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", |
| 442 | optype); |
| 443 | return -1; |
| 444 | } |
| 445 | return opcode_index; |
| 446 | } |
| 447 | } |
| 448 | |
| 449 | static int spi_setup_offset(spi_transaction *trans) |
| 450 | { |
| 451 | /* Separate the SPI address and data. */ |
| 452 | switch (trans->type) { |
| 453 | case SPI_OPCODE_TYPE_READ_NO_ADDRESS: |
| 454 | case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: |
| 455 | return 0; |
| 456 | case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: |
| 457 | case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: |
| 458 | trans->offset = ((uint32_t)trans->out[0] << 16) | |
| 459 | ((uint32_t)trans->out[1] << 8) | |
| 460 | ((uint32_t)trans->out[2] << 0); |
| 461 | spi_use_out(trans, 3); |
| 462 | return 1; |
| 463 | default: |
| 464 | printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); |
| 465 | return -1; |
| 466 | } |
| 467 | } |
| 468 | |
| 469 | /* |
| 470 | * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set |
| 471 | * below is True) or 0. In case the wait was for the bit(s) to set - write |
| 472 | * those bits back, which would cause resetting them. |
| 473 | * |
| 474 | * Return the last read status value on success or -1 on failure. |
| 475 | */ |
| 476 | static int ich_status_poll(u16 bitmask, int wait_til_set) |
| 477 | { |
| 478 | int timeout = 40000; /* This will result in 400 ms */ |
| 479 | u16 status = 0; |
| 480 | |
| 481 | while (timeout--) { |
| 482 | status = readw_(cntlr.status); |
| 483 | if (wait_til_set ^ ((status & bitmask) == 0)) { |
| 484 | if (wait_til_set) |
| 485 | writew_((status & bitmask), cntlr.status); |
| 486 | return status; |
| 487 | } |
| 488 | udelay(10); |
| 489 | } |
| 490 | |
| 491 | printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", |
| 492 | status, bitmask); |
| 493 | return -1; |
| 494 | } |
| 495 | |
| 496 | unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) |
| 497 | { |
| 498 | return min(cntlr.databytes, buf_len); |
| 499 | } |
| 500 | |
| 501 | int spi_xfer(struct spi_slave *slave, const void *dout, |
| 502 | unsigned int bytesout, void *din, unsigned int bytesin) |
| 503 | { |
| 504 | uint16_t control; |
| 505 | int16_t opcode_index; |
| 506 | int with_address; |
| 507 | int status; |
| 508 | |
| 509 | spi_transaction trans = { |
| 510 | dout, bytesout, |
| 511 | din, bytesin, |
| 512 | 0xff, 0xff, 0 |
| 513 | }; |
| 514 | |
| 515 | /* There has to always at least be an opcode. */ |
| 516 | if (!bytesout || !dout) { |
| 517 | printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); |
| 518 | return -1; |
| 519 | } |
| 520 | /* Make sure if we read something we have a place to put it. */ |
| 521 | if (bytesin != 0 && !din) { |
| 522 | printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); |
| 523 | return -1; |
| 524 | } |
| 525 | |
| 526 | if (ich_status_poll(SPIS_SCIP, 0) == -1) |
| 527 | return -1; |
| 528 | |
| 529 | writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); |
| 530 | |
| 531 | spi_setup_type(&trans); |
| 532 | if ((opcode_index = spi_setup_opcode(&trans)) < 0) |
| 533 | return -1; |
| 534 | if ((with_address = spi_setup_offset(&trans)) < 0) |
| 535 | return -1; |
| 536 | |
| 537 | if (trans.opcode == SPI_OPCODE_WREN) { |
| 538 | /* |
| 539 | * Treat Write Enable as Atomic Pre-Op if possible |
| 540 | * in order to prevent the Management Engine from |
| 541 | * issuing a transaction between WREN and DATA. |
| 542 | */ |
| 543 | if (!ichspi_lock) |
| 544 | writew_(trans.opcode, cntlr.preop); |
| 545 | return 0; |
| 546 | } |
| 547 | |
| 548 | /* Preset control fields */ |
| 549 | control = SPIC_SCGO | ((opcode_index & 0x07) << 4); |
| 550 | |
| 551 | /* Issue atomic preop cycle if needed */ |
| 552 | if (readw_(cntlr.preop)) |
| 553 | control |= SPIC_ACS; |
| 554 | |
| 555 | if (!trans.bytesout && !trans.bytesin) { |
| 556 | /* SPI addresses are 24 bit only */ |
| 557 | if (with_address) |
| 558 | writel_(trans.offset & 0x00FFFFFF, cntlr.addr); |
| 559 | |
| 560 | /* |
| 561 | * This is a 'no data' command (like Write Enable), its |
| 562 | * bytesout size was 1, decremented to zero while executing |
| 563 | * spi_setup_opcode() above. Tell the chip to send the |
| 564 | * command. |
| 565 | */ |
| 566 | writew_(control, cntlr.control); |
| 567 | |
| 568 | /* wait for the result */ |
| 569 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 570 | if (status == -1) |
| 571 | return -1; |
| 572 | |
| 573 | if (status & SPIS_FCERR) { |
| 574 | printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); |
| 575 | return -1; |
| 576 | } |
| 577 | |
| 578 | return 0; |
| 579 | } |
| 580 | |
| 581 | /* |
| 582 | * Check if this is a write command attempting to transfer more bytes |
| 583 | * than the controller can handle. Iterations for writes are not |
| 584 | * supported here because each SPI write command needs to be preceded |
| 585 | * and followed by other SPI commands, and this sequence is controlled |
| 586 | * by the SPI chip driver. |
| 587 | */ |
| 588 | if (trans.bytesout > cntlr.databytes) { |
| 589 | printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" |
| 590 | " spi_crop_chunk()?\n"); |
| 591 | return -1; |
| 592 | } |
| 593 | |
| 594 | /* |
| 595 | * Read or write up to databytes bytes at a time until everything has |
| 596 | * been sent. |
| 597 | */ |
| 598 | while (trans.bytesout || trans.bytesin) { |
| 599 | uint32_t data_length; |
| 600 | |
| 601 | /* SPI addresses are 24 bit only */ |
| 602 | writel_(trans.offset & 0x00FFFFFF, cntlr.addr); |
| 603 | |
| 604 | if (trans.bytesout) |
| 605 | data_length = min(trans.bytesout, cntlr.databytes); |
| 606 | else |
| 607 | data_length = min(trans.bytesin, cntlr.databytes); |
| 608 | |
| 609 | /* Program data into FDATA0 to N */ |
| 610 | if (trans.bytesout) { |
| 611 | write_reg(trans.out, cntlr.data, data_length); |
| 612 | spi_use_out(&trans, data_length); |
| 613 | if (with_address) |
| 614 | trans.offset += data_length; |
| 615 | } |
| 616 | |
| 617 | /* Add proper control fields' values */ |
| 618 | control &= ~((cntlr.databytes - 1) << 8); |
| 619 | control |= SPIC_DS; |
| 620 | control |= (data_length - 1) << 8; |
| 621 | |
| 622 | /* write it */ |
| 623 | writew_(control, cntlr.control); |
| 624 | |
| 625 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
| 626 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 627 | if (status == -1) |
| 628 | return -1; |
| 629 | |
| 630 | if (status & SPIS_FCERR) { |
| 631 | printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); |
| 632 | return -1; |
| 633 | } |
| 634 | |
| 635 | if (trans.bytesin) { |
| 636 | read_reg(cntlr.data, trans.in, data_length); |
| 637 | spi_use_in(&trans, data_length); |
| 638 | if (with_address) |
| 639 | trans.offset += data_length; |
| 640 | } |
| 641 | } |
| 642 | |
| 643 | /* Clear atomic preop now that xfer is done */ |
| 644 | writew_(0, cntlr.preop); |
| 645 | |
| 646 | return 0; |
| 647 | } |