Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 20 | * MA 02110-1301 USA |
| 21 | */ |
| 22 | |
| 23 | #include <types.h> |
| 24 | #include <console/console.h> |
| 25 | #include <arch/acpi.h> |
| 26 | #include <arch/acpigen.h> |
| 27 | #include <arch/cpu.h> |
| 28 | #include <cpu/x86/msr.h> |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 29 | #include <cpu/x86/lapic.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 30 | #include <cpu/intel/acpi.h> |
| 31 | #include <cpu/intel/speedstep.h> |
| 32 | #include <cpu/intel/turbo.h> |
| 33 | #include <device/device.h> |
| 34 | #include <device/pci.h> |
| 35 | #include "model_206ax.h" |
| 36 | #include "chip.h" |
| 37 | |
| 38 | static int get_cores_per_package(void) |
| 39 | { |
| 40 | struct cpuinfo_x86 c; |
| 41 | struct cpuid_result result; |
| 42 | int cores = 1; |
| 43 | |
| 44 | get_fms(&c, cpuid_eax(1)); |
| 45 | if (c.x86 != 6) |
| 46 | return 1; |
| 47 | |
Stefan Reinauer | bb31f3a | 2012-05-11 16:30:54 -0700 | [diff] [blame] | 48 | result = cpuid_ext(0xb, 1); |
| 49 | cores = result.ebx & 0xff; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 50 | |
| 51 | return cores; |
| 52 | } |
| 53 | |
| 54 | static int generate_cstate_entries(acpi_cstate_t *cstates, |
| 55 | int c1, int c2, int c3) |
| 56 | { |
| 57 | int length, cstate_count = 0; |
| 58 | |
| 59 | /* Count number of active C-states */ |
| 60 | if (c1 > 0) |
| 61 | ++cstate_count; |
| 62 | if (c2 > 0) |
| 63 | ++cstate_count; |
| 64 | if (c3 > 0) |
| 65 | ++cstate_count; |
| 66 | if (!cstate_count) |
| 67 | return 0; |
| 68 | |
| 69 | length = acpigen_write_package(cstate_count + 1); |
| 70 | length += acpigen_write_byte(cstate_count); |
| 71 | |
| 72 | /* Add an entry if the level is enabled */ |
Stefan Reinauer | c31384e | 2012-04-27 23:13:39 +0200 | [diff] [blame] | 73 | if (c1 > 0) { |
| 74 | cstates[c1].ctype = 1; |
| 75 | length += acpigen_write_CST_package_entry(&cstates[c1]); |
| 76 | } |
| 77 | if (c2 > 0) { |
| 78 | cstates[c2].ctype = 2; |
| 79 | length += acpigen_write_CST_package_entry(&cstates[c2]); |
| 80 | } |
| 81 | if (c3 > 0) { |
Duncan Laurie | b38e0c3 | 2012-06-20 14:38:53 -0700 | [diff] [blame] | 82 | cstates[c3].ctype = 3; |
Stefan Reinauer | c31384e | 2012-04-27 23:13:39 +0200 | [diff] [blame] | 83 | length += acpigen_write_CST_package_entry(&cstates[c3]); |
| 84 | } |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 85 | |
| 86 | acpigen_patch_len(length - 1); |
| 87 | return length; |
| 88 | } |
| 89 | |
| 90 | static int generate_C_state_entries(void) |
| 91 | { |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 92 | struct cpu_driver *cpu; |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 93 | struct device *cpu_dev; |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 94 | int len, lenif; |
| 95 | device_t lapic; |
| 96 | struct cpu_intel_model_206ax_config *conf = NULL; |
| 97 | |
| 98 | /* Find the SpeedStep CPU in the device tree using magic APIC ID */ |
| 99 | lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
| 100 | if (!lapic) |
| 101 | return 0; |
| 102 | conf = lapic->chip_info; |
| 103 | if (!conf) |
| 104 | return 0; |
| 105 | |
| 106 | /* Find CPU map of supported C-states */ |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 107 | cpu_dev = dev_find_lapic(lapicid()); |
| 108 | if (!cpu_dev) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 109 | return 0; |
Sven Schnelle | 042c146 | 2012-06-17 10:32:55 +0200 | [diff] [blame] | 110 | cpu = find_cpu_driver(cpu_dev); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 111 | if (!cpu || !cpu->cstates) |
| 112 | return 0; |
| 113 | |
| 114 | len = acpigen_emit_byte(0x14); /* MethodOp */ |
| 115 | len += acpigen_write_len_f(); /* PkgLength */ |
| 116 | len += acpigen_emit_namestring("_CST"); |
| 117 | len += acpigen_emit_byte(0x00); /* No Arguments */ |
| 118 | |
| 119 | /* If running on AC power */ |
| 120 | len += acpigen_emit_byte(0xa0); /* IfOp */ |
| 121 | lenif = acpigen_write_len_f(); /* PkgLength */ |
| 122 | lenif += acpigen_emit_namestring("PWRS"); |
| 123 | lenif += acpigen_emit_byte(0xa4); /* ReturnOp */ |
| 124 | lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower, |
| 125 | conf->c2_acpower, conf->c3_acpower); |
| 126 | acpigen_patch_len(lenif - 1); |
| 127 | len += lenif; |
| 128 | |
| 129 | /* Else on battery power */ |
| 130 | len += acpigen_emit_byte(0xa4); /* ReturnOp */ |
| 131 | len += generate_cstate_entries(cpu->cstates, conf->c1_battery, |
| 132 | conf->c2_battery, conf->c3_battery); |
| 133 | acpigen_patch_len(len - 1); |
| 134 | return len; |
| 135 | } |
| 136 | |
| 137 | static acpi_tstate_t tss_table_fine[] = { |
| 138 | { 100, 1000, 0, 0x00, 0 }, |
| 139 | { 94, 940, 0, 0x1f, 0 }, |
| 140 | { 88, 880, 0, 0x1e, 0 }, |
| 141 | { 82, 820, 0, 0x1d, 0 }, |
| 142 | { 75, 760, 0, 0x1c, 0 }, |
| 143 | { 69, 700, 0, 0x1b, 0 }, |
| 144 | { 63, 640, 0, 0x1a, 0 }, |
| 145 | { 57, 580, 0, 0x19, 0 }, |
| 146 | { 50, 520, 0, 0x18, 0 }, |
| 147 | { 44, 460, 0, 0x17, 0 }, |
| 148 | { 38, 400, 0, 0x16, 0 }, |
| 149 | { 32, 340, 0, 0x15, 0 }, |
| 150 | { 25, 280, 0, 0x14, 0 }, |
| 151 | { 19, 220, 0, 0x13, 0 }, |
| 152 | { 13, 160, 0, 0x12, 0 }, |
| 153 | }; |
| 154 | |
| 155 | static acpi_tstate_t tss_table_coarse[] = { |
| 156 | { 100, 1000, 0, 0x00, 0 }, |
| 157 | { 88, 875, 0, 0x1f, 0 }, |
| 158 | { 75, 750, 0, 0x1e, 0 }, |
| 159 | { 63, 625, 0, 0x1d, 0 }, |
| 160 | { 50, 500, 0, 0x1c, 0 }, |
| 161 | { 38, 375, 0, 0x1b, 0 }, |
| 162 | { 25, 250, 0, 0x1a, 0 }, |
| 163 | { 13, 125, 0, 0x19, 0 }, |
| 164 | }; |
| 165 | |
| 166 | static int generate_T_state_entries(int core, int cores_per_package) |
| 167 | { |
| 168 | int len; |
| 169 | |
| 170 | /* Indicate SW_ALL coordination for T-states */ |
| 171 | len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
| 172 | |
| 173 | /* Indicate FFixedHW so OS will use MSR */ |
| 174 | len += acpigen_write_empty_PTC(); |
| 175 | |
| 176 | /* Set a T-state limit that can be modified in NVS */ |
| 177 | len += acpigen_write_TPC("\\TLVL"); |
| 178 | |
| 179 | /* |
| 180 | * CPUID.(EAX=6):EAX[5] indicates support |
| 181 | * for extended throttle levels. |
| 182 | */ |
| 183 | if (cpuid_eax(6) & (1 << 5)) |
| 184 | len += acpigen_write_TSS_package( |
| 185 | ARRAY_SIZE(tss_table_fine), tss_table_fine); |
| 186 | else |
| 187 | len += acpigen_write_TSS_package( |
| 188 | ARRAY_SIZE(tss_table_coarse), tss_table_coarse); |
| 189 | |
| 190 | return len; |
| 191 | } |
| 192 | |
| 193 | static int calculate_power(int tdp, int p1_ratio, int ratio) |
| 194 | { |
| 195 | u32 m; |
| 196 | u32 power; |
| 197 | |
| 198 | /* |
| 199 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 200 | * |
| 201 | * Power = (ratio / p1_ratio) * m * tdp |
| 202 | */ |
| 203 | |
| 204 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 205 | m = (m * m) / 1000; |
| 206 | |
| 207 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 208 | power *= (m / 100) * (tdp / 1000); |
| 209 | power /= 1000; |
| 210 | |
| 211 | return (int)power; |
| 212 | } |
| 213 | |
| 214 | static int generate_P_state_entries(int core, int cores_per_package) |
| 215 | { |
| 216 | int len, len_pss; |
| 217 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 218 | int coord_type, power_max, power_unit, num_entries; |
| 219 | int ratio, power, clock, clock_max; |
| 220 | msr_t msr; |
| 221 | |
| 222 | /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ |
| 223 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 224 | if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) |
| 225 | coord_type = SW_ANY; |
| 226 | else |
| 227 | coord_type = HW_ALL; |
| 228 | |
| 229 | /* Get bus ratio limits and calculate clock speeds */ |
| 230 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 231 | ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ |
| 232 | ratio_max = (msr.lo >> 8) & 0xff; /* Max Non-Turbo Ratio */ |
| 233 | clock_max = ratio_max * SANDYBRIDGE_BCLK; |
| 234 | |
| 235 | /* Calculate CPU TDP in mW */ |
| 236 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 237 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 238 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 239 | power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; |
| 240 | |
| 241 | /* Write _PCT indicating use of FFixedHW */ |
| 242 | len = acpigen_write_empty_PCT(); |
| 243 | |
| 244 | /* Write _PPC with no limit on supported P-state */ |
| 245 | len += acpigen_write_PPC(0); |
| 246 | |
| 247 | /* Write PSD indicating configured coordination type */ |
| 248 | len += acpigen_write_PSD_package(core, cores_per_package, coord_type); |
| 249 | |
| 250 | /* Add P-state entries in _PSS table */ |
| 251 | len += acpigen_write_name("_PSS"); |
| 252 | |
| 253 | /* Determine ratio points */ |
| 254 | ratio_step = PSS_RATIO_STEP; |
| 255 | num_entries = (ratio_max - ratio_min) / ratio_step; |
| 256 | while (num_entries > PSS_MAX_ENTRIES-1) { |
| 257 | ratio_step <<= 1; |
| 258 | num_entries >>= 1; |
| 259 | } |
| 260 | |
| 261 | /* P[T] is Turbo state if enabled */ |
| 262 | if (get_turbo_state() == TURBO_ENABLED) { |
| 263 | /* _PSS package count including Turbo */ |
| 264 | len_pss = acpigen_write_package(num_entries + 2); |
| 265 | |
| 266 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 267 | ratio_turbo = msr.lo & 0xff; |
| 268 | |
| 269 | /* Add entry for Turbo ratio */ |
| 270 | len_pss += acpigen_write_PSS_package( |
| 271 | clock_max + 1, /*MHz*/ |
| 272 | power_max, /*mW*/ |
| 273 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 274 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 275 | ratio_turbo << 8, /*control*/ |
| 276 | ratio_turbo << 8); /*status*/ |
| 277 | } else { |
| 278 | /* _PSS package count without Turbo */ |
| 279 | len_pss = acpigen_write_package(num_entries + 1); |
| 280 | } |
| 281 | |
| 282 | /* First regular entry is max non-turbo ratio */ |
| 283 | len_pss += acpigen_write_PSS_package( |
| 284 | clock_max, /*MHz*/ |
| 285 | power_max, /*mW*/ |
| 286 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 287 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 288 | ratio_max << 8, /*control*/ |
| 289 | ratio_max << 8); /*status*/ |
| 290 | |
| 291 | /* Generate the remaining entries */ |
| 292 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 293 | ratio >= ratio_min; ratio -= ratio_step) { |
| 294 | |
| 295 | /* Calculate power at this ratio */ |
| 296 | power = calculate_power(power_max, ratio_max, ratio); |
| 297 | clock = ratio * SANDYBRIDGE_BCLK; |
| 298 | |
| 299 | len_pss += acpigen_write_PSS_package( |
| 300 | clock, /*MHz*/ |
| 301 | power, /*mW*/ |
| 302 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 303 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 304 | ratio << 8, /*control*/ |
| 305 | ratio << 8); /*status*/ |
| 306 | } |
| 307 | |
| 308 | /* Fix package length */ |
| 309 | len_pss--; |
| 310 | acpigen_patch_len(len_pss); |
| 311 | |
| 312 | return len + len_pss; |
| 313 | } |
| 314 | |
| 315 | void generate_cpu_entries(void) |
| 316 | { |
| 317 | int len_pr; |
| 318 | int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; |
| 319 | int totalcores = dev_count_cpu(); |
| 320 | int cores_per_package = get_cores_per_package(); |
| 321 | int numcpus = totalcores/cores_per_package; |
| 322 | |
| 323 | printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", |
| 324 | numcpus, cores_per_package); |
| 325 | |
| 326 | for (cpuID=1; cpuID <=numcpus; cpuID++) { |
| 327 | for (coreID=1; coreID<=cores_per_package; coreID++) { |
| 328 | if (coreID>1) { |
| 329 | pcontrol_blk = 0; |
| 330 | plen = 0; |
| 331 | } |
| 332 | |
| 333 | /* Generate processor \_PR.CPUx */ |
| 334 | len_pr = acpigen_write_processor( |
| 335 | (cpuID-1)*cores_per_package+coreID-1, |
| 336 | pcontrol_blk, plen); |
| 337 | |
| 338 | /* Generate P-state tables */ |
| 339 | len_pr += generate_P_state_entries( |
| 340 | cpuID-1, cores_per_package); |
| 341 | |
| 342 | /* Generate C-state tables */ |
| 343 | len_pr += generate_C_state_entries(); |
| 344 | |
| 345 | /* Generate T-state tables */ |
| 346 | len_pr += generate_T_state_entries( |
| 347 | cpuID-1, cores_per_package); |
| 348 | |
| 349 | len_pr--; |
| 350 | acpigen_patch_len(len_pr); |
| 351 | } |
| 352 | } |
| 353 | } |
| 354 | |
| 355 | struct chip_operations cpu_intel_model_206ax_ops = { |
| 356 | CHIP_NAME(CONFIG_CPU_MODEL_NAME) |
| 357 | }; |