Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include "i945.h" |
| 21 | #include "pcie_config.c" |
| 22 | |
| 23 | static int i945_silicon_revision(void) |
| 24 | { |
| 25 | return pci_read_config8(PCI_DEV(0, 0x00, 0), 8); |
| 26 | } |
| 27 | |
| 28 | static void i945_detect_chipset(void) |
| 29 | { |
| 30 | u8 reg8; |
| 31 | |
| 32 | printk_info("\r\n"); |
| 33 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; |
| 34 | switch (reg8) { |
| 35 | case 1: |
| 36 | printk_info("Mobile Intel(R) 945GM/GME Express"); |
| 37 | break; |
| 38 | case 2: |
| 39 | printk_info("Mobile Intel(R) 945GMS/GU Express"); |
| 40 | break; |
| 41 | case 3: |
| 42 | printk_info("Mobile Intel(R) 945PM Express"); |
| 43 | break; |
| 44 | case 5: |
| 45 | printk_info("Intel(R) 945GT Express"); |
| 46 | break; |
| 47 | case 6: |
| 48 | printk_info("Mobile Intel(R) 943/940GML Express"); |
| 49 | break; |
| 50 | default: |
| 51 | printk_info("Unknown (%02x)", reg8); /* Others reserved. */ |
| 52 | } |
| 53 | printk_info(" Chipset\r\n"); |
| 54 | |
| 55 | printk_debug("(G)MCH capable of up to FSB "); |
| 56 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5; |
| 57 | switch (reg8) { |
| 58 | case 2: |
| 59 | printk_debug("800 MHz"); /* According to 965 spec */ |
| 60 | break; |
| 61 | case 3: |
| 62 | printk_debug("667 MHz"); |
| 63 | break; |
| 64 | case 4: |
| 65 | printk_debug("533 MHz"); |
| 66 | break; |
| 67 | default: |
| 68 | printk_debug("N/A MHz (%02x)", reg8); |
| 69 | } |
| 70 | printk_debug("\r\n"); |
| 71 | |
| 72 | printk_debug("(G)MCH capable of "); |
| 73 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); |
| 74 | switch (reg8) { |
| 75 | case 2: |
| 76 | printk_debug("up to DDR2-667"); |
| 77 | break; |
| 78 | case 3: |
| 79 | printk_debug("up to DDR2-533"); |
| 80 | break; |
| 81 | case 4: |
| 82 | printk_debug("DDR2-400"); |
| 83 | break; |
| 84 | default: |
| 85 | printk_info("unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ |
| 86 | } |
| 87 | printk_debug("\r\n"); |
| 88 | } |
| 89 | |
| 90 | static void i945_setup_bars(void) |
| 91 | { |
| 92 | u8 reg8; |
| 93 | |
| 94 | /* As of now, we don't have all the A0 workarounds implemented */ |
| 95 | if (i945_silicon_revision() == 0) |
| 96 | printk_info |
| 97 | ("Warning: i945 silicon revision A0 might not work correctly.\r\n"); |
| 98 | |
| 99 | /* Setting up Southbridge. In the northbridge code. */ |
| 100 | printk_debug("Setting up static southbridge registers..."); |
| 101 | pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); |
| 102 | |
| 103 | pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); |
| 104 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ |
| 105 | |
| 106 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); |
| 107 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */ |
| 108 | setup_ich7_gpios(); |
| 109 | printk_debug(" done.\r\n"); |
| 110 | |
| 111 | printk_debug("Disabling Watchdog reboot..."); |
| 112 | RCBA32(GCS) = (RCBA32(0x3410)) | (1 << 5); /* No reset */ |
| 113 | outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ |
| 114 | printk_debug(" done.\r\n"); |
| 115 | |
| 116 | printk_debug("Setting up static northbridge registers..."); |
| 117 | /* Set up all hardcoded northbridge BARs */ |
| 118 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
| 119 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); |
| 120 | pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ |
| 121 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); |
| 122 | pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); |
| 123 | |
| 124 | /* Hardware default is 8MB UMA. If someone wants to make this a |
| 125 | * CMOS or compile time option, send a patch. |
| 126 | * pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x30); |
| 127 | */ |
| 128 | |
| 129 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 130 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); |
| 131 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |
| 132 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); |
| 133 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); |
| 134 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); |
| 135 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); |
| 136 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); |
| 137 | |
| 138 | pci_write_config8(PCI_DEV(0, 0x00, 0), TOLUD, 0x40); /* 1G XXX dynamic! */ |
| 139 | |
| 140 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); |
| 141 | printk_debug(" done.\r\n"); |
| 142 | |
| 143 | /* Wait for MCH BAR to come up */ |
| 144 | printk_debug("Waiting for MCHBAR to come up..."); |
| 145 | if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ |
| 146 | do { |
| 147 | reg8 = *(volatile u8 *)0xfed40000; |
| 148 | } while (!(reg8 & 0x80)); |
| 149 | } |
| 150 | printk_debug("ok\r\n"); |
| 151 | } |
| 152 | |
| 153 | static void i945_setup_egress_port(void) |
| 154 | { |
| 155 | u32 reg32; |
| 156 | u32 timeout; |
| 157 | |
| 158 | printk_debug("Setting up Egress Port RCRB\n"); |
| 159 | |
| 160 | /* Egress Port Virtual Channel 0 Configuration */ |
| 161 | |
| 162 | /* map only TC0 to VC0 */ |
| 163 | reg32 = EPBAR32(EPVC0RCTL); |
| 164 | reg32 &= 0xffffff01; |
| 165 | EPBAR32(EPVC0RCTL) = reg32; |
| 166 | |
| 167 | |
| 168 | reg32 = EPBAR32(EPPVCCAP1); |
| 169 | reg32 &= ~(7 << 0); |
| 170 | reg32 |= 1; |
| 171 | EPBAR32(EPPVCCAP1) = reg32; |
| 172 | |
| 173 | /* Egress Port Virtual Channel 1 Configuration */ |
| 174 | reg32 = EPBAR32(0x2c); |
| 175 | reg32 &= 0xffffff00; |
| 176 | if ((MCHBAR32(CLKCFG) & 7) == 1) |
| 177 | reg32 |= 0x0d; /* 533MHz */ |
| 178 | if ((MCHBAR32(CLKCFG) & 7) == 3) |
| 179 | reg32 |= 0x10; /* 667MHz */ |
| 180 | EPBAR32(0x2c) = reg32; |
| 181 | |
| 182 | EPBAR32(EPVC1MTS) = 0x0a0a0a0a; |
| 183 | |
| 184 | reg32 = EPBAR32(EPVC1RCAP); |
| 185 | reg32 &= ~(0x7f << 16); |
| 186 | reg32 |= (0x0a << 16); |
| 187 | EPBAR32(EPVC1RCAP) = reg32; |
| 188 | |
| 189 | if ((MCHBAR32(CLKCFG) & 7) == 1) { /* 533MHz */ |
| 190 | EPBAR32(EPVC1IST + 0) = 0x009c009c; |
| 191 | EPBAR32(EPVC1IST + 4) = 0x009c009c; |
| 192 | } |
| 193 | |
| 194 | if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ |
| 195 | EPBAR32(EPVC1IST + 0) = 0x00c000c0; |
| 196 | EPBAR32(EPVC1IST + 4) = 0x00c000c0; |
| 197 | } |
| 198 | |
| 199 | /* Is internal graphics enabled? */ |
| 200 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), 54) & ((1 << 4) | (1 << 3))) { /* DEVEN */ |
| 201 | MCHBAR32(MMARB1) |= (1 << 17); |
| 202 | } |
| 203 | |
| 204 | /* Assign Virtual Channel ID 1 to VC1 */ |
| 205 | reg32 = EPBAR32(EPVC1RCTL); |
| 206 | reg32 &= ~(7 << 24); |
| 207 | reg32 |= (1 << 24); |
| 208 | EPBAR32(EPVC1RCTL) = reg32; |
| 209 | |
| 210 | reg32 = EPBAR32(EPVC1RCTL); |
| 211 | reg32 &= 0xffffff01; |
| 212 | reg32 |= (1 << 7); |
| 213 | EPBAR32(EPVC1RCTL) = reg32; |
| 214 | |
| 215 | EPBAR32(PORTARB + 0x00) = 0x01000001; |
| 216 | EPBAR32(PORTARB + 0x04) = 0x00040000; |
| 217 | EPBAR32(PORTARB + 0x08) = 0x00001000; |
| 218 | EPBAR32(PORTARB + 0x0c) = 0x00000040; |
| 219 | EPBAR32(PORTARB + 0x10) = 0x01000001; |
| 220 | EPBAR32(PORTARB + 0x14) = 0x00040000; |
| 221 | EPBAR32(PORTARB + 0x18) = 0x00001000; |
| 222 | EPBAR32(PORTARB + 0x1c) = 0x00000040; |
| 223 | |
| 224 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 225 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 226 | |
| 227 | printk_debug("Loading port arbitration table ..."); |
| 228 | /* Loop until bit 0 becomes 0 */ |
| 229 | timeout = 0x7fffff; |
| 230 | while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ; |
| 231 | if (!timeout) |
| 232 | printk_debug("timeout!\n"); |
| 233 | else |
| 234 | printk_debug("ok\n"); |
| 235 | |
| 236 | /* Now enable VC1 */ |
| 237 | EPBAR32(EPVC1RCTL) |= (1 << 31); |
| 238 | |
| 239 | printk_debug("Wait for VC1 negotiation ..."); |
| 240 | /* Wait for VC1 negotiation pending */ |
| 241 | timeout = 0x7fff; |
| 242 | while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ; |
| 243 | if (!timeout) |
| 244 | printk_debug("timeout!\n"); |
| 245 | else |
| 246 | printk_debug("ok\n"); |
| 247 | |
| 248 | } |
| 249 | |
| 250 | static void ich7_setup_dmi_rcrb(void) |
| 251 | { |
| 252 | u16 reg16; |
| 253 | |
| 254 | |
| 255 | reg16 = RCBA16(LCTL); |
| 256 | reg16 &= ~(3 << 0); |
| 257 | reg16 |= 1; |
| 258 | RCBA16(LCTL) = reg16; |
| 259 | |
| 260 | RCBA32(V0CTL) = 0x80000001; |
| 261 | RCBA32(V1CAP) = 0x03128010; |
| 262 | RCBA32(ESD) = 0x00000810; |
| 263 | RCBA32(RP1D) = 0x01000003; |
| 264 | RCBA32(RP2D) = 0x02000002; |
| 265 | RCBA32(RP3D) = 0x03000002; |
| 266 | RCBA32(RP4D) = 0x04000002; |
| 267 | RCBA32(HDD) = 0x0f000003; |
| 268 | RCBA32(RP5D) = 0x05000002; |
| 269 | |
| 270 | RCBA32(RPFN) = 0x00543210; |
| 271 | |
| 272 | pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141); |
| 273 | pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141); |
| 274 | pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141); |
| 275 | |
| 276 | pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); |
| 277 | pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); |
| 278 | } |
| 279 | |
| 280 | static void i945_setup_dmi_rcrb(void) |
| 281 | { |
| 282 | u32 reg32; |
| 283 | u32 timeout; |
| 284 | |
| 285 | printk_debug("Setting up DMI RCRB\n"); |
| 286 | |
| 287 | /* Virtual Channel 0 Configuration */ |
| 288 | reg32 = DMIBAR32(DMIVC0RCTL0); |
| 289 | reg32 &= 0xffffff01; |
| 290 | DMIBAR32(DMIVC0RCTL0) = reg32; |
| 291 | |
| 292 | reg32 = DMIBAR32(DMIPVCCAP1); |
| 293 | reg32 &= ~(7 << 0); |
| 294 | reg32 |= 1; |
| 295 | DMIBAR32(DMIPVCCAP1) = reg32; |
| 296 | |
| 297 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 298 | reg32 &= ~(7 << 24); |
| 299 | reg32 |= (1 << 24); /* NOTE: This ID must match ICH7 side */ |
| 300 | DMIBAR32(DMIVC1RCTL) = reg32; |
| 301 | |
| 302 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 303 | reg32 &= 0xffffff01; |
| 304 | reg32 |= (1 << 7); |
| 305 | DMIBAR32(DMIVC1RCTL) = reg32; |
| 306 | |
| 307 | /* Now enable VC1 */ |
| 308 | DMIBAR32(DMIVC1RCTL) |= (1 << 31); |
| 309 | |
| 310 | printk_debug("Wait for VC1 negotiation ..."); |
| 311 | /* Wait for VC1 negotiation pending */ |
| 312 | timeout = 0x7ffff; |
| 313 | while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ; |
| 314 | if (!timeout) |
| 315 | printk_debug("timeout!\n"); |
| 316 | else |
| 317 | printk_debug("done..\n"); |
| 318 | #if 1 |
| 319 | /* Enable Active State Power Management (ASPM) L0 state */ |
| 320 | |
| 321 | reg32 = DMIBAR32(DMILCAP); |
| 322 | reg32 &= ~(7 << 12); |
| 323 | reg32 |= (2 << 12); |
| 324 | |
| 325 | reg32 &= ~(7 << 15); |
| 326 | |
| 327 | reg32 |= (2 << 15); |
| 328 | DMIBAR32(DMILCAP) = reg32; |
| 329 | |
| 330 | reg32 = DMIBAR32(DMICC); |
| 331 | reg32 &= 0x00ffffff; |
| 332 | reg32 &= ~(3 << 0); |
| 333 | reg32 |= (1 << 0); |
| 334 | DMIBAR32(DMICC) = reg32; |
| 335 | |
| 336 | if (0) { |
| 337 | DMIBAR32(DMILCTL) |= (3 << 0); |
| 338 | } |
| 339 | #endif |
| 340 | |
| 341 | /* Last but not least, some additional steps */ |
| 342 | reg32 = MCHBAR32(FSBSNPCTL); |
| 343 | reg32 &= ~(0xff << 2); |
| 344 | reg32 |= (0xaa << 2); |
| 345 | MCHBAR32(FSBSNPCTL) = reg32; |
| 346 | |
| 347 | DMIBAR32(0x2c) = 0x86000040; |
| 348 | |
| 349 | reg32 = DMIBAR32(0x204); |
| 350 | reg32 &= ~0x3ff; |
| 351 | #if 1 |
| 352 | reg32 |= 0x13f; /* for x4 DMI only */ |
| 353 | #else |
| 354 | reg32 |= 0x1e4; /* for x2 DMI only */ |
| 355 | #endif |
| 356 | DMIBAR32(0x204) = reg32; |
| 357 | |
| 358 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), 54) & ((1 << 4) | (1 << 3))) { /* DEVEN */ |
| 359 | DMIBAR32(0x200) |= (1 << 21); |
| 360 | } else { |
| 361 | DMIBAR32(0x200) &= ~(1 << 21); |
| 362 | } |
| 363 | |
| 364 | reg32 = DMIBAR32(0x204); |
| 365 | reg32 &= ~((1 << 11) | (1 << 10)); |
| 366 | DMIBAR32(0x204) = reg32; |
| 367 | |
| 368 | reg32 = DMIBAR32(0x204); |
| 369 | reg32 &= ~(0xff << 12); |
| 370 | reg32 |= (0x0d << 12); |
| 371 | DMIBAR32(0x204) = reg32; |
| 372 | |
| 373 | DMIBAR32(DMICTL1) |= (3 << 24); |
| 374 | |
| 375 | reg32 = DMIBAR32(0x200); |
| 376 | reg32 &= ~(0x3 << 26); |
| 377 | reg32 |= (0x02 << 26); |
| 378 | DMIBAR32(0x200) = reg32; |
| 379 | |
| 380 | DMIBAR32(DMIDRCCFG) &= ~(1 << 31); |
| 381 | DMIBAR32(DMICTL2) |= (1 << 31); |
| 382 | |
| 383 | if (i945_silicon_revision() >= 3) { |
| 384 | reg32 = DMIBAR32(0xec0); |
| 385 | reg32 &= 0x0fffffff; |
| 386 | reg32 |= (2 << 28); |
| 387 | DMIBAR32(0xec0) = reg32; |
| 388 | |
| 389 | reg32 = DMIBAR32(0xed4); |
| 390 | reg32 &= 0x0fffffff; |
| 391 | reg32 |= (2 << 28); |
| 392 | DMIBAR32(0xed4) = reg32; |
| 393 | |
| 394 | reg32 = DMIBAR32(0xee8); |
| 395 | reg32 &= 0x0fffffff; |
| 396 | reg32 |= (2 << 28); |
| 397 | DMIBAR32(0xee8) = reg32; |
| 398 | |
| 399 | reg32 = DMIBAR32(0xefc); |
| 400 | reg32 &= 0x0fffffff; |
| 401 | reg32 |= (2 << 28); |
| 402 | DMIBAR32(0xefc) = reg32; |
| 403 | } |
| 404 | |
| 405 | /* wait for bit toggle to 0 */ |
| 406 | printk_debug("Waiting for DMI hardware..."); |
| 407 | timeout = 0x7fffff; |
| 408 | while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ; |
| 409 | if (!timeout) |
| 410 | printk_debug("timeout!\n"); |
| 411 | else |
| 412 | printk_debug("ok\n"); |
| 413 | |
| 414 | DMIBAR32(0x1c4) = 0xffffffff; |
| 415 | DMIBAR32(0x1d0) = 0xffffffff; |
| 416 | DMIBAR32(0x228) = 0xffffffff; |
| 417 | |
| 418 | DMIBAR32(0x308) = DMIBAR32(0x308); |
| 419 | DMIBAR32(0x314) = DMIBAR32(0x314); |
| 420 | DMIBAR32(0x324) = DMIBAR32(0x324); |
| 421 | DMIBAR32(0x328) = DMIBAR32(0x328); |
| 422 | DMIBAR32(0x338) = DMIBAR32(0x334); |
| 423 | DMIBAR32(0x338) = DMIBAR32(0x338); |
| 424 | |
| 425 | if (i945_silicon_revision() == 1 && ((MCHBAR8(0xe08) & (1 << 5)) == 1)) { |
| 426 | if ((MCHBAR32(0x214) & 0xf) != 0x3) { |
| 427 | printk_info |
| 428 | ("DMI link requires A1 stepping workaround. Rebooting.\n"); |
| 429 | reg32 = MCHBAR32(MMARB1); |
| 430 | reg32 &= 0xfffffff8; |
| 431 | reg32 |= 3; |
| 432 | outb(0x06, 0xcf9); |
| 433 | for (;;) ; /* wait for reset */ |
| 434 | } |
| 435 | } |
| 436 | } |
| 437 | |
| 438 | static void i945_setup_pci_express_x16(void) |
| 439 | { |
| 440 | u32 timeout; |
| 441 | u32 reg32; |
| 442 | u16 reg16; |
| 443 | u8 reg8; |
| 444 | |
| 445 | /* For now we just disable the x16 link */ |
| 446 | printk_debug("Disabling PCI Express x16 Link\n"); |
| 447 | |
| 448 | MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); |
| 449 | |
| 450 | reg8 = pcie_read_config8(PCI_DEV(0, 0x01, 0), BCTRL1); |
| 451 | reg8 |= (1 << 6); |
| 452 | pcie_write_config8(PCI_DEV(0, 0x01, 0), BCTRL1, reg8); |
| 453 | |
| 454 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224); |
| 455 | reg32 |= (1 << 8); |
| 456 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); |
| 457 | |
| 458 | reg8 = pcie_read_config8(PCI_DEV(0, 0x01, 0), BCTRL1); |
| 459 | reg8 &= ~(1 << 6); |
| 460 | pcie_write_config8(PCI_DEV(0, 0x01, 0), BCTRL1, reg8); |
| 461 | |
| 462 | printk_debug("Wait for link to enter detect state... "); |
| 463 | timeout = 0x7fffff; |
| 464 | for (reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214); |
| 465 | (reg32 & 0x000f0000) && --timeout;) ; |
| 466 | if (!timeout) |
| 467 | printk_debug("timeout!\n"); |
| 468 | else |
| 469 | printk_debug("ok\n"); |
| 470 | |
| 471 | /* Finally: Disable the PCI config header */ |
| 472 | reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); |
| 473 | reg16 &= ~DEVEN_D1F0; |
| 474 | pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); |
| 475 | } |
| 476 | |
| 477 | static void i945_setup_root_complex_topology(void) |
| 478 | { |
| 479 | u32 reg32; |
| 480 | |
| 481 | printk_debug("Setting up Root Complex Topology\n"); |
| 482 | /* Egress Port Root Topology */ |
| 483 | reg32 = EPBAR32(EPESD); |
| 484 | reg32 &= 0xff00ffff; |
| 485 | reg32 |= (1 << 16); |
| 486 | EPBAR32(EPESD) = reg32; |
| 487 | |
| 488 | EPBAR32(EPLE1D) |= (1 << 0); |
| 489 | |
| 490 | EPBAR32(EPLE1A) = DEFAULT_PCIEXBAR + 0x4000; |
| 491 | |
| 492 | EPBAR32(EPLE2D) |= (1 << 0); |
| 493 | |
| 494 | /* DMI Port Root Topology */ |
| 495 | reg32 = DMIBAR32(DMILE1D); |
| 496 | reg32 &= 0x00ffffff; |
| 497 | DMIBAR32(DMILE1D) = reg32; |
| 498 | |
| 499 | reg32 = DMIBAR32(DMILE1D); |
| 500 | reg32 &= 0xff00ffff; |
| 501 | reg32 |= (2 << 16); |
| 502 | DMIBAR32(DMILE1D) = reg32; |
| 503 | |
| 504 | DMIBAR32(DMILE1D) |= (1 << 0); |
| 505 | |
| 506 | DMIBAR32(DMILE1A) = DEFAULT_PCIEXBAR + 0x8000; |
| 507 | |
| 508 | DMIBAR32(DMILE2D) |= (1 << 0); |
| 509 | |
| 510 | DMIBAR32(DMILE2A) = DEFAULT_PCIEXBAR + 0x5000; |
| 511 | |
| 512 | /* PCI Express x16 Port Root Topology */ |
| 513 | if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { |
| 514 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x158, |
| 515 | DEFAULT_PCIEXBAR + 0x5000); |
| 516 | |
| 517 | reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x150); |
| 518 | reg32 |= (1 << 0); |
| 519 | pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32); |
| 520 | } |
| 521 | } |
| 522 | |
| 523 | static void ich7_setup_root_complex_topology(void) |
| 524 | { |
| 525 | RCBA32(0x104) = 0x00000802; |
| 526 | RCBA32(0x110) = 0x00000001; |
| 527 | RCBA32(0x114) = 0x00000000; |
| 528 | RCBA32(0x118) = 0x00000000; |
| 529 | } |
| 530 | |
| 531 | static void ich7_setup_pci_express(void) |
| 532 | { |
| 533 | RCBA32(CG) |= (1 << 0); |
| 534 | |
| 535 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060); |
| 536 | |
| 537 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); |
| 538 | } |
| 539 | |
| 540 | static void i945_early_initialization(void) |
| 541 | { |
| 542 | /* Print some chipset specific information */ |
| 543 | i945_detect_chipset(); |
| 544 | |
| 545 | /* Setup all BARs required for early PCIe and raminit */ |
| 546 | i945_setup_bars(); |
| 547 | |
| 548 | /* Change port80 to LPC */ |
| 549 | RCBA32(GCS) &= (~0x04); |
| 550 | } |
| 551 | |
| 552 | static void i945_late_initialization(void) |
| 553 | { |
| 554 | i945_setup_egress_port(); |
| 555 | |
| 556 | ich7_setup_root_complex_topology(); |
| 557 | |
| 558 | ich7_setup_pci_express(); |
| 559 | |
| 560 | ich7_setup_dmi_rcrb(); |
| 561 | |
| 562 | i945_setup_dmi_rcrb(); |
| 563 | |
| 564 | i945_setup_pci_express_x16(); |
| 565 | |
| 566 | i945_setup_root_complex_topology(); |
| 567 | } |