Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2006 Tyan |
| 5 | * Copyright (C) 2006 AMD |
| 6 | * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD. |
| 7 | * |
| 8 | * Copyright (C) 2007 University of Mannheim |
| 9 | * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim |
| 10 | * Copyright (C) 2009 University of Heidelberg |
| 11 | * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License as published by |
| 15 | * the Free Software Foundation; either version 2 of the License, or |
| 16 | * (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 25 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 26 | */ |
| 27 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 28 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 29 | #include <string.h> |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 30 | #include <device/pci_def.h> |
| 31 | #include <device/pci_ids.h> |
| 32 | #include <arch/io.h> |
| 33 | #include <device/pnp_def.h> |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 34 | #include <cpu/x86/lapic.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 35 | #include <pc80/mc146818rtc.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 36 | #include <console/console.h> |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 37 | #include <cpu/amd/model_fxx_rev.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 38 | #include "southbridge/broadcom/bcm5785/early_smbus.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame^] | 39 | #include <northbridge/amd/amdk8/raminit.h> |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 40 | #include "lib/delay.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame^] | 41 | #include <cpu/x86/lapic.h> |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 42 | #include "northbridge/amd/amdk8/reset_test.c" |
Edward O'Callaghan | f18abab | 2014-03-31 21:53:32 +1100 | [diff] [blame] | 43 | #include <superio/serverengines/pilot/pilot.h> |
Edward O'Callaghan | b8f05d4 | 2015-01-04 16:17:54 +1100 | [diff] [blame] | 44 | #include <superio/nsc/pc87417/pc87417.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame^] | 45 | #include <cpu/x86/bist.h> |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 46 | #include "northbridge/amd/amdk8/debug.c" |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 47 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 48 | #include "southbridge/broadcom/bcm5785/early_setup.c" |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 49 | |
| 50 | #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) |
| 51 | #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) |
| 52 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 53 | static void memreset(int controllers, const struct mem_controller *ctrl) { } |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 54 | |
| 55 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 56 | { |
| 57 | #define SMBUS_SWITCH1 0x70 |
| 58 | #define SMBUS_SWITCH2 0x72 |
| 59 | unsigned device = (ctrl->channel0[0]) >> 8; |
| 60 | smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); |
| 61 | smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); |
| 62 | } |
| 63 | |
| 64 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 65 | { |
| 66 | return smbus_read_byte(device, address); |
| 67 | } |
| 68 | |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame^] | 69 | #include <northbridge/amd/amdk8/f.h> |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 70 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Stefan Reinauer | 23836e2 | 2010-04-15 12:39:29 +0000 | [diff] [blame] | 71 | #include "northbridge/amd/amdk8/coherent_ht.c" |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 72 | #include "northbridge/amd/amdk8/raminit_f.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 73 | #include "lib/generic_sdram.c" |
Patrick Georgi | 9bd9a90 | 2010-11-20 10:31:00 +0000 | [diff] [blame] | 74 | #include <spd.h> |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 75 | #include "cpu/amd/dualcore/dualcore.c" |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 76 | #include "cpu/amd/model_fxx/init_cpus.c" |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 77 | #include "cpu/amd/model_fxx/fidvid.c" |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 78 | #include "northbridge/amd/amdk8/early_ht.c" |
| 79 | |
| 80 | #if 0 |
| 81 | #include "ipmi.c" |
| 82 | |
| 83 | static void setup_early_ipmi_serial() |
| 84 | { |
| 85 | unsigned char result; |
| 86 | char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05}; |
| 87 | char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f}; |
| 88 | char serial_mux1[]={0x0c<<2,0x12,0x04,0x06}; |
| 89 | char serial_mux2[]={0x0c<<2,0x12,0x04,0x03}; |
| 90 | char serial_mux3[]={0x0c<<2,0x12,0x04,0x07}; |
| 91 | |
| 92 | // earlydbg(0x0d); |
| 93 | //set channel access system only |
| 94 | ipmi_request(5,channel_access); |
| 95 | // earlydbg(result); |
| 96 | /* |
| 97 | //Set serial/modem config |
| 98 | result=ipmi_request(6,serialmodem_conf); |
| 99 | earlydbg(result); |
| 100 | |
| 101 | //Set serial mux 1 |
| 102 | result=ipmi_request(4,serial_mux1); |
| 103 | earlydbg(result); |
| 104 | |
| 105 | //Set serial mux 2 |
| 106 | result=ipmi_request(4,serial_mux2); |
| 107 | earlydbg(result); |
| 108 | |
| 109 | //Set serial mux 3 |
| 110 | result=ipmi_request(4,serial_mux3); |
| 111 | earlydbg(result); |
| 112 | */ |
| 113 | // earlydbg(0x0e); |
| 114 | |
| 115 | } |
| 116 | #endif |
| 117 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 118 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 119 | { |
| 120 | static const uint16_t spd_addr[] = { |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 121 | // first node |
Uwe Hermann | 6dc92f0 | 2010-11-21 11:36:03 +0000 | [diff] [blame] | 122 | DIMM0, DIMM2, 0, 0, |
| 123 | DIMM1, DIMM3, 0, 0, |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 124 | // second node |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 125 | DIMM4, DIMM6, 0, 0, |
| 126 | DIMM5, DIMM7, 0, 0, |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 127 | }; |
| 128 | |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 129 | struct sys_info *sysinfo = &sysinfo_car; |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 130 | int needs_reset; |
| 131 | unsigned bsp_apicid = 0; |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 132 | |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 133 | if (!cpu_init_detectedx && boot_cpu()) { |
| 134 | /* Nothing special needs to be done to find bus 0 */ |
| 135 | /* Allow the HT devices to be found */ |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 136 | enumerate_ht_chain(); |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 137 | bcm5785_enable_lpc(); |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 138 | pc87417_enable_dev(RTC_DEV); /* Enable RTC */ |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 139 | } |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 140 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 141 | if (bist == 0) |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 142 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 143 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 144 | pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 145 | |
Stefan Reinauer | 42fa7fe | 2011-04-20 20:54:07 +0000 | [diff] [blame] | 146 | console_init(); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 147 | |
| 148 | /* Halt if there was a built in self test failure */ |
| 149 | report_bist_failure(bist); |
| 150 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 151 | // setup_early_ipmi_serial(); |
| 152 | pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 153 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Stefan Reinauer | d653211 | 2010-04-16 00:31:44 +0000 | [diff] [blame] | 154 | printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 155 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 156 | set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 157 | setup_coherent_ht_domain(); |
| 158 | |
| 159 | wait_all_core0_started(); |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 160 | #if CONFIG_LOGICAL_CPUS |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 161 | // It is said that we should start core1 after all core0 launched |
| 162 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
| 163 | * So here need to make sure last core0 is started, esp for two way system, |
| 164 | * (there may be apic id conflicts in that case) |
| 165 | */ |
| 166 | start_other_cores(); |
| 167 | wait_all_other_cores_started(bsp_apicid); |
| 168 | #endif |
| 169 | |
| 170 | /* it will set up chains and store link pair for optimization later */ |
| 171 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 172 | bcm5785_early_setup(); |
| 173 | |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 174 | #if CONFIG_SET_FIDVID |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 175 | { |
| 176 | msr_t msr; |
| 177 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | d653211 | 2010-04-16 00:31:44 +0000 | [diff] [blame] | 178 | printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 179 | } |
| 180 | enable_fid_change(); |
| 181 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 182 | init_fidvid_bsp(bsp_apicid); |
| 183 | // show final fid and vid |
| 184 | { |
| 185 | msr_t msr; |
| 186 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | d653211 | 2010-04-16 00:31:44 +0000 | [diff] [blame] | 187 | printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 188 | } |
| 189 | #endif |
| 190 | |
| 191 | needs_reset = optimize_link_coherent_ht(); |
| 192 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 193 | |
| 194 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 195 | if (needs_reset) { |
Stefan Reinauer | d653211 | 2010-04-16 00:31:44 +0000 | [diff] [blame] | 196 | printk(BIOS_INFO, "ht reset -\n"); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 197 | soft_reset(); |
| 198 | } |
| 199 | |
| 200 | allow_all_aps_stop(bsp_apicid); |
| 201 | |
| 202 | //It's the time to set ctrl in sysinfo now; |
| 203 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 204 | enable_smbus(); |
| 205 | |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 206 | //do we need apci timer, tsc...., only debug need it for better output |
| 207 | /* all ap stopped? */ |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 208 | // init_timer(); // Need to use TMICT to synconize FID/VID |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 209 | |
| 210 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 211 | |
| 212 | post_cache_as_ram(); |
Mondrian nuessle | 5b34bdd | 2009-04-22 20:34:05 +0000 | [diff] [blame] | 213 | } |