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Lee Leahyb0005132015-05-12 18:19:47 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright (C) 2014 Google Inc.
Lee Leahy1d14b3e2015-05-12 18:23:27 -07006 * Copyright (C) 2015 Intel Corporation.
Lee Leahyb0005132015-05-12 18:19:47 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Lee Leahyb0005132015-05-12 18:19:47 -070016 */
17
Lee Leahy1d14b3e2015-05-12 18:23:27 -070018#ifndef _SOC_NVS_H_
19#define _SOC_NVS_H_
Lee Leahyb0005132015-05-12 18:19:47 -070020
Jonathan Neuschäfer0781cbe2017-10-30 17:20:18 +010021#include <commonlib/helpers.h>
Stefan Reinauer6a001132017-07-13 02:20:27 +020022#include <compiler.h>
Jonathan Neuschäfer0781cbe2017-10-30 17:20:18 +010023#include <rules.h>
Lee Leahyb0005132015-05-12 18:19:47 -070024#include <vendorcode/google/chromeos/gnvs.h>
Lee Leahyb0005132015-05-12 18:19:47 -070025
Jonathan Neuschäfer0781cbe2017-10-30 17:20:18 +010026typedef struct global_nvs_t {
Lee Leahyb0005132015-05-12 18:19:47 -070027 /* Miscellaneous */
28 u16 osys; /* 0x00 - Operating System */
29 u8 smif; /* 0x02 - SMI function call ("TRAP") */
30 u8 prm0; /* 0x03 - SMI function call parameter */
31 u8 prm1; /* 0x04 - SMI function call parameter */
32 u8 scif; /* 0x05 - SCI function call (via _L00) */
33 u8 prm2; /* 0x06 - SCI function call parameter */
34 u8 prm3; /* 0x07 - SCI function call parameter */
35 u8 lckf; /* 0x08 - Global Lock function for EC */
36 u8 prm4; /* 0x09 - Lock function parameter */
37 u8 prm5; /* 0x0a - Lock function parameter */
38 u8 pcnt; /* 0x0b - Processor Count */
39 u8 ppcm; /* 0x0c - Max PPC State */
40 u8 tmps; /* 0x0d - Temperature Sensor ID */
41 u8 tlvl; /* 0x0e - Throttle Level Limit */
42 u8 flvl; /* 0x0f - Current FAN Level */
43 u8 tcrt; /* 0x10 - Critical Threshold */
44 u8 tpsv; /* 0x11 - Passive Threshold */
45 u8 tmax; /* 0x12 - CPU Tj_max */
46 u8 s5u0; /* 0x13 - Enable USB in S5 */
47 u8 s3u0; /* 0x14 - Enable USB in S3 */
48 u8 s33g; /* 0x15 - Enable 3G in S3 */
49 u8 lids; /* 0x16 - LID State */
50 u8 pwrs; /* 0x17 - AC Power State */
51 u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */
Martin Rothe18e6422017-06-03 20:03:18 -060052 u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
Lee Leahyb0005132015-05-12 18:19:47 -070053 u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
54 u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */
Duncan Laurie08112302015-08-27 15:49:12 -070055 u8 dpte; /* 0x30 - Enable DPTF */
Duncan Laurie89960842015-11-21 18:40:19 -080056 u64 nhla; /* 0x31 - NHLT Address */
57 u32 nhll; /* 0x39 - NHLT Length */
Duncan Laurie3d3b76b2016-02-25 08:45:43 -080058 u16 cid1; /* 0x3d - Wifi Country Identifier */
Furquan Shaikh3bfe3402016-10-18 14:25:25 -070059 u16 u2we; /* 0x3f - USB2 Wake Enable Bitmap */
60 u8 u3we; /* 0x41 - USB3 Wake Enable Bitmap */
Furquan Shaikh96024832017-08-04 16:24:12 -070061 u8 uior; /* 0x42 - UART debug controller init on S3 resume */
Pratik Prajapati90ebf962017-10-11 16:11:43 -070062 u8 ecps; /* 0x43 - SGX Enabled status */
63 u64 emna; /* 0x44 - 0x4B EPC base address */
64 u64 elng; /* 0x4C - 0x53 EPC Length */
Matt DeVillier76d17712017-07-01 12:25:46 -050065 u8 rsvd[96];
66
67 /* IGD OpRegion */
68 u32 aslb; /* 0xb4 - IGD OpRegion Base Address */
69 u8 ibtt; /* 0xb8 - IGD boot type */
70 u8 ipat; /* 0xb9 - IGD panel type */
71 u8 itvf; /* 0xba - IGD TV format */
72 u8 itvm; /* 0xbb - IGD TV minor format */
73 u8 ipsc; /* 0xbc - IGD Panel Scaling */
74 u8 iblc; /* 0xbd - IGD BLC configuration */
75 u8 ibia; /* 0xbe - IGD BIA configuration */
76 u8 issc; /* 0xbf - IGD SSC configuration */
77 u8 i409; /* 0xc0 - IGD 0409 modified settings */
78 u8 i509; /* 0xc1 - IGD 0509 modified settings */
79 u8 i609; /* 0xc2 - IGD 0609 modified settings */
80 u8 i709; /* 0xc3 - IGD 0709 modified settings */
81 u8 idmm; /* 0xc4 - IGD Power Conservation */
82 u8 idms; /* 0xc5 - IGD DVMT memory size */
83 u8 if1e; /* 0xc6 - IGD Function 1 Enable */
84 u8 hvco; /* 0xc7 - IGD HPLL VCO */
85 u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
86 u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
87 u8 pavp; /* 0xe9 - IGD PAVP data */
88 u8 rsvd12; /* 0xea - rsvd */
89 u8 oscc; /* 0xeb - PCIe OSC control */
90 u8 npce; /* 0xec - native pcie support */
91 u8 plfl; /* 0xed - platform flavor */
92 u8 brev; /* 0xee - board revision */
93 u8 dpbm; /* 0xef - digital port b mode */
94 u8 dpcm; /* 0xf0 - digital port c mode */
95 u8 dpdm; /* 0xf1 - digital port c mode */
96 u8 alfp; /* 0xf2 - active lfp */
97 u8 imon; /* 0xf3 - current graphics turbo imon value */
98 u8 mmio; /* 0xf4 - 64bit mmio support */
99
100 u8 unused[11];
Lee Leahyb0005132015-05-12 18:19:47 -0700101
102 /* ChromeOS specific (0x100 - 0xfff) */
103 chromeos_acpi_t chromeos;
Stefan Reinauer6a001132017-07-13 02:20:27 +0200104} __packed global_nvs_t;
Jonathan Neuschäfer0781cbe2017-10-30 17:20:18 +0100105check_member(global_nvs_t, chromeos, 0x100);
Lee Leahyb0005132015-05-12 18:19:47 -0700106
Lee Leahyb0005132015-05-12 18:19:47 -0700107#endif