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Lee Leahyb0005132015-05-12 18:19:47 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2014 Google Inc.
Lee Leahy1d14b3e2015-05-12 18:23:27 -07006 * Copyright (C) 2015 Intel Corporation.
Lee Leahyb0005132015-05-12 18:19:47 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Lee Leahyb0005132015-05-12 18:19:47 -070016 */
17
18/* Global Variables */
19
20Name (\PICM, 0) // IOAPIC/8259
21
22/*
23 * Global ACPI memory region. This region is used for passing information
24 * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
25 * Since we don't know where this will end up in memory at ACPI compile time,
26 * we have to fix it up in coreboot's ACPI creation phase.
27 */
28
Duncan Laurieaa1b6b02015-09-23 18:01:45 -070029External (NVSA)
30
Aaron Durbin04a06662015-08-04 15:33:23 -050031OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
Lee Leahyb0005132015-05-12 18:19:47 -070032Field (GNVS, ByteAcc, NoLock, Preserve)
33{
34 /* Miscellaneous */
35 Offset (0x00),
36 OSYS, 16, // 0x00 - Operating System
37 SMIF, 8, // 0x02 - SMI function
38 PRM0, 8, // 0x03 - SMI function parameter
39 PRM1, 8, // 0x04 - SMI function parameter
40 SCIF, 8, // 0x05 - SCI function
41 PRM2, 8, // 0x06 - SCI function parameter
42 PRM3, 8, // 0x07 - SCI function parameter
43 LCKF, 8, // 0x08 - Global Lock function for EC
44 PRM4, 8, // 0x09 - Lock function parameter
45 PRM5, 8, // 0x0a - Lock function parameter
46 PCNT, 8, // 0x0b - Processor Count
47 PPCM, 8, // 0x0c - Max PPC State
48 TMPS, 8, // 0x0d - Temperature Sensor ID
49 TLVL, 8, // 0x0e - Throttle Level Limit
50 FLVL, 8, // 0x0f - Current FAN Level
51 TCRT, 8, // 0x10 - Critical Threshold
52 TPSV, 8, // 0x11 - Passive Threshold
53 TMAX, 8, // 0x12 - CPU Tj_max
54 S5U0, 8, // 0x13 - Enable USB in S5
55 S3U0, 8, // 0x14 - Enable USB in S3
56 S33G, 8, // 0x15 - Enable 3G in S3
57 LIDS, 8, // 0x16 - LID State
58 PWRS, 8, // 0x17 - AC Power State
59 CMEM, 32, // 0x18 - 0x1b - CBMEM TOC
Martin Rothe18e6422017-06-03 20:03:18 -060060 CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console
Lee Leahyb0005132015-05-12 18:19:47 -070061 PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
62 GPEI, 64, // 0x28 - 0x2f - GPE wake status bit
Duncan Laurie08112302015-08-27 15:49:12 -070063 DPTE, 8, // 0x30 - Enable DPTF
Duncan Laurie89960842015-11-21 18:40:19 -080064 NHLA, 64, // 0x31 - NHLT Address
65 NHLL, 32, // 0x39 - NHLT Length
Duncan Laurie3d3b76b2016-02-25 08:45:43 -080066 CID1, 16, // 0x3d - Wifi Country Identifier
Furquan Shaikh3bfe3402016-10-18 14:25:25 -070067 U2WE, 16, // 0x3f - USB2 Wake Enable Bitmap
68 U3WE, 8, // 0x41 - USB3 Wake Enable Bitmap
Furquan Shaikh96024832017-08-04 16:24:12 -070069 UIOR, 8, // 0x42 - UART debug controller init on S3 resume
Pratik Prajapati90ebf962017-10-11 16:11:43 -070070 EPCS, 8, // 0x43 - SGX Enabled status
71 EMNA, 64, // 0x44 - 0x4B EPC base address
72 ELNG, 64, // 0x4C - 0x53 EPC Length
Lee Leahyb0005132015-05-12 18:19:47 -070073
Matt DeVillier76d17712017-07-01 12:25:46 -050074 /* IGD OpRegion */
75 Offset (0xb4),
76 ASLB, 32, // 0xb4 - IGD OpRegion Base Address
77 IBTT, 8, // 0xb8 - IGD boot panel device
78 IPAT, 8, // 0xb9 - IGD panel type cmos option
79 ITVF, 8, // 0xba - IGD TV format cmos option
80 ITVM, 8, // 0xbb - IGD TV minor format option
81 IPSC, 8, // 0xbc - IGD panel scaling
82 IBLC, 8, // 0xbd - IGD BLC config
83 IBIA, 8, // 0xbe - IGD BIA config
84 ISSC, 8, // 0xbf - IGD SSC config
85 I409, 8, // 0xc0 - IGD 0409 modified settings
86 I509, 8, // 0xc1 - IGD 0509 modified settings
87 I609, 8, // 0xc2 - IGD 0609 modified settings
88 I709, 8, // 0xc3 - IGD 0709 modified settings
89 IDMM, 8, // 0xc4 - IGD Power conservation feature
90 IDMS, 8, // 0xc5 - IGD DVMT memory size
91 IF1E, 8, // 0xc6 - IGD function 1 enable
92 HVCO, 8, // 0xc7 - IGD HPLL VCO
93 NXD1, 32, // 0xc8 - IGD _DGS next DID1
94 NXD2, 32, // 0xcc - IGD _DGS next DID2
95 NXD3, 32, // 0xd0 - IGD _DGS next DID3
96 NXD4, 32, // 0xd4 - IGD _DGS next DID4
97 NXD5, 32, // 0xd8 - IGD _DGS next DID5
98 NXD6, 32, // 0xdc - IGD _DGS next DID6
99 NXD7, 32, // 0xe0 - IGD _DGS next DID7
100 NXD8, 32, // 0xe4 - IGD _DGS next DID8
101
102 ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI)
103 PAVP, 8, // 0xe9 - IGD PAVP data
104 Offset (0xeb),
105 OSCC, 8, // 0xeb - PCIe OSC control
106 NPCE, 8, // 0xec - native pcie support
107 PLFL, 8, // 0xed - platform flavor
108 BREV, 8, // 0xee - board revision
109 DPBM, 8, // 0xef - digital port b mode
110 DPCM, 8, // 0xf0 - digital port c mode
111 DPDM, 8, // 0xf1 - digital port d mode
112 ALFP, 8, // 0xf2 - active lfp
113 IMON, 8, // 0xf3 - current graphics turbo imon value
114 MMIO, 8, // 0xf4 - 64bit mmio support
115
Lee Leahyb0005132015-05-12 18:19:47 -0700116 /* ChromeOS specific */
117 Offset (0x100),
118 #include <vendorcode/google/chromeos/acpi/gnvs.asl>
Duncan Laurief966d3b2015-08-27 17:19:24 -0700119}
Lee Leahyb0005132015-05-12 18:19:47 -0700120
Duncan Laurief966d3b2015-08-27 17:19:24 -0700121/* Set flag to enable USB charging in S3 */
122Method (S3UE)
123{
124 Store (One, \S3U0)
125}
126
127/* Set flag to disable USB charging in S3 */
128Method (S3UD)
129{
130 Store (Zero, \S3U0)
Lee Leahyb0005132015-05-12 18:19:47 -0700131}
132
Lee Leahyb0005132015-05-12 18:19:47 -0700133/* Set flag to enable USB charging in S5 */
134Method (S5UE)
135{
136 Store (One, \S5U0)
137}
138
139/* Set flag to disable USB charging in S5 */
140Method (S5UD)
141{
142 Store (Zero, \S5U0)
143}