Angel Pons | 6c42d14 | 2021-06-14 13:53:44 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
| 5 | #include <console/streams.h> |
| 6 | #include <console/usb.h> |
| 7 | #include <string.h> |
| 8 | #include <cbmem.h> |
| 9 | #include <cbfs.h> |
| 10 | #include <cf9_reset.h> |
Angel Pons | 6c42d14 | 2021-06-14 13:53:44 +0200 | [diff] [blame] | 11 | #include <memory_info.h> |
| 12 | #include <mrc_cache.h> |
| 13 | #include <device/device.h> |
| 14 | #include <device/pci_def.h> |
| 15 | #include <device/pci_ops.h> |
| 16 | #include <device/dram/ddr3.h> |
| 17 | #include <northbridge/intel/haswell/chip.h> |
| 18 | #include <northbridge/intel/haswell/haswell.h> |
| 19 | #include <northbridge/intel/haswell/raminit.h> |
| 20 | #include <smbios.h> |
| 21 | #include <spd.h> |
| 22 | #include <security/vboot/vboot_common.h> |
| 23 | #include <commonlib/region.h> |
| 24 | #include <southbridge/intel/lynxpoint/me.h> |
| 25 | #include <southbridge/intel/lynxpoint/pch.h> |
| 26 | #include <timestamp.h> |
| 27 | #include <types.h> |
| 28 | |
| 29 | #include "pei_data.h" |
| 30 | |
| 31 | static void save_mrc_data(struct pei_data *pei_data) |
| 32 | { |
| 33 | printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, |
| 34 | pei_data->data_to_save_size); |
| 35 | |
| 36 | if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0) |
| 37 | mrc_cache_stash_data(MRC_TRAINING_DATA, 0, |
| 38 | pei_data->data_to_save, |
| 39 | pei_data->data_to_save_size); |
| 40 | } |
| 41 | |
| 42 | static const char *const ecc_decoder[] = { |
| 43 | "inactive", |
| 44 | "active on IO", |
| 45 | "disabled on IO", |
| 46 | "active", |
| 47 | }; |
| 48 | |
| 49 | /* |
| 50 | * Dump in the log memory controller configuration as read from the memory |
| 51 | * controller registers. |
| 52 | */ |
| 53 | static void report_memory_config(void) |
| 54 | { |
| 55 | int i; |
| 56 | |
| 57 | const u32 addr_decoder_common = mchbar_read32(MAD_CHNL); |
| 58 | |
| 59 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
| 60 | (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); |
| 61 | |
| 62 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
| 63 | (addr_decoder_common >> 0) & 3, |
| 64 | (addr_decoder_common >> 2) & 3, |
| 65 | (addr_decoder_common >> 4) & 3); |
| 66 | |
| 67 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 68 | const u32 ch_conf = mchbar_read32(MAD_DIMM(i)); |
| 69 | |
| 70 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); |
| 71 | printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); |
| 72 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 73 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
| 74 | |
| 75 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 76 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
| 77 | |
| 78 | printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", |
| 79 | ((ch_conf >> 0) & 0xff) * 256, |
| 80 | ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", |
| 81 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 82 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
| 83 | |
| 84 | printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", |
| 85 | ((ch_conf >> 8) & 0xff) * 256, |
| 86 | ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", |
| 87 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 88 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 89 | } |
| 90 | } |
| 91 | |
Elyes Haouas | 9d450b2 | 2023-09-10 10:30:29 +0200 | [diff] [blame] | 92 | typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data); |
Angel Pons | 6c42d14 | 2021-06-14 13:53:44 +0200 | [diff] [blame] | 93 | |
| 94 | static void ABI_X86 send_to_console(unsigned char b) |
| 95 | { |
| 96 | console_tx_byte(b); |
| 97 | } |
| 98 | |
| 99 | /* |
| 100 | * Find PEI executable in coreboot filesystem and execute it. |
| 101 | */ |
| 102 | static void sdram_initialize(struct pei_data *pei_data) |
| 103 | { |
| 104 | size_t mrc_size; |
| 105 | pei_wrapper_entry_t entry; |
| 106 | int ret; |
| 107 | |
| 108 | /* Assume boot device is memory mapped. */ |
| 109 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
| 110 | |
| 111 | pei_data->saved_data = |
| 112 | mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0, |
| 113 | &mrc_size); |
| 114 | if (pei_data->saved_data) { |
| 115 | /* MRC cache found */ |
| 116 | pei_data->saved_data_size = mrc_size; |
| 117 | } else if (pei_data->boot_mode == ACPI_S3) { |
| 118 | /* Waking from S3 and no cache. */ |
| 119 | printk(BIOS_DEBUG, |
| 120 | "No MRC cache found in S3 resume path.\n"); |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 121 | post_code(POSTCODE_RESUME_FAILURE); |
Angel Pons | 6c42d14 | 2021-06-14 13:53:44 +0200 | [diff] [blame] | 122 | system_reset(); |
| 123 | } else { |
| 124 | printk(BIOS_DEBUG, "No MRC cache found.\n"); |
| 125 | } |
| 126 | |
| 127 | /* |
| 128 | * Do not use saved pei data. Can be set by mainboard romstage |
| 129 | * to force a full train of memory on every boot. |
| 130 | */ |
| 131 | if (pei_data->disable_saved_data) { |
| 132 | printk(BIOS_DEBUG, "Disabling PEI saved data by request\n"); |
| 133 | pei_data->saved_data = NULL; |
| 134 | pei_data->saved_data_size = 0; |
| 135 | } |
| 136 | |
| 137 | /* We don't care about leaking the mapping */ |
| 138 | entry = cbfs_ro_map("mrc.bin", NULL); |
| 139 | if (entry == NULL) |
| 140 | die("mrc.bin not found!"); |
| 141 | |
| 142 | printk(BIOS_DEBUG, "Starting Memory Reference Code\n"); |
| 143 | |
| 144 | ret = entry(pei_data); |
| 145 | if (ret < 0) |
| 146 | die("pei_data version mismatch\n"); |
| 147 | |
| 148 | /* Print the MRC version after executing the UEFI PEI stage. */ |
| 149 | u32 version = mchbar_read32(MRC_REVISION); |
| 150 | printk(BIOS_DEBUG, "MRC Version %u.%u.%u Build %u\n", |
| 151 | (version >> 24) & 0xff, (version >> 16) & 0xff, |
| 152 | (version >> 8) & 0xff, (version >> 0) & 0xff); |
| 153 | |
| 154 | report_memory_config(); |
| 155 | } |
| 156 | |
| 157 | static uint8_t nb_get_ecc_type(const uint32_t capid0_a) |
| 158 | { |
| 159 | return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; |
| 160 | } |
| 161 | |
| 162 | static uint16_t nb_slots_per_channel(const uint32_t capid0_a) |
| 163 | { |
| 164 | return !(capid0_a & CAPID_DDPCD) + 1; |
| 165 | } |
| 166 | |
| 167 | static uint16_t nb_number_of_channels(const uint32_t capid0_a) |
| 168 | { |
| 169 | return !(capid0_a & CAPID_PDCD) + 1; |
| 170 | } |
| 171 | |
| 172 | static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) |
| 173 | { |
| 174 | uint32_t ddrsz; |
| 175 | |
| 176 | /* Values from documentation, which assume two DIMMs per channel */ |
| 177 | switch (CAPID_DDRSZ(capid0_a)) { |
| 178 | case 1: |
| 179 | ddrsz = 8192; |
| 180 | break; |
| 181 | case 2: |
| 182 | ddrsz = 2048; |
| 183 | break; |
| 184 | case 3: |
| 185 | ddrsz = 512; |
| 186 | break; |
| 187 | default: |
| 188 | ddrsz = 16384; |
| 189 | break; |
| 190 | } |
| 191 | |
| 192 | /* Account for the maximum number of DIMMs per channel */ |
| 193 | return (ddrsz / 2) * nb_slots_per_channel(capid0_a); |
| 194 | } |
| 195 | |
| 196 | static void setup_sdram_meminfo(struct pei_data *pei_data) |
| 197 | { |
| 198 | unsigned int dimm_cnt = 0; |
| 199 | |
| 200 | struct memory_info *mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); |
| 201 | if (!mem_info) |
| 202 | die("Failed to add memory info to CBMEM.\n"); |
| 203 | |
| 204 | memset(mem_info, 0, sizeof(struct memory_info)); |
| 205 | |
| 206 | const u32 ddr_frequency = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; |
| 207 | |
| 208 | for (unsigned int ch = 0; ch < NUM_CHANNELS; ch++) { |
| 209 | const u32 ch_conf = mchbar_read32(MAD_DIMM(ch)); |
| 210 | for (unsigned int slot = 0; slot < NUM_SLOTS; slot++) { |
| 211 | const u32 dimm_size = ((ch_conf >> (slot * 8)) & 0xff) * 256; |
| 212 | if (dimm_size) { |
| 213 | struct dimm_info *dimm = &mem_info->dimm[dimm_cnt]; |
| 214 | dimm->dimm_size = dimm_size; |
| 215 | dimm->ddr_type = MEMORY_TYPE_DDR3; |
| 216 | dimm->ddr_frequency = ddr_frequency; |
| 217 | dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + slot)) & 1); |
| 218 | dimm->channel_num = ch; |
| 219 | dimm->dimm_num = slot; |
| 220 | dimm->bank_locator = ch * 2; |
| 221 | memcpy(dimm->serial, |
| 222 | &pei_data->spd_data[ch][slot][SPD_DIMM_SERIAL_NUM], |
| 223 | SPD_DIMM_SERIAL_LEN); |
| 224 | memcpy(dimm->module_part_number, |
| 225 | &pei_data->spd_data[ch][slot][SPD_DIMM_PART_NUM], |
| 226 | SPD_DIMM_PART_LEN); |
| 227 | dimm->mod_id = |
| 228 | (pei_data->spd_data[ch][slot][SPD_DIMM_MOD_ID2] << 8) | |
| 229 | (pei_data->spd_data[ch][slot][SPD_DIMM_MOD_ID1] & 0xff); |
| 230 | dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; |
| 231 | dimm->bus_width = MEMORY_BUS_WIDTH_64; |
| 232 | dimm_cnt++; |
| 233 | } |
| 234 | } |
| 235 | } |
| 236 | mem_info->dimm_cnt = dimm_cnt; |
| 237 | |
| 238 | const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 239 | |
| 240 | const uint16_t channels = nb_number_of_channels(capid0_a); |
| 241 | |
| 242 | mem_info->ecc_type = nb_get_ecc_type(capid0_a); |
| 243 | mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); |
| 244 | mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a); |
| 245 | } |
| 246 | |
| 247 | #include <device/smbus_host.h> |
| 248 | #define SPD_LEN 256 |
| 249 | |
| 250 | /* Copy SPD data for on-board memory */ |
| 251 | static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi) |
| 252 | { |
| 253 | if (!CONFIG(HAVE_SPD_IN_CBFS)) |
| 254 | return; |
| 255 | |
| 256 | printk(BIOS_DEBUG, "SPD index %d\n", spdi->spd_index); |
| 257 | |
| 258 | size_t spd_file_len; |
| 259 | uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len); |
| 260 | |
| 261 | if (!spd_file) |
| 262 | die("SPD data not found."); |
| 263 | |
| 264 | if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) { |
| 265 | printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); |
| 266 | spdi->spd_index = 0; |
| 267 | } |
| 268 | |
| 269 | if (spd_file_len < SPD_LEN) |
| 270 | die("Missing SPD data."); |
| 271 | |
| 272 | /* MRC only uses index 0, but coreboot uses the other indices */ |
| 273 | memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_LEN), SPD_LEN); |
| 274 | |
| 275 | for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) { |
| 276 | if (spdi->addresses[i] == SPD_MEMORY_DOWN) |
| 277 | memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_LEN); |
| 278 | } |
| 279 | } |
| 280 | |
| 281 | /* |
| 282 | * 0 = leave channel enabled |
| 283 | * 1 = disable dimm 0 on channel |
| 284 | * 2 = disable dimm 1 on channel |
| 285 | * 3 = disable dimm 0+1 on channel |
| 286 | */ |
| 287 | static int make_channel_disabled_mask(const struct pei_data *pd, int ch) |
| 288 | { |
| 289 | return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1); |
| 290 | } |
| 291 | |
| 292 | static enum pei_usb2_port_location map_to_pei_usb2_location(const enum usb2_port_location loc) |
| 293 | { |
| 294 | /* TODO: USB_PORT_NGFF_DEVICE_DOWN (not used by any board, though) */ |
| 295 | static const enum pei_usb2_port_location map[] = { |
| 296 | [USB_PORT_SKIP] = PEI_USB_PORT_SKIP, |
| 297 | [USB_PORT_BACK_PANEL] = PEI_USB_PORT_BACK_PANEL, |
| 298 | [USB_PORT_FRONT_PANEL] = PEI_USB_PORT_FRONT_PANEL, |
| 299 | [USB_PORT_DOCK] = PEI_USB_PORT_DOCK, |
| 300 | [USB_PORT_MINI_PCIE] = PEI_USB_PORT_MINI_PCIE, |
| 301 | [USB_PORT_FLEX] = PEI_USB_PORT_FLEX, |
| 302 | [USB_PORT_INTERNAL] = PEI_USB_PORT_INTERNAL, |
| 303 | }; |
| 304 | return loc >= ARRAY_SIZE(map) ? PEI_USB_PORT_SKIP : map[loc]; |
| 305 | } |
| 306 | |
| 307 | static uint8_t map_to_pei_oc_pin(const uint8_t oc_pin) |
| 308 | { |
| 309 | return oc_pin >= USB_OC_PIN_SKIP ? PEI_USB_OC_PIN_SKIP : oc_pin; |
| 310 | } |
| 311 | |
| 312 | static bool early_init_native(int s3resume) |
| 313 | { |
| 314 | printk(BIOS_DEBUG, "Starting native platform initialisation\n"); |
| 315 | |
| 316 | intel_early_me_init(); |
| 317 | /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/ |
| 318 | const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check(); |
| 319 | |
| 320 | early_pch_init_native(s3resume); |
| 321 | |
| 322 | if (!CONFIG(INTEL_LYNXPOINT_LP)) |
| 323 | dmi_early_init(); |
| 324 | |
| 325 | return cpu_replaced; |
| 326 | } |
| 327 | |
| 328 | void perform_raminit(const int s3resume) |
| 329 | { |
| 330 | const struct northbridge_intel_haswell_config *cfg = config_of_soc(); |
| 331 | |
| 332 | struct pei_data pei_data = { |
| 333 | .pei_version = PEI_VERSION, |
| 334 | .board_type = get_pch_platform_type(), |
| 335 | .usbdebug = CONFIG(USBDEBUG), |
| 336 | .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, |
| 337 | .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, |
| 338 | .ehcibar = CONFIG_EHCI_BAR, |
| 339 | .xhcibar = 0xd7000000, |
| 340 | .gttbar = 0xe0000000, |
| 341 | .pmbase = DEFAULT_PMBASE, |
| 342 | .gpiobase = DEFAULT_GPIOBASE, |
| 343 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 344 | .temp_mmio_base = 0xfed08000, |
| 345 | .ec_present = cfg->ec_present, |
| 346 | .dq_pins_interleaved = cfg->dq_pins_interleaved, |
| 347 | .tx_byte = send_to_console, |
| 348 | .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), |
| 349 | .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, /* Might be unused */ |
| 350 | }; |
| 351 | |
| 352 | for (size_t i = 0; i < ARRAY_SIZE(mainboard_usb2_ports); i++) { |
| 353 | /* If a port is not enabled, skip it */ |
| 354 | if (!mainboard_usb2_ports[i].enable) { |
| 355 | pei_data.usb2_ports[i].oc_pin = PEI_USB_OC_PIN_SKIP; |
| 356 | pei_data.usb2_ports[i].location = PEI_USB_PORT_SKIP; |
| 357 | continue; |
| 358 | } |
| 359 | const enum usb2_port_location loc = mainboard_usb2_ports[i].location; |
| 360 | const uint8_t oc_pin = mainboard_usb2_ports[i].oc_pin; |
| 361 | pei_data.usb2_ports[i].length = mainboard_usb2_ports[i].length; |
| 362 | pei_data.usb2_ports[i].enable = mainboard_usb2_ports[i].enable; |
| 363 | pei_data.usb2_ports[i].oc_pin = map_to_pei_oc_pin(oc_pin); |
| 364 | pei_data.usb2_ports[i].location = map_to_pei_usb2_location(loc); |
| 365 | } |
| 366 | |
| 367 | for (size_t i = 0; i < ARRAY_SIZE(mainboard_usb3_ports); i++) { |
| 368 | const uint8_t oc_pin = mainboard_usb3_ports[i].oc_pin; |
| 369 | pei_data.usb3_ports[i].enable = mainboard_usb3_ports[i].enable; |
| 370 | pei_data.usb3_ports[i].oc_pin = map_to_pei_oc_pin(oc_pin); |
| 371 | } |
| 372 | |
| 373 | /* Broadwell MRC uses ACPI values for boot_mode */ |
| 374 | pei_data.boot_mode = s3resume ? ACPI_S3 : ACPI_S0; |
| 375 | |
| 376 | /* Obtain the SPD addresses from mainboard code */ |
| 377 | struct spd_info spdi = {0}; |
| 378 | mb_get_spd_map(&spdi); |
| 379 | |
| 380 | /* |
| 381 | * Read the SPDs over SMBus in coreboot code so that the data can be used to |
| 382 | * populate meminfo. MRC returns some data, but it seems to be incomplete. |
| 383 | */ |
| 384 | for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) { |
| 385 | const uint8_t addr = spdi.addresses[i]; |
| 386 | pei_data.spd_addresses[i] = addr == SPD_MEMORY_DOWN ? 0xff : addr << 1; |
| 387 | if (addr == SPD_MEMORY_DOWN) |
| 388 | continue; |
| 389 | |
| 390 | if (i2c_eeprom_read(addr, 0, 256, pei_data.spd_data[i / 2][i % 2]) != 256) { |
| 391 | printk(BIOS_ERR, "0x%02x failed to read\n", addr); |
| 392 | memset(pei_data.spd_data[i / 2][i % 2], 0, 256); |
| 393 | } |
| 394 | } |
| 395 | |
| 396 | /* Calculate unimplemented DIMM slots for each channel */ |
| 397 | pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); |
| 398 | pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1); |
| 399 | |
| 400 | for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) |
| 401 | pei_data.spd_addresses[i] = 0; |
| 402 | |
| 403 | if (early_init_native(s3resume)) |
| 404 | pei_data.disable_saved_data = true; |
| 405 | |
| 406 | timestamp_add_now(TS_INITRAM_START); |
| 407 | |
| 408 | copy_spd(&pei_data, &spdi); |
| 409 | |
| 410 | sdram_initialize(&pei_data); |
| 411 | |
| 412 | timestamp_add_now(TS_INITRAM_END); |
| 413 | |
| 414 | if (intel_early_me_uma_size() > 0) { |
| 415 | /* |
| 416 | * The 'other' success value is to report loss of memory |
| 417 | * consistency to ME if warm boot was downgraded to cold. |
| 418 | * However, we can't tell if MRC downgraded the bootmode. |
| 419 | */ |
| 420 | intel_early_me_init_done(ME_INIT_STATUS_SUCCESS_OTHER); |
| 421 | } |
| 422 | |
| 423 | intel_early_me_status(); |
| 424 | |
| 425 | int cbmem_was_initted = !cbmem_recovery(s3resume); |
| 426 | if (s3resume && !cbmem_was_initted) { |
| 427 | /* Failed S3 resume, reset to come up cleanly */ |
| 428 | printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n"); |
| 429 | system_reset(); |
| 430 | } |
| 431 | |
| 432 | /* Save data returned from MRC on non-S3 resumes. */ |
| 433 | if (!s3resume) |
| 434 | save_mrc_data(&pei_data); |
| 435 | |
| 436 | setup_sdram_meminfo(&pei_data); |
| 437 | } |