Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
| 5 | * |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation, either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef DEVICE_DRAM_DDR3L_H |
| 21 | #define DEVICE_DRAM_DDR3L_H |
| 22 | |
| 23 | /** |
| 24 | * @file ddr3.h |
| 25 | * |
| 26 | * \brief Utilities for decoding DDR3 SPDs |
| 27 | */ |
| 28 | |
| 29 | #include <stdint.h> |
| 30 | #include <spd.h> |
| 31 | |
| 32 | /** |
| 33 | * \brief Convenience definitions for TCK values |
| 34 | * |
| 35 | * Different values for tCK, representing standard DDR3 frequencies. |
| 36 | * These values are in 1/256 ns units. |
| 37 | * @{ |
| 38 | */ |
| 39 | #define TCK_1066MHZ 240 |
| 40 | #define TCK_800MHZ 320 |
| 41 | #define TCK_666MHZ 384 |
| 42 | #define TCK_533MHZ 480 |
| 43 | #define TCK_400MHZ 640 |
| 44 | #define TCK_333MHZ 768 |
| 45 | #define TCK_266MHZ 960 |
| 46 | #define TCK_200MHZ 1280 |
| 47 | /** @} */ |
| 48 | |
| 49 | /** |
| 50 | * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP |
| 51 | * |
| 52 | * Use this macro instead of printk(); for verbose RAM initialization messages. |
| 53 | * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically |
| 54 | * disabled. |
| 55 | * @{ |
| 56 | */ |
| 57 | #if defined(CONFIG_DEBUG_RAM_SETUP) && (CONFIG_DEBUG_RAM_SETUP) |
| 58 | #define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) |
| 59 | #else |
| 60 | #define printram(x, ...) |
| 61 | #endif |
| 62 | /** @} */ |
| 63 | |
| 64 | /* |
| 65 | * Module type (byte 3, bits 3:0) of SPD |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 66 | * This definition is specific to DDR3. DDR2 SPDs have a different structure. |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 67 | */ |
| 68 | enum spd_dimm_type { |
| 69 | SPD_DIMM_TYPE_UNDEFINED = 0x00, |
| 70 | SPD_DIMM_TYPE_RDIMM = 0x01, |
| 71 | SPD_DIMM_TYPE_UDIMM = 0x02, |
| 72 | SPD_DIMM_TYPE_SO_DIMM = 0x03, |
| 73 | SPD_DIMM_TYPE_MICRO_DIMM = 0x04, |
| 74 | SPD_DIMM_TYPE_MINI_RDIMM = 0x05, |
| 75 | SPD_DIMM_TYPE_MINI_UDIMM = 0x06, |
| 76 | SPD_DIMM_TYPE_MINI_CDIMM = 0x07, |
| 77 | SPD_DIMM_TYPE_72B_SO_UDIMM = 0x08, |
| 78 | SPD_DIMM_TYPE_72B_SO_RDIMM = 0x09, |
| 79 | SPD_DIMM_TYPE_72B_SO_CDIMM = 0x0a, |
| 80 | SPD_DIMM_TYPE_LRDIMM = 0x0b, |
| 81 | SPD_DIMM_TYPE_16B_SO_DIMM = 0x0d, |
| 82 | SPD_DIMM_TYPE_32B_SO_DIMM = 0x0e, |
| 83 | /* Masks to bits 3:0 to give the dimm type */ |
| 84 | SPD_DIMM_TYPE_MASK = 0x0f, |
| 85 | }; |
| 86 | |
| 87 | /** |
| 88 | * \brief DIMM flags |
| 89 | * |
| 90 | * Characteristic flags for the DIMM, as presented by the SPD |
| 91 | */ |
| 92 | typedef union dimm_flags_st { |
| 93 | /* The whole point of the union/struct construct is to allow us to clear |
| 94 | * all the bits with one line: flags.raw = 0. |
| 95 | * We do not care how these bits are ordered */ |
| 96 | struct { |
| 97 | /* Indicates if rank 1 of DIMM uses a mirrored pin mapping. See: |
| 98 | * Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM */ |
| 99 | unsigned pins_mirrored:1; |
| 100 | /* Module can work at 1.50V - All DIMMS must be 1.5V operable */ |
| 101 | unsigned operable_1_50V:1; |
| 102 | /* Module can work at 1.35V */ |
| 103 | unsigned operable_1_35V:1; |
| 104 | /* Module can work at 1.20V */ |
| 105 | unsigned operable_1_25V:1; |
| 106 | /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ |
| 107 | unsigned is_ecc:1; |
| 108 | /* DLL-Off Mode Support */ |
| 109 | unsigned dll_off_mode:1; |
| 110 | /* Indicates a drive strength of RZQ/6 (40 Ohm) is supported */ |
| 111 | unsigned rzq6_supported:1; |
| 112 | /* Indicates a drive strength of RZQ/7 (35 Ohm) is supported */ |
| 113 | unsigned rzq7_supported:1; |
| 114 | /* Partial Array Self Refresh */ |
| 115 | unsigned pasr:1; |
| 116 | /* On-die Thermal Sensor Readout */ |
| 117 | unsigned odts:1; |
| 118 | /* Auto Self Refresh */ |
| 119 | unsigned asr:1; |
| 120 | /* Extended temperature range supported */ |
| 121 | unsigned ext_temp_range:1; |
| 122 | /* Operating at extended temperature requires 2X refresh rate */ |
| 123 | unsigned ext_temp_refresh:1; |
| 124 | /* Thermal sensor incorporated */ |
| 125 | unsigned therm_sensor:1; |
| 126 | }; |
| 127 | unsigned raw; |
| 128 | } dimm_flags_t; |
| 129 | |
| 130 | /** |
| 131 | * \brief DIMM characteristics |
| 132 | * |
| 133 | * The characteristics of each DIMM, as presented by the SPD |
| 134 | */ |
| 135 | typedef struct dimm_attr_st { |
| 136 | enum spd_memory_type dram_type; |
| 137 | u16 cas_supported; |
| 138 | /* Flags extracted from SPD */ |
| 139 | dimm_flags_t flags; |
| 140 | /* Number of ranks */ |
| 141 | u8 ranks; |
| 142 | /* Number or row address bits */ |
| 143 | u8 row_bits; |
| 144 | /* Number or column address bits */ |
| 145 | u8 col_bits; |
| 146 | /* Size of module in MiB */ |
| 147 | u32 size_mb; |
| 148 | /* Latencies are in units of 1/256 ns */ |
| 149 | u32 tCK; |
| 150 | u32 tAA; |
| 151 | u32 tWR; |
| 152 | u32 tRCD; |
| 153 | u32 tRRD; |
| 154 | u32 tRP; |
| 155 | u32 tRAS; |
| 156 | u32 tRC; |
| 157 | u32 tRFC; |
| 158 | u32 tWTR; |
| 159 | u32 tRTP; |
| 160 | u32 tFAW; |
| 161 | } dimm_attr; |
| 162 | |
| 163 | /** Result of the SPD decoding process */ |
| 164 | enum spd_status { |
| 165 | SPD_STATUS_OK = 0, |
| 166 | SPD_STATUS_INVALID, |
| 167 | SPD_STATUS_CRC_ERROR, |
| 168 | SPD_STATUS_INVALID_FIELD, |
| 169 | }; |
| 170 | |
| 171 | typedef u8 spd_raw_data[256]; |
| 172 | |
Alexandru Gagniuc | 4c37e58 | 2013-12-17 13:08:01 -0500 | [diff] [blame] | 173 | u16 spd_ddr3_calc_crc(u8 *spd, int len); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 174 | int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd_data); |
| 175 | int dimm_is_registered(enum spd_dimm_type type); |
| 176 | void dram_print_spd_ddr3(const dimm_attr * dimm); |
| 177 | |
| 178 | /** |
| 179 | * \brief Read double word from specified address |
| 180 | * |
| 181 | * Should be useful when doing an MRS to the DIMM |
| 182 | */ |
| 183 | static inline u32 volatile_read(volatile u32 addr) |
| 184 | { |
| 185 | volatile u32 result; |
| 186 | result = *(volatile u32 *)addr; |
| 187 | return result; |
| 188 | } |
| 189 | |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 190 | /** |
| 191 | * \brief Representation of an MRS command |
| 192 | * |
| 193 | * This represents an MRS command as seen by the DIMM. This is not a memory |
| 194 | * address that can be read to generate an MRS command. The mapping of CPU |
| 195 | * to memory pins is hardware-dependent. |
| 196 | * \n |
| 197 | * The idea is to generalize the MRS code, and only need a hardware-specific |
| 198 | * function to map the MRS bits to CPU address bits. An MRS command can be |
| 199 | * sent like: |
| 200 | * @code{.c} |
| 201 | * u32 addr; |
| 202 | * mrs_cmd_t mrs; |
| 203 | * chipset_enable_mrs_command_mode(); |
| 204 | * mrs = ddr3_get_mr2(rtt_wr, srt, asr, cwl) |
| 205 | * if (rank_has_mirrorred_pins) |
| 206 | * mrs = ddr3_mrs_mirror_pins(mrs); |
| 207 | * addr = chipset_specific_get_mrs_addr(mrs); |
| 208 | * volatile_read(addr); |
| 209 | * @endcode |
| 210 | * |
| 211 | * The MRS representation has the following structure: |
| 212 | * - cmd[15:0] = Address pins MA[15:0] |
| 213 | * - cmd[18:16] = Bank address BA[2:0] |
| 214 | */ |
| 215 | typedef u32 mrs_cmd_t; |
| 216 | |
| 217 | enum ddr3_mr0_precharge { |
| 218 | DDR3_MR0_PRECHARGE_SLOW = 0, |
| 219 | DDR3_MR0_PRECHARGE_FAST = 1, |
| 220 | }; |
| 221 | enum ddr3_mr0_mode { |
| 222 | DDR3_MR0_MODE_NORMAL = 0, |
| 223 | DDR3_MR0_MODE_TEST = 1, |
| 224 | }; |
| 225 | enum ddr3_mr0_dll_reset { |
| 226 | DDR3_MR0_DLL_RESET_NO = 0, |
| 227 | DDR3_MR0_DLL_RESET_YES = 1, |
| 228 | }; |
| 229 | enum ddr3_mr0_burst_type { |
| 230 | DDR3_MR0_BURST_TYPE_SEQUENTIAL = 0, |
| 231 | DDR3_MR0_BURST_TYPE_INTERLEAVED = 1, |
| 232 | }; |
| 233 | enum ddr3_mr0_burst_length { |
| 234 | DDR3_MR0_BURST_LENGTH_8 = 0, |
| 235 | DDR3_MR0_BURST_LENGTH_CHOP = 1, |
| 236 | DDR3_MR0_BURST_LENGTH_4 = 2, |
| 237 | }; |
| 238 | mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, |
| 239 | u8 write_recovery, |
| 240 | enum ddr3_mr0_dll_reset dll_reset, |
| 241 | enum ddr3_mr0_mode mode, |
| 242 | u8 cas, |
| 243 | enum ddr3_mr0_burst_type interleaved_burst, |
| 244 | enum ddr3_mr0_burst_length burst_length); |
| 245 | |
| 246 | enum ddr3_mr1_qoff { |
| 247 | DDR3_MR1_QOFF_ENABLE = 0, |
| 248 | DDR3_MR1_QOFF_DISABLE = 1, |
| 249 | }; |
| 250 | enum ddr3_mr1_tqds { |
| 251 | DDR3_MR1_TQDS_DISABLE = 0, |
| 252 | DDR3_MR1_TQDS_ENABLE = 1, |
| 253 | }; |
| 254 | enum ddr3_mr1_write_leveling { |
| 255 | DDR3_MR1_WRLVL_DISABLE = 0, |
| 256 | DDR3_MR1_WRLVL_ENABLE = 1, |
| 257 | }; |
| 258 | enum ddr3_mr1_rtt_nom { |
| 259 | DDR3_MR1_RTT_NOM_OFF = 0, |
| 260 | DDR3_MR1_RTT_NOM_RZQ4 = 1, |
| 261 | DDR3_MR1_RTT_NOM_RZQ2 = 2, |
| 262 | DDR3_MR1_RTT_NOM_RZQ6 = 3, |
| 263 | DDR3_MR1_RTT_NOM_RZQ12 = 4, |
| 264 | DDR3_MR1_RTT_NOM_RZQ8 = 5, |
| 265 | }; |
| 266 | enum ddr3_mr1_additive_latency { |
| 267 | DDR3_MR1_AL_DISABLE = 0, |
| 268 | DDR3_MR1_AL_CL_MINUS_1 = 1, |
| 269 | DDR3_MR1_AL_CL_MINUS_2 = 2, |
| 270 | }; |
| 271 | enum ddr3_mr1_ods { |
| 272 | DDR3_MR1_ODS_RZQ6 = 0, |
| 273 | DDR3_MR1_ODS_RZQ7 = 1, |
| 274 | }; |
| 275 | enum ddr3_mr1_dll { |
| 276 | DDR3_MR1_DLL_ENABLE = 0, |
| 277 | DDR3_MR1_DLL_DISABLE = 1, |
| 278 | }; |
| 279 | |
| 280 | mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, |
| 281 | enum ddr3_mr1_tqds tqds, |
| 282 | enum ddr3_mr1_rtt_nom rtt_nom, |
| 283 | enum ddr3_mr1_write_leveling write_leveling, |
| 284 | enum ddr3_mr1_ods output_drive_strenght, |
| 285 | enum ddr3_mr1_additive_latency additive_latency, |
| 286 | enum ddr3_mr1_dll dll_disable); |
| 287 | |
| 288 | enum ddr3_mr2_rttwr { |
| 289 | DDR3_MR2_RTTWR_OFF = 0, |
| 290 | DDR3_MR2_RTTWR_RZQ4 = 1, |
| 291 | DDR3_MR2_RTTWR_RZQ2 = 2, |
| 292 | }; |
| 293 | enum ddr3_mr2_srt_range { |
| 294 | DDR3_MR2_SRT_NORMAL = 0, |
| 295 | DDR3_MR2_SRT_EXTENDED = 1, |
| 296 | }; |
| 297 | enum ddr3_mr2_asr { |
| 298 | DDR3_MR2_ASR_MANUAL = 0, |
| 299 | DDR3_MR2_ASR_AUTO = 1, |
| 300 | }; |
| 301 | |
| 302 | mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, |
| 303 | enum ddr3_mr2_srt_range extended_temp, |
| 304 | enum ddr3_mr2_asr self_refresh, u8 cas_cwl); |
| 305 | |
| 306 | mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr); |
| 307 | mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd); |
| 308 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 309 | #endif /* DEVICE_DRAM_DDR3_H */ |