Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2014 - 2017 Intel Corporation. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | |
| 16 | config SOC_INTEL_DENVERTON_NS |
| 17 | bool |
| 18 | help |
| 19 | Intel Denverton-NS SoC support |
| 20 | |
| 21 | if SOC_INTEL_DENVERTON_NS |
| 22 | |
| 23 | config CPU_SPECIFIC_OPTIONS |
| 24 | def_bool y |
| 25 | select ARCH_BOOTBLOCK_X86_32 |
| 26 | select ARCH_RAMSTAGE_X86_32 |
| 27 | select ARCH_ROMSTAGE_X86_32 |
| 28 | select ARCH_VERSTAGE_X86_32 |
| 29 | select BOOTBLOCK_CONSOLE |
| 30 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 31 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 32 | select POSTCAR_CONSOLE |
| 33 | select SOC_INTEL_COMMON |
| 34 | select SOC_INTEL_COMMON_RESET |
| 35 | select PLATFORM_USES_FSP2_0 |
| 36 | select HAVE_HARD_RESET |
| 37 | select POSTCAR_STAGE |
| 38 | select C_ENVIRONMENT_BOOTBLOCK |
| 39 | select IOAPIC |
| 40 | select HAVE_SMI_HANDLER |
| 41 | select SMM_TSEG |
| 42 | select CACHE_MRC_SETTINGS |
| 43 | select RELOCATABLE_RAMSTAGE # Build fails if this is not selected |
| 44 | select PARALLEL_MP |
| 45 | select SMP |
| 46 | select SOC_INTEL_COMMON_BLOCK |
| 47 | # select SOC_INTEL_COMMON_BLOCK_SA |
| 48 | select SOC_INTEL_COMMON_BLOCK_FAST_SPI |
| 49 | select TSC_CONSTANT_RATE |
| 50 | select TSC_MONOTONIC_TIMER |
| 51 | select TSC_SYNC_MFENCE |
| 52 | select UDELAY_TSC |
| 53 | |
| 54 | config FSP_T_ADDR |
| 55 | hex "Intel FSP-T (temp ram init) binary location" |
| 56 | depends on ADD_FSP_BINARIES && FSP_CAR |
| 57 | default 0xfff30000 |
| 58 | help |
| 59 | The memory location of the Intel FSP-T binary for this platform. |
| 60 | |
| 61 | config FSP_M_ADDR |
| 62 | hex "Intel FSP-M (memory init) binary location" |
| 63 | depends on ADD_FSP_BINARIES |
| 64 | default 0xfff32000 |
| 65 | help |
| 66 | The memory location of the Intel FSP-M binary for this platform. |
| 67 | |
| 68 | config FSP_S_ADDR |
| 69 | hex "Intel FSP-S (silicon init) binary location" |
| 70 | depends on ADD_FSP_BINARIES |
| 71 | default 0xfffc3000 |
| 72 | help |
| 73 | The memory location of the Intel FSP-S binary for this platform. |
| 74 | |
| 75 | # CAR memory layout on DENVERTON_NS hardware: |
| 76 | ## CAR base address - 0xfef00000 |
| 77 | ## CAR size 1MB - 0x100 (0xfff00) |
| 78 | ## coreboot usage: |
| 79 | ## DCACHE base - 0xfef00000 |
| 80 | ## DCACHE size - 0xb0000 |
| 81 | ## FSP usage: |
| 82 | ## FSP base - 0xfefb0000 |
| 83 | ## FSP size - 0x50000 - 0x100 (0x4ff00) |
| 84 | config MAX_CPUS |
| 85 | int |
| 86 | default 16 |
| 87 | |
| 88 | config DCACHE_RAM_BASE |
| 89 | hex |
| 90 | default 0xfef00000 |
| 91 | |
| 92 | config DCACHE_RAM_SIZE |
| 93 | hex |
| 94 | default 0xb0000 if FSP_CAR |
| 95 | default 0x100000 if !FSP_CAR |
| 96 | |
| 97 | config DCACHE_BSP_STACK_SIZE |
| 98 | hex |
| 99 | default 0x10000 |
| 100 | |
| 101 | config CPU_MICROCODE_CBFS_LOC |
| 102 | hex |
| 103 | default 0xfff20040 |
| 104 | |
| 105 | config CPU_MICROCODE_CBFS_LEN |
| 106 | hex |
| 107 | default 0x0ff80 |
| 108 | |
| 109 | config SMM_TSEG_SIZE |
| 110 | hex |
| 111 | default 0x200000 |
| 112 | |
| 113 | config SMM_RESERVED_SIZE |
| 114 | hex |
| 115 | default 0x000000 |
| 116 | |
| 117 | config IQAT_ENABLE |
| 118 | bool "Enable IQAT" |
| 119 | default y |
| 120 | |
| 121 | config IQAT_MEMORY_REGION_SIZE |
| 122 | depends on IQAT_ENABLE |
| 123 | hex |
| 124 | default 0x100000 |
| 125 | help |
| 126 | Do not change this value |
| 127 | |
| 128 | config HSUART_DEV |
| 129 | hex |
| 130 | default 0x1a |
| 131 | |
| 132 | config HSUART_FUNC |
| 133 | hex |
| 134 | default 0x0 |
| 135 | |
| 136 | choice |
| 137 | prompt "UART mode selection" |
| 138 | default NON_LEGACY_UART_MODE |
| 139 | |
| 140 | config NON_LEGACY_UART_MODE |
| 141 | bool "Non Legacy Mode" |
| 142 | help |
| 143 | Disable legacy UART mode |
| 144 | |
| 145 | config LEGACY_UART_MODE |
| 146 | bool "Legacy Mode" |
| 147 | help |
| 148 | Enable legacy UART mode |
| 149 | endchoice |
| 150 | |
| 151 | config ENABLE_HSUART |
| 152 | depends on (!DRIVERS_UART_8250IO && NON_LEGACY_UART_MODE) |
| 153 | bool "Enable High-speed UART debug port selected by UART_FOR_CONSOLE." |
| 154 | default n |
| 155 | select CONSOLE_SERIAL |
| 156 | select DRIVERS_UART |
| 157 | select DRIVERS_UART_8250MEM |
| 158 | |
| 159 | config CONSOLE_UART_BASE_ADDRESS |
| 160 | depends on ENABLE_HSUART |
| 161 | hex "MMIO base address for UART" |
| 162 | default 0xd4000000 |
| 163 | |
| 164 | config C_ENV_BOOTBLOCK_SIZE |
| 165 | hex |
| 166 | default 0x8000 |
| 167 | |
| 168 | config DENVERTON_NS_CAR_NEM_ENHANCED |
| 169 | bool "Enhanced Non-evict mode" |
| 170 | depends on !FSP_CAR |
| 171 | default y |
| 172 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 173 | select INTEL_CAR_NEM_ENHANCED |
| 174 | help |
| 175 | A current limitation of NEM (Non-Evict mode) is that code and data sizes |
| 176 | are derived from the requirement to not write out any modified cache line. |
| 177 | With NEM, if there is no physical memory behind the cached area, |
| 178 | the modified data will be lost and NEM results will be inconsistent. |
| 179 | ENHANCED NEM guarantees that modified data is always |
| 180 | kept in cache while clean data is replaced. |
| 181 | |
| 182 | endif ## SOC_INTEL_DENVERTON_NS |