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Angel Pons60ec3652020-04-03 01:22:13 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Aamir Bohra630aa4b2019-12-06 19:19:19 +05303
4#include <baseboard/gpio.h>
5#include <baseboard/variants.h>
6#include <commonlib/helpers.h>
7
8/* Pad configuration in ramstage*/
9static const struct pad_config gpio_table[] = {
Maulik V Vaghelad7564dc2020-03-20 15:44:46 +053010
Maulik V Vaghelaaa832c12020-03-27 17:38:15 +053011 /* WWAN_WAKE_N */
12 PAD_CFG_GPI_SCI(GPP_A10, NONE, DEEP, LEVEL, INVERT),
13
Maulik V Vaghela733ef792020-04-21 20:21:34 +053014 /* DDI1_HPD */
15 PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
16
17 /* DDI0_HPD */
18 PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
19
Maulik V Vaghelaaa832c12020-03-27 17:38:15 +053020 /* M.2_WWAN_DISABLE_N */
21 PAD_CFG_GPO(GPP_A19, 1, PLTRST),
22
Maulik V Vaghela733ef792020-04-21 20:21:34 +053023 /* PMC_CORE_VID0 */
24 PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
25
26 /* PMC_CORE_VID1 */
27 PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
28
29 /* PMC_SLP_S0_N */
30 PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
31
32 /* PMC_PLT_RST_N */
33 PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
34
Maulik V Vaghelaef5ff0b2020-03-30 20:15:01 +053035 /* M.2_WLAN_PERST_N */
36 PAD_CFG_GPO(GPP_B17, 1, PLTRST),
37
Maulik V Vaghela733ef792020-04-21 20:21:34 +053038 /* GSPI1_CS0_N */
Ronak Kanabard31c1502020-04-14 18:00:04 +053039 PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
40
41 /* GSPI1_CLK */
42 PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
43
44 /* GSPI1_MISO */
45 PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
46
47 /* GSPI1_MOSI */
48 PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
49
Maulik V Vaghela733ef792020-04-21 20:21:34 +053050 /* DDI2_HPD */
Ronak Kanabard31c1502020-04-14 18:00:04 +053051 PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
52
Maulik V Vaghelaaa832c12020-03-27 17:38:15 +053053 /* WWAN_PERST_N */
54 PAD_CFG_GPO(GPP_C0, 0, PLTRST),
55
56 /* M2_WWAN_SSD_SKT2_CFG2 */
57 PAD_CFG_GPI(GPP_C3, NONE, PLTRST),
58
Maulik V Vaghela733ef792020-04-21 20:21:34 +053059 /* SLP_LAN_N */
Ronak Kanabard31c1502020-04-14 18:00:04 +053060 PAD_CFG_GPO(GPP_C7, 0, PLTRST),
61
Maulik V Vaghelad7564dc2020-03-20 15:44:46 +053062 /* I2C0_SDA */
63 PAD_CFG_NF(GPP_C16, UP_2K, DEEP, NF1),
64
65 /* I2C0_SCL */
66 PAD_CFG_NF(GPP_C17, UP_2K, DEEP, NF1),
67
Maulik V Vaghelaef5ff0b2020-03-30 20:15:01 +053068 /* WIFI_RF_KILL_N */
69 PAD_CFG_GPO(GPP_D0, 1, PLTRST),
70
71 /* BT_RF_KILL_N */
72 PAD_CFG_GPO(GPP_D1, 1, PLTRST),
73
Maulik V Vaghela733ef792020-04-21 20:21:34 +053074 /* LAN_RST_N */
Ronak Kanabard31c1502020-04-14 18:00:04 +053075 PAD_CFG_GPO(GPP_D6, 1, PLTRST),
76
Maulik V Vaghela733ef792020-04-21 20:21:34 +053077 /* AVS_I2S_MCLK */
Maulik V Vaghelad7564dc2020-03-20 15:44:46 +053078 PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
79
Maulik V Vaghela733ef792020-04-21 20:21:34 +053080 /* CNV_MFUART2_RXD */
81 PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
82
83 /* CNV_MFUART2_TXD */
84 PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
85
86 /* CNV_PA_BLANKING */
87 PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
88
Maulik V Vaghelaaa832c12020-03-27 17:38:15 +053089 /* WWAN_FCP_OFF_N */
90 PAD_CFG_GPO(GPP_E3, 1, PLTRST),
Ronak Kanabarda4272452020-03-13 12:13:54 +053091
Maulik V Vaghela733ef792020-04-21 20:21:34 +053092 /* DDI0_DDC_SCL */
93 PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
94
95 /* DDI0_DDC_SDA */
96 PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
97
98 /* DDI1_DDC_SCL */
99 PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
100
101 /* DDI1_DDC_SDA */
102 PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
103
104 /* DDI2_DDC_SCL */
105 PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
106
107 /* DDI2_DDC_SDA */
108 PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
109
110 /* CNV_BRI_DT */
111 PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
112
113 /* CNV_BRI_RSP */
114 PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
115
116 /* CNV_RGI_DT */
117 PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
118
119 /* CNV_RGI_RSP */
120 PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
121
122 /* CNV_RF_RESET_B */
123 PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
124
125 /* EMMC_CMD */
126 PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
127
128 /* EMMC_DATA0 */
129 PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
130
131 /* EMMC_DATA1 */
132 PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
133
134 /* EMMC_DATA2 */
135 PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1),
136
137 /* EMMC_DATA3 */
138 PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
139
140 /* EMMC_DATA4 */
141 PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
142
143 /* EMMC_DATA5 */
144 PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
145
146 /* EMMC_DATA6 */
147 PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
148
149 /* EMMC_DATA7 */
150 PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
151
152 /* EMMC_RCLK */
153 PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
154
155 /* EMMC_CLK */
156 PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
157
158 /* EMMC_RESET_N */
159 PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
160
161 /* SD_SDIO_CMD */
162 PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
163
164 /* SD_SDIO_D0 */
165 PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
166
167 /* SD_SDIO_D1 */
168 PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
169
170 /* SD_SDIO_D2 */
171 PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
172
173 /* SD_SDIO_D3 */
174 PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
175
176 /* SD_SDIO_CD_N */
177 PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1),
178
179 /* SD_SDIO_CLK */
180 PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
181
182 /* SD_SDIO_WP */
183 PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1),
184
185 /* FPS_INT */
Ronak Kanabard31c1502020-04-14 18:00:04 +0530186 PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, INVERT),
187
Maulik V Vaghela733ef792020-04-21 20:21:34 +0530188 /* SD_SDIO_PWR_EN_N */
189 PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
190
191 /* MODEM_CLKREQ0 */
192 PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
193
Maulik V Vaghelaaa832c12020-03-27 17:38:15 +0530194 /* WWAN EN GPIO */
195 PAD_CFG_GPO(GPP_H7, 1, PLTRST),
Ronak Kanabarda4272452020-03-13 12:13:54 +0530196
Maulik V Vaghela733ef792020-04-21 20:21:34 +0530197 /* CPU_C10_GATE_N */
198 PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
199
Maulik V Vaghelaef5ff0b2020-03-30 20:15:01 +0530200 /* M.2_BT_I2S2_SCLK */
201 PAD_CFG_GPI(GPP_H11, NONE, PLTRST),
202
Maulik V Vaghela733ef792020-04-21 20:21:34 +0530203 /* CNV_RF_RESET_N */
204 PAD_CFG_NF(GPP_H12, NONE, DEEP, NF2),
205
206 /* PCH_INT_ODL */
Ronak Kanabard31c1502020-04-14 18:00:04 +0530207 PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),
208
Maulik V Vaghelaef5ff0b2020-03-30 20:15:01 +0530209 /* M.2_BT_I2S2_RXD */
210 PAD_CFG_GPI(GPP_H14, NONE, PLTRST),
211
Maulik V Vaghela733ef792020-04-21 20:21:34 +0530212 /* AVS_I2S1_SCLK */
Maulik V Vaghelad7564dc2020-03-20 15:44:46 +0530213 PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
214
215 /* Audio Jack Detection */
216 PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, EDGE_BOTH),
217
Maulik V Vaghelaef5ff0b2020-03-30 20:15:01 +0530218 /* M2_CNVI_EN_N */
219 PAD_CFG_GPO(GPP_H19, 0, PLTRST),
220
Maulik V Vaghela733ef792020-04-21 20:21:34 +0530221 /* AVS_I2S0_SCLK */
Maulik V Vaghelad7564dc2020-03-20 15:44:46 +0530222 PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
223
Maulik V Vaghela733ef792020-04-21 20:21:34 +0530224 /* AVS_I2S0_SFRM */
Maulik V Vaghelad7564dc2020-03-20 15:44:46 +0530225 PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
226
Maulik V Vaghela733ef792020-04-21 20:21:34 +0530227 /* AVS_I2S0_TXD */
Maulik V Vaghelad7564dc2020-03-20 15:44:46 +0530228 PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
229
Maulik V Vaghela733ef792020-04-21 20:21:34 +0530230 /* AVS_I2S0_RXD */
Maulik V Vaghelad7564dc2020-03-20 15:44:46 +0530231 PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
232
Maulik V Vaghela733ef792020-04-21 20:21:34 +0530233 /* AVS_I2S1_RXD */
Maulik V Vaghelad7564dc2020-03-20 15:44:46 +0530234 PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
235
Maulik V Vaghela733ef792020-04-21 20:21:34 +0530236 /* AVS_I2S1_SFRM */
237 PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1),
Maulik V Vaghelad7564dc2020-03-20 15:44:46 +0530238
Maulik V Vaghela733ef792020-04-21 20:21:34 +0530239 /* AVS_I2S1_TXD */
240 PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1),
Maulik V Vaghelad7564dc2020-03-20 15:44:46 +0530241
Maulik V Vaghelaaa832c12020-03-27 17:38:15 +0530242 /* WWAN RST_N */
243 PAD_CFG_GPO(GPP_S0, 1, DEEP),
244
Maulik V Vaghelad7564dc2020-03-20 15:44:46 +0530245 /* DMIC_CLK_1 */
246 PAD_CFG_NF(GPP_S2, UP_20K, DEEP, NF2),
247
248 /* DMIC_DATA_1 */
249 PAD_CFG_NF(GPP_S3, UP_20K, DEEP, NF2),
250
251 /* DMIC_CLK_0 */
252 PAD_CFG_NF(GPP_S6, UP_20K, DEEP, NF2),
253
254 /* DMIC_DATA_0 */
255 PAD_CFG_NF(GPP_S7, UP_20K, DEEP, NF2),
256
Maulik V Vaghela733ef792020-04-21 20:21:34 +0530257 /* PMC_BATLOW_N */
258 PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
259
260 /* PMC_ACPRESENT */
261 PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
262
263 /* LAN_WAKE_N */
264 PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
265
266 /* PMC_PWR_BTN_N */
267 PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
268
269 /* PMC_SLP_S3_N */
270 PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
271
272 /* PMC_SLP_S4_N */
273 PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
274
275 /* PMC_SUSCLK */
276 PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
277
278 /* virtual GPIO for SD card detect */
279 PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, DEEP),
Aamir Bohra630aa4b2019-12-06 19:19:19 +0530280};
281
282/* Early pad configuration in bootblock */
283static const struct pad_config early_gpio_table[] = {
Ronak Kanabard31c1502020-04-14 18:00:04 +0530284
285 /* GSPI1_CS# */
286 PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
287
288 /* GSPI1_CLK */
289 PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
290
291 /* GSPI1_MISO */
292 PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
293
294 /* GSPI1_MOSI */
295 PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
296
Maulik V Vaghela733ef792020-04-21 20:21:34 +0530297 /* PCH_INT_ODL */
Ronak Kanabard31c1502020-04-14 18:00:04 +0530298 PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),
Aamir Bohra630aa4b2019-12-06 19:19:19 +0530299};
300
301const struct pad_config *variant_gpio_table(size_t *num)
302{
303 *num = ARRAY_SIZE(gpio_table);
304 return gpio_table;
305}
306
307const struct pad_config *variant_early_gpio_table(size_t *num)
308{
309 *num = ARRAY_SIZE(early_gpio_table);
310 return early_gpio_table;
311}
312
313static const struct cros_gpio cros_gpios[] = {
Shaunak Sahae8338da2020-01-15 11:43:19 -0800314 CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
Aamir Bohra630aa4b2019-12-06 19:19:19 +0530315};
316
317const struct cros_gpio *variant_cros_gpios(size_t *num)
318{
319 *num = ARRAY_SIZE(cros_gpios);
320 return cros_gpios;
321}