blob: ac83eb86b071234384e7d75a661dbde2613b8add [file] [log] [blame]
Arthur Heymansfbc508f2017-06-01 14:50:07 +02001##
2## This file is part of the coreboot project.
3##
Arthur Heymansfbc508f2017-06-01 14:50:07 +02004##
5## This program is free software; you can redistribute it and/or modify
6## it under the terms of the GNU General Public License as published by
7## the Free Software Foundation; version 2 of the License.
8##
9## This program is distributed in the hope that it will be useful,
10## but WITHOUT ANY WARRANTY; without even the implied warranty of
11## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12## GNU General Public License for more details.
13##
14
15# -----------------------------------------------------------------
16entries
17
18# -----------------------------------------------------------------
19# Status Register A
20# -----------------------------------------------------------------
21# Status Register B
22# -----------------------------------------------------------------
23# Status Register C
24#96 4 r 0 status_c_rsvd
25#100 1 r 0 uf_flag
26#101 1 r 0 af_flag
27#102 1 r 0 pf_flag
28#103 1 r 0 irqf_flag
29# -----------------------------------------------------------------
30# Status Register D
31#104 7 r 0 status_d_rsvd
32#111 1 r 0 valid_cmos_ram
33# -----------------------------------------------------------------
34# Diagnostic Status Register
35#112 8 r 0 diag_rsvd1
36
37# -----------------------------------------------------------------
380 120 r 0 reserved_memory
39#120 264 r 0 unused
40
41# -----------------------------------------------------------------
42# RTC_BOOT_BYTE (coreboot hardcoded)
43384 1 e 4 boot_option
44388 4 h 0 reboot_counter
45#390 5 r 0 unused?
46
47# -----------------------------------------------------------------
48# coreboot config options: console
49395 4 e 6 debug_level
50#399 1 r 0 unused
51
52# coreboot config options: southbridge
53408 1 e 1 nmi
54409 2 e 7 power_on_after_fail
55
56# coreboot config options: cpu
57#424 8 r 0 unused
58
59# coreboot config options: northbridge
60432 4 e 11 gfx_uma_size
61#435 549 r 0 unused
62
63
64# coreboot config options: check sums
65984 16 h 0 check_sum
66
671024 144 r 0 recv_enable_results
68# -----------------------------------------------------------------
69
70enumerations
71
72#ID value text
731 0 Disable
741 1 Enable
752 0 Enable
762 1 Disable
774 0 Fallback
784 1 Normal
796 1 Emergency
806 2 Alert
816 3 Critical
826 4 Error
836 5 Warning
846 6 Notice
856 7 Info
866 8 Debug
876 9 Spew
887 0 Disable
897 1 Enable
907 2 Keep
9111 6 64M
9211 7 128M
9311 8 256M
9411 9 96M
9511 10 160M
9611 11 224M
9711 12 352M
98
99# -----------------------------------------------------------------
100checksums
101
102checksum 392 983 984