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Stefan Reinauer3511b922013-06-19 12:02:47 -07001config CPU_SAMSUNG_EXYNOS5250
2 depends on ARCH_ARMV7
3 select HAVE_MONOTONIC_TIMER
4 select HAVE_UART_SPECIAL
Stefan Reinauerd2f45c62013-06-19 13:42:00 -07005 select EARLY_CONSOLE
Stefan Reinauer66287442013-06-19 15:54:19 -07006 select DYNAMIC_CBMEM
Stefan Reinauer3511b922013-06-19 12:02:47 -07007 bool
8 default n
9
10if CPU_SAMSUNG_EXYNOS5250
11
David Hendricks694719a2013-01-11 11:34:06 -080012config BOOTBLOCK_CPU_INIT
13 string
14 default "cpu/samsung/exynos5250/bootblock.c"
15 help
16 CPU/SoC-specific bootblock code. This is useful if the
17 bootblock must load microcode or copy data from ROM before
18 searching for the bootblock.
19
Hung-Te Lind63bddc2013-06-11 21:55:58 -070020# ROM image layout.
21#
22# 0x0000: vendor-provided BL1 (8k).
23# 0x2000: bootblock
24# 0x2010-0x2090: reserved for CBFS master header.
25# 0xA000: Free for CBFS data.
26
27config BOOTBLOCK_ROM_OFFSET
28 hex
29 default 0x2000
30
31config CBFS_HEADER_ROM_OFFSET
32 hex "offset of master CBFS header in ROM"
33 default 0x2010
34
35config CBFS_ROM_OFFSET
36 # Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size.
37 hex "offset of CBFS data in ROM"
38 default 0x0A000
39
David Hendricksb73d9042013-02-08 19:10:33 -080040
David Hendricks211a5d52013-01-17 20:52:21 -080041# Example SRAM/iRAM map for Exynos5250 platform:
42#
43# 0x0202_0000: vendor-provided BL1
44# 0x0202_3400: bootblock, assume up to 32KB in size
David Hendricks211a5d52013-01-17 20:52:21 -080045# 0x0203_0000: romstage, assume up to 128KB in size.
David Hendricks882fdcf2013-02-14 16:41:54 -080046# 0x0207_8000: stack pointer
Stefan Reinauer9fe20cb2012-12-07 17:18:43 -080047
David Hendricks211a5d52013-01-17 20:52:21 -080048config BOOTBLOCK_BASE
David Hendricksf1dfb2e2012-12-27 13:50:32 -080049 hex
David Hendricks211a5d52013-01-17 20:52:21 -080050 default 0x02023400
51
David Hendricks211a5d52013-01-17 20:52:21 -080052config ROMSTAGE_BASE
53 hex
54 default 0x02030000
55
56config ROMSTAGE_SIZE
57 hex
58 default 0x10000
59
David Hendricks882fdcf2013-02-14 16:41:54 -080060# Stack may reside in either IRAM or DRAM. We will define it to live
61# at the top of IRAM for now.
62#
63# Stack grows downward, push operation stores register contents in
64# consecutive memory locations ending just below SP
65config STACK_TOP
66 hex
67 default 0x02078000
68
69config STACK_BOTTOM
70 hex
71 default 0x02077000
72
73config STACK_SIZE
74 hex
75 default 0x1000
76
Hung-Te Lin6fe0cab2013-01-22 18:57:56 +080077# TODO We may probably move this to board-specific implementation files instead
78# of KConfig values.
79config CBFS_CACHE_ADDRESS
80 hex "memory address to put CBFS cache data"
81 default 0x02060000
82
83config CBFS_CACHE_SIZE
84 hex "size of CBFS cache data"
85 default 0x000017000
86
David Hendricks211a5d52013-01-17 20:52:21 -080087config SYS_SDRAM_BASE
Ronald G. Minnich836fd192013-02-20 13:24:35 -080088 hex
David Hendricks211a5d52013-01-17 20:52:21 -080089 default 0x40000000
90
Stefan Reinauer043eb0e2013-05-10 16:21:58 -070091choice CONSOLE_SERIAL_UART_CHOICES
92 prompt "Serial Console UART"
93 default CONSOLE_SERIAL_UART3
94 depends on CONSOLE_SERIAL_UART
95
96config CONSOLE_SERIAL_UART0
97 bool "UART0"
98 help
99 Serial console on UART0
100
101config CONSOLE_SERIAL_UART1
102 bool "UART1"
103 help
104 Serial console on UART1
105
106config CONSOLE_SERIAL_UART2
107 bool "UART2"
108 help
109 Serial console on UART2
110
111config CONSOLE_SERIAL_UART3
112 bool "UART3"
113 help
114 Serial console on UART3
115
116endchoice
117
118config CONSOLE_SERIAL_UART_ADDRESS
119 hex
120 depends on CONSOLE_SERIAL_UART
121 default 0x12c00000 if CONSOLE_SERIAL_UART0
122 default 0x12c10000 if CONSOLE_SERIAL_UART1
123 default 0x12c20000 if CONSOLE_SERIAL_UART2
124 default 0x12c30000 if CONSOLE_SERIAL_UART3
125 help
126 Map the UART names to the respective MMIO address.
127
Stefan Reinauer3511b922013-06-19 12:02:47 -0700128endif