| Stefan Reinauer | cc46e73 | 2009-03-13 00:44:09 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | Include ("../../../northbridge/intel/i945/acpi/i945_hostbridge.asl") |
| 23 | |
| 24 | /* PCI Device Resource Consumption */ |
| 25 | Device (PDRC) |
| 26 | { |
| 27 | Name (_HID, EISAID("PNP0C02")) |
| 28 | Name (_UID, 1) |
| 29 | Name (PDRS, ResourceTemplate() { |
| 30 | Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA |
| 31 | Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR |
| 32 | Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR |
| 33 | Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR |
| 34 | Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR |
| 35 | Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH |
| 36 | }) |
| 37 | |
| 38 | // Current Resource Settings |
| 39 | Method (_CRS, 0, Serialized) |
| 40 | { |
| 41 | CreateDwordField(PDRS, ^RCRB._BAS, RBR0) |
| 42 | ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0) |
| 43 | |
| 44 | CreateDwordField(PDRS, ^MCHB._BAS, MBR0) |
| 45 | ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0) |
| 46 | |
| 47 | CreateDwordField(PDRS, ^DMIB._BAS, DBR0) |
| 48 | ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0) |
| 49 | |
| 50 | CreateDwordField(PDRS, ^EGPB._BAS, EBR0) |
| 51 | ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0) |
| 52 | |
| 53 | CreateDwordField(PDRS, ^PCIE._BAS, PBR0) |
| 54 | ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0) |
| 55 | |
| 56 | CreateDwordField(PDRS, ^PCIE._LEN, PSZ0) |
| 57 | ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0) |
| 58 | |
| 59 | Return(PDRS) |
| 60 | } |
| 61 | } |
| 62 | |
| 63 | // PCIe graphics port 0:1.0 |
| 64 | Include ("../../../northbridge/intel/i945/acpi/i945_peg.asl") |
| 65 | |
| 66 | // Integrated graphics 0:2.0 |
| 67 | Include ("../../../northbridge/intel/i945/acpi/i945_igd.asl") |
| 68 | |
| 69 | Scope (\) |
| 70 | { |
| 71 | // backlight control, display switching, lid |
| 72 | Include ("acpi/video.asl") |
| 73 | } |