Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <console/console.h> |
| 23 | #include <delay.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include "pch.h" |
| 27 | |
| 28 | static int pch_revision_id = -1; |
| 29 | static int pch_type = -1; |
| 30 | |
| 31 | int pch_silicon_revision(void) |
| 32 | { |
| 33 | if (pch_revision_id < 0) |
| 34 | pch_revision_id = pci_read_config8( |
| 35 | dev_find_slot(0, PCI_DEVFN(0x1f, 0)), |
| 36 | PCI_REVISION_ID); |
| 37 | return pch_revision_id; |
| 38 | } |
| 39 | |
| 40 | int pch_silicon_type(void) |
| 41 | { |
| 42 | if (pch_type < 0) |
| 43 | pch_type = pci_read_config8( |
| 44 | dev_find_slot(0, PCI_DEVFN(0x1f, 0)), |
| 45 | PCI_DEVICE_ID + 1); |
| 46 | return pch_type; |
| 47 | } |
| 48 | |
| 49 | int pch_silicon_supported(int type, int rev) |
| 50 | { |
| 51 | return 1; |
| 52 | } |
| 53 | |
| 54 | /* Set bit in Function Disble register to hide this device */ |
| 55 | static void pch_hide_devfn(unsigned devfn) |
| 56 | { |
| 57 | switch (devfn) { |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 58 | case PCI_DEVFN(19, 0): /* Audio DSP */ |
| 59 | RCBA32_OR(FD, PCH_DISABLE_ADSPD); |
| 60 | break; |
| 61 | case PCI_DEVFN(20, 0): /* XHCI */ |
| 62 | RCBA32_OR(FD, PCH_DISABLE_XHCI); |
| 63 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 64 | case PCI_DEVFN(22, 0): /* MEI #1 */ |
| 65 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 66 | break; |
| 67 | case PCI_DEVFN(22, 1): /* MEI #2 */ |
| 68 | RCBA32_OR(FD2, PCH_DISABLE_MEI2); |
| 69 | break; |
| 70 | case PCI_DEVFN(22, 2): /* IDE-R */ |
| 71 | RCBA32_OR(FD2, PCH_DISABLE_IDER); |
| 72 | break; |
| 73 | case PCI_DEVFN(22, 3): /* KT */ |
| 74 | RCBA32_OR(FD2, PCH_DISABLE_KT); |
| 75 | break; |
| 76 | case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ |
| 77 | RCBA32_OR(BUC, PCH_DISABLE_GBE); |
| 78 | break; |
| 79 | case PCI_DEVFN(26, 0): /* EHCI #2 */ |
| 80 | RCBA32_OR(FD, PCH_DISABLE_EHCI2); |
| 81 | break; |
| 82 | case PCI_DEVFN(27, 0): /* HD Audio Controller */ |
| 83 | RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); |
| 84 | break; |
| 85 | case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ |
| 86 | case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ |
| 87 | case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ |
| 88 | case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ |
| 89 | case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ |
| 90 | case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ |
| 91 | case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ |
| 92 | case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ |
| 93 | RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn))); |
| 94 | break; |
| 95 | case PCI_DEVFN(29, 0): /* EHCI #1 */ |
| 96 | RCBA32_OR(FD, PCH_DISABLE_EHCI1); |
| 97 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 98 | case PCI_DEVFN(31, 0): /* LPC */ |
| 99 | RCBA32_OR(FD, PCH_DISABLE_LPC); |
| 100 | break; |
| 101 | case PCI_DEVFN(31, 2): /* SATA #1 */ |
| 102 | RCBA32_OR(FD, PCH_DISABLE_SATA1); |
| 103 | break; |
| 104 | case PCI_DEVFN(31, 3): /* SMBUS */ |
| 105 | RCBA32_OR(FD, PCH_DISABLE_SMBUS); |
| 106 | break; |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 107 | case PCI_DEVFN(31, 5): /* SATA #2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 108 | RCBA32_OR(FD, PCH_DISABLE_SATA2); |
| 109 | break; |
| 110 | case PCI_DEVFN(31, 6): /* Thermal Subsystem */ |
| 111 | RCBA32_OR(FD, PCH_DISABLE_THERMAL); |
| 112 | break; |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | #define IOBP_RETRY 1000 |
| 117 | static inline int iobp_poll(void) |
| 118 | { |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 119 | unsigned try; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 120 | |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 121 | for (try = IOBP_RETRY; try > 0; try--) { |
| 122 | u16 status = RCBA16(IOBPS); |
| 123 | if ((status & IOBPS_READY) == 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 124 | return 1; |
| 125 | udelay(10); |
| 126 | } |
| 127 | |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 128 | printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 129 | return 0; |
| 130 | } |
| 131 | |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 132 | static u32 pch_iobp_read(u32 address) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 133 | { |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 134 | u16 status; |
| 135 | |
| 136 | if (!iobp_poll()) |
| 137 | return 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 138 | |
| 139 | /* Set the address */ |
| 140 | RCBA32(IOBPIRI) = address; |
| 141 | |
| 142 | /* READ OPCODE */ |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 143 | status = RCBA16(IOBPS); |
| 144 | status &= ~IOBPS_MASK; |
| 145 | status |= IOBPS_READ; |
| 146 | RCBA16(IOBPS) = status; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 147 | |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 148 | /* Undocumented magic */ |
| 149 | RCBA16(IOBPU) = IOBPU_MAGIC; |
| 150 | |
| 151 | /* Set ready bit */ |
| 152 | status = RCBA16(IOBPS); |
| 153 | status |= IOBPS_READY; |
| 154 | RCBA16(IOBPS) = status; |
| 155 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 156 | if (!iobp_poll()) |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 157 | return 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 158 | |
| 159 | /* Check for successful transaction */ |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 160 | status = RCBA16(IOBPS); |
| 161 | if (status & IOBPS_TX_MASK) { |
| 162 | printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address); |
| 163 | return 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 164 | } |
| 165 | |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 166 | /* Read IOBP data */ |
| 167 | return RCBA32(IOBPD); |
| 168 | } |
| 169 | |
| 170 | void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) |
| 171 | { |
| 172 | u16 status; |
| 173 | u32 data = pch_iobp_read(address); |
| 174 | |
| 175 | /* WRITE OPCODE */ |
| 176 | status = RCBA16(IOBPS); |
| 177 | status &= ~IOBPS_MASK; |
| 178 | status |= IOBPS_WRITE; |
| 179 | RCBA16(IOBPS) = status; |
| 180 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 181 | /* Update the data */ |
| 182 | data &= andvalue; |
| 183 | data |= orvalue; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 184 | RCBA32(IOBPD) = data; |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 185 | |
| 186 | /* Undocumented magic */ |
| 187 | RCBA16(IOBPU) = IOBPU_MAGIC; |
| 188 | |
| 189 | /* Set ready bit */ |
| 190 | status = RCBA16(IOBPS); |
| 191 | status |= IOBPS_READY; |
| 192 | RCBA16(IOBPS) = status; |
| 193 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 194 | if (!iobp_poll()) |
| 195 | return; |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 196 | |
| 197 | /* Check for successful transaction */ |
| 198 | status = RCBA16(IOBPS); |
| 199 | if (status & IOBPS_TX_MASK) { |
| 200 | printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address); |
| 201 | return; |
| 202 | } |
| 203 | |
| 204 | printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 205 | } |
| 206 | |
| 207 | /* Check if any port in set X to X+3 is enabled */ |
| 208 | static int pch_pcie_check_set_enabled(device_t dev) |
| 209 | { |
| 210 | device_t port; |
| 211 | int port_func; |
| 212 | int dev_func = PCI_FUNC(dev->path.pci.devfn); |
| 213 | |
| 214 | printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev)); |
| 215 | |
| 216 | /* Go through static device tree list of devices |
| 217 | * because enumeration is still in progress */ |
| 218 | for (port = all_devices; port; port = port->next) { |
| 219 | /* Only care about PCIe root ports */ |
| 220 | if (PCI_SLOT(port->path.pci.devfn) != |
| 221 | PCI_SLOT(dev->path.pci.devfn)) |
| 222 | continue; |
| 223 | |
| 224 | /* Check if port is in range and enabled */ |
| 225 | port_func = PCI_FUNC(port->path.pci.devfn); |
| 226 | if (port_func >= dev_func && |
| 227 | port_func < (dev_func + 4) && |
| 228 | port->enabled) |
| 229 | return 1; |
| 230 | } |
| 231 | |
| 232 | /* None of the ports in this set are enabled */ |
| 233 | return 0; |
| 234 | } |
| 235 | |
| 236 | /* RPFN is a write-once register so keep a copy until it is written */ |
| 237 | static u32 new_rpfn; |
| 238 | |
| 239 | /* Swap function numbers assigned to two PCIe Root Ports */ |
| 240 | static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) |
| 241 | { |
| 242 | u32 old_rpfn = new_rpfn; |
| 243 | |
| 244 | printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", |
| 245 | old_fn, new_fn); |
| 246 | |
| 247 | new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn)); |
| 248 | |
| 249 | /* Old function set to new function and disabled */ |
| 250 | new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn)); |
| 251 | new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn)); |
| 252 | } |
| 253 | |
| 254 | /* Update devicetree with new Root Port function number assignment */ |
| 255 | static void pch_pcie_devicetree_update(void) |
| 256 | { |
| 257 | device_t dev; |
| 258 | |
| 259 | /* Update the function numbers in the static devicetree */ |
| 260 | for (dev = all_devices; dev; dev = dev->next) { |
| 261 | u8 new_devfn; |
| 262 | |
| 263 | /* Only care about PCH PCIe root ports */ |
| 264 | if (PCI_SLOT(dev->path.pci.devfn) != |
| 265 | PCH_PCIE_DEV_SLOT) |
| 266 | continue; |
| 267 | |
| 268 | /* Determine the new devfn for this port */ |
| 269 | new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, |
| 270 | RPFN_FNGET(new_rpfn, |
| 271 | PCI_FUNC(dev->path.pci.devfn))); |
| 272 | |
| 273 | if (dev->path.pci.devfn != new_devfn) { |
| 274 | printk(BIOS_DEBUG, |
| 275 | "PCH: PCIe map %02x.%1x -> %02x.%1x\n", |
| 276 | PCI_SLOT(dev->path.pci.devfn), |
| 277 | PCI_FUNC(dev->path.pci.devfn), |
| 278 | PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); |
| 279 | |
| 280 | dev->path.pci.devfn = new_devfn; |
| 281 | } |
| 282 | } |
| 283 | } |
| 284 | |
| 285 | /* Special handling for PCIe Root Port devices */ |
| 286 | static void pch_pcie_enable(device_t dev) |
| 287 | { |
| 288 | struct southbridge_intel_lynxpoint_config *config = dev->chip_info; |
| 289 | u32 reg32; |
| 290 | |
| 291 | /* |
| 292 | * Save a copy of the Root Port Function Number map when |
| 293 | * starting to walk the list of PCIe Root Ports so it can |
| 294 | * be updated locally and written out when the last port |
| 295 | * has been processed. |
| 296 | */ |
| 297 | if (PCI_FUNC(dev->path.pci.devfn) == 0) { |
| 298 | new_rpfn = RCBA32(RPFN); |
| 299 | |
| 300 | /* |
| 301 | * Enable Root Port coalescing if the first port is disabled |
| 302 | * or the other devices will not be enumerated by the OS. |
| 303 | */ |
| 304 | if (!dev->enabled) |
| 305 | config->pcie_port_coalesce = 1; |
| 306 | |
| 307 | if (config->pcie_port_coalesce) |
| 308 | printk(BIOS_INFO, |
| 309 | "PCH: PCIe Root Port coalescing is enabled\n"); |
| 310 | } |
| 311 | |
| 312 | if (!dev->enabled) { |
| 313 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 314 | |
| 315 | /* |
| 316 | * PCIE Power Savings for PantherPoint and CougarPoint/B1+ |
| 317 | * |
| 318 | * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 |
| 319 | * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 |
| 320 | * |
| 321 | * This check is done here instead of pcie driver |
| 322 | * because the pcie driver enable() handler is not |
| 323 | * called unless the device is enabled. |
| 324 | */ |
| 325 | if ((PCI_FUNC(dev->path.pci.devfn) == 0 || |
| 326 | PCI_FUNC(dev->path.pci.devfn) == 4)) { |
| 327 | /* Handle workaround for PPT and CPT/B1+ */ |
| 328 | if (!pch_pcie_check_set_enabled(dev)) { |
| 329 | u8 reg8 = pci_read_config8(dev, 0xe2); |
| 330 | reg8 |= 1; |
| 331 | pci_write_config8(dev, 0xe2, reg8); |
| 332 | } |
| 333 | |
| 334 | /* |
| 335 | * Enable Clock Gating for shared PCIe resources |
| 336 | * before disabling this particular port. |
| 337 | */ |
| 338 | pci_write_config8(dev, 0xe1, 0x3c); |
| 339 | } |
| 340 | |
| 341 | /* Ensure memory, io, and bus master are all disabled */ |
| 342 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 343 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 344 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 345 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 346 | |
| 347 | /* Do not claim downstream transactions for PCIe ports */ |
| 348 | new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); |
| 349 | |
| 350 | /* Hide this device if possible */ |
| 351 | pch_hide_devfn(dev->path.pci.devfn); |
| 352 | } else { |
| 353 | int fn; |
| 354 | |
| 355 | /* |
| 356 | * Check if there is a lower disabled port to swap with this |
| 357 | * port in order to maintain linear order starting at zero. |
| 358 | */ |
| 359 | if (config->pcie_port_coalesce) { |
| 360 | for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { |
| 361 | if (!(new_rpfn & RPFN_HIDE(fn))) |
| 362 | continue; |
| 363 | |
| 364 | /* Swap places with this function */ |
| 365 | pch_pcie_function_swap( |
| 366 | PCI_FUNC(dev->path.pci.devfn), fn); |
| 367 | break; |
| 368 | } |
| 369 | } |
| 370 | |
| 371 | /* Enable SERR */ |
| 372 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 373 | reg32 |= PCI_COMMAND_SERR; |
| 374 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 375 | } |
| 376 | |
| 377 | /* |
| 378 | * When processing the last PCIe root port we can now |
| 379 | * update the Root Port Function Number and Hide register. |
| 380 | */ |
| 381 | if (PCI_FUNC(dev->path.pci.devfn) == 7) { |
| 382 | printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", |
| 383 | RCBA32(RPFN), new_rpfn); |
| 384 | RCBA32(RPFN) = new_rpfn; |
| 385 | |
| 386 | /* Update static devictree with new function numbers */ |
| 387 | if (config->pcie_port_coalesce) |
| 388 | pch_pcie_devicetree_update(); |
| 389 | } |
| 390 | } |
| 391 | |
| 392 | void pch_enable(device_t dev) |
| 393 | { |
| 394 | u32 reg32; |
| 395 | |
| 396 | /* PCH PCIe Root Ports get special handling */ |
| 397 | if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) |
| 398 | return pch_pcie_enable(dev); |
| 399 | |
| 400 | if (!dev->enabled) { |
| 401 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 402 | |
| 403 | /* Ensure memory, io, and bus master are all disabled */ |
| 404 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 405 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 406 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 407 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 408 | |
| 409 | /* Hide this device if possible */ |
| 410 | pch_hide_devfn(dev->path.pci.devfn); |
| 411 | } else { |
| 412 | /* Enable SERR */ |
| 413 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 414 | reg32 |= PCI_COMMAND_SERR; |
| 415 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | struct chip_operations southbridge_intel_lynxpoint_ops = { |
| 420 | CHIP_NAME("Intel Series 8 (Lynx Point) Southbridge") |
| 421 | .enable_dev = pch_enable, |
| 422 | }; |