Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <arch/acpi.h> |
| 19 | #include <arch/io.h> |
| 20 | #include <stdint.h> |
| 21 | #include <delay.h> |
| 22 | #include <cpu/intel/haswell/haswell.h> |
| 23 | #include <cpu/x86/msr.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <device/pci_ids.h> |
| 27 | #include <device/hypertransport.h> |
| 28 | #include <stdlib.h> |
| 29 | #include <string.h> |
| 30 | #include <cpu/cpu.h> |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 31 | #include <cpu/x86/smm.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 32 | #include <boot/tables.h> |
| 33 | #include <cbmem.h> |
| 34 | #include "chip.h" |
| 35 | #include "haswell.h" |
| 36 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 37 | static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 38 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 39 | u32 pciexbar_reg; |
| 40 | |
| 41 | *base = 0; |
| 42 | *len = 0; |
| 43 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 44 | pciexbar_reg = pci_read_config32(dev, index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 45 | |
| 46 | if (!(pciexbar_reg & (1 << 0))) |
| 47 | return 0; |
| 48 | |
| 49 | switch ((pciexbar_reg >> 1) & 3) { |
| 50 | case 0: // 256MB |
| 51 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); |
| 52 | *len = 256 * 1024 * 1024; |
| 53 | return 1; |
| 54 | case 1: // 128M |
| 55 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); |
| 56 | *len = 128 * 1024 * 1024; |
| 57 | return 1; |
| 58 | case 2: // 64M |
| 59 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); |
| 60 | *len = 64 * 1024 * 1024; |
| 61 | return 1; |
| 62 | } |
| 63 | |
| 64 | return 0; |
| 65 | } |
| 66 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 67 | static void pci_domain_set_resources(device_t dev) |
| 68 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 69 | assign_resources(dev->link_list); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 70 | } |
| 71 | |
| 72 | /* TODO We could determine how many PCIe busses we need in |
| 73 | * the bar. For now that number is hardcoded to a max of 64. |
| 74 | * See e7525/northbridge.c for an example. |
| 75 | */ |
| 76 | static struct device_operations pci_domain_ops = { |
| 77 | .read_resources = pci_domain_read_resources, |
| 78 | .set_resources = pci_domain_set_resources, |
| 79 | .enable_resources = NULL, |
| 80 | .init = NULL, |
| 81 | .scan_bus = pci_domain_scan_bus, |
Kyösti Mälkki | 872c922 | 2013-07-03 09:44:28 +0300 | [diff] [blame] | 82 | .ops_pci_bus = pci_bus_default_ops, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 83 | }; |
| 84 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 85 | static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 86 | { |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 87 | u32 bar; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 88 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 89 | bar = pci_read_config32(dev, index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 90 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 91 | /* If not enabled don't report it. */ |
| 92 | if (!(bar & 0x1)) |
| 93 | return 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 94 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 95 | /* Knock down the enable bit. */ |
| 96 | *base = bar & ~1; |
| 97 | |
| 98 | return 1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 99 | } |
| 100 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 101 | /* There are special BARs that actually are programmed in the MCHBAR. These |
| 102 | * Intel special features, but they do consume resources that need to be |
| 103 | * accounted for. */ |
| 104 | static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, |
| 105 | u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 106 | { |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 107 | u32 bar; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 108 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 109 | bar = MCHBAR32(index); |
| 110 | |
| 111 | /* If not enabled don't report it. */ |
| 112 | if (!(bar & 0x1)) |
| 113 | return 0; |
| 114 | |
| 115 | /* Knock down the enable bit. */ |
| 116 | *base = bar & ~1; |
| 117 | |
| 118 | return 1; |
| 119 | } |
| 120 | |
| 121 | struct fixed_mmio_descriptor { |
| 122 | unsigned int index; |
| 123 | u32 size; |
| 124 | int (*get_resource)(device_t dev, unsigned int index, |
| 125 | u32 *base, u32 *size); |
| 126 | const char *description; |
| 127 | }; |
| 128 | |
| 129 | #define SIZE_KB(x) ((x)*1024) |
| 130 | struct fixed_mmio_descriptor mc_fixed_resources[] = { |
| 131 | { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, |
| 132 | { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, |
| 133 | { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, |
| 134 | { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, |
| 135 | { 0x5420, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, |
| 136 | { 0x5408, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, |
| 137 | }; |
| 138 | #undef SIZE_KB |
| 139 | |
| 140 | /* |
| 141 | * Add all known fixed MMIO ranges that hang off the host bridge/memory |
| 142 | * controller device. |
| 143 | */ |
| 144 | static void mc_add_fixed_mmio_resources(device_t dev) |
| 145 | { |
| 146 | int i; |
| 147 | |
| 148 | for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { |
| 149 | u32 base; |
| 150 | u32 size; |
| 151 | struct resource *resource; |
| 152 | unsigned int index; |
| 153 | |
| 154 | size = mc_fixed_resources[i].size; |
| 155 | index = mc_fixed_resources[i].index; |
| 156 | if (!mc_fixed_resources[i].get_resource(dev, index, |
| 157 | &base, &size)) |
| 158 | continue; |
| 159 | |
| 160 | resource = new_resource(dev, mc_fixed_resources[i].index); |
| 161 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
| 162 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 163 | IORESOURCE_ASSIGNED; |
| 164 | resource->base = base; |
| 165 | resource->size = size; |
| 166 | printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", |
| 167 | __func__, mc_fixed_resources[i].description, index, |
| 168 | (unsigned long)base, (unsigned long)(base + size - 1)); |
| 169 | } |
| 170 | } |
| 171 | |
| 172 | /* Host Memory Map: |
| 173 | * |
| 174 | * +--------------------------+ TOUUD |
| 175 | * | | |
| 176 | * +--------------------------+ 4GiB |
| 177 | * | PCI Address Space | |
| 178 | * +--------------------------+ TOLUD (also maps into MC address space) |
| 179 | * | iGD | |
| 180 | * +--------------------------+ BDSM |
| 181 | * | GTT | |
| 182 | * +--------------------------+ BGSM |
| 183 | * | TSEG | |
| 184 | * +--------------------------+ TSEGMB |
| 185 | * | Usage DRAM | |
| 186 | * +--------------------------+ 0 |
| 187 | * |
| 188 | * Some of the base registers above can be equal making the size of those |
| 189 | * regions 0. The reason is because the memory controller internally subtracts |
| 190 | * the base registers from each other to determine sizes of the regions. In |
| 191 | * other words, the memory map is in a fixed order no matter what. |
| 192 | */ |
| 193 | |
| 194 | struct map_entry { |
| 195 | int reg; |
| 196 | int is_64_bit; |
| 197 | int is_limit; |
| 198 | const char *description; |
| 199 | }; |
| 200 | |
| 201 | static void read_map_entry(device_t dev, struct map_entry *entry, |
| 202 | uint64_t *result) |
| 203 | { |
| 204 | uint64_t value; |
| 205 | uint64_t mask; |
| 206 | |
| 207 | /* All registers are on a 1MiB granularity. */ |
| 208 | mask = ((1ULL<<20)-1); |
| 209 | mask = ~mask; |
| 210 | |
| 211 | value = 0; |
| 212 | |
| 213 | if (entry->is_64_bit) { |
| 214 | value = pci_read_config32(dev, entry->reg + 4); |
| 215 | value <<= 32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 216 | } |
| 217 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 218 | value |= pci_read_config32(dev, entry->reg); |
| 219 | value &= mask; |
| 220 | |
| 221 | if (entry->is_limit) |
| 222 | value |= ~mask; |
| 223 | |
| 224 | *result = value; |
| 225 | } |
| 226 | |
| 227 | #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ |
| 228 | { \ |
| 229 | .reg = reg_, \ |
| 230 | .is_64_bit = is_64_, \ |
| 231 | .is_limit = is_limit_, \ |
| 232 | .description = desc_, \ |
| 233 | } |
| 234 | |
| 235 | #define MAP_ENTRY_BASE_64(reg_, desc_) \ |
| 236 | MAP_ENTRY(reg_, 1, 0, desc_) |
| 237 | #define MAP_ENTRY_LIMIT_64(reg_, desc_) \ |
| 238 | MAP_ENTRY(reg_, 1, 1, desc_) |
| 239 | #define MAP_ENTRY_BASE_32(reg_, desc_) \ |
| 240 | MAP_ENTRY(reg_, 0, 0, desc_) |
| 241 | |
| 242 | enum { |
| 243 | TOM_REG, |
| 244 | TOUUD_REG, |
| 245 | MESEG_BASE_REG, |
| 246 | MESEG_LIMIT_REG, |
| 247 | REMAP_BASE_REG, |
| 248 | REMAP_LIMIT_REG, |
| 249 | TOLUD_REG, |
| 250 | BGSM_REG, |
| 251 | BDSM_REG, |
| 252 | TSEG_REG, |
| 253 | // Must be last. |
| 254 | NUM_MAP_ENTRIES |
| 255 | }; |
| 256 | |
| 257 | static struct map_entry memory_map[NUM_MAP_ENTRIES] = { |
| 258 | [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), |
| 259 | [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), |
| 260 | [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), |
| 261 | [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), |
| 262 | [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), |
| 263 | [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), |
| 264 | [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), |
Aaron Durbin | 1570260 | 2012-12-21 22:18:58 -0600 | [diff] [blame] | 265 | [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), |
| 266 | [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 267 | [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), |
| 268 | }; |
| 269 | |
| 270 | static void mc_read_map_entries(device_t dev, uint64_t *values) |
| 271 | { |
| 272 | int i; |
| 273 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 274 | read_map_entry(dev, &memory_map[i], &values[i]); |
| 275 | } |
| 276 | } |
| 277 | |
| 278 | static void mc_report_map_entries(device_t dev, uint64_t *values) |
| 279 | { |
| 280 | int i; |
| 281 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 282 | printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", |
| 283 | memory_map[i].description, values[i]); |
| 284 | } |
| 285 | /* One can validate the BDSM and BGSM against the GGC. */ |
| 286 | printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); |
| 287 | } |
| 288 | |
| 289 | static void mc_add_dram_resources(device_t dev) |
| 290 | { |
| 291 | unsigned long base_k, size_k; |
Aaron Durbin | 27435d3 | 2013-06-03 09:46:56 -0500 | [diff] [blame] | 292 | unsigned long touud_k; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 293 | unsigned long index; |
| 294 | struct resource *resource; |
| 295 | uint64_t mc_values[NUM_MAP_ENTRIES]; |
| 296 | |
| 297 | /* Read in the MAP registers and report their values. */ |
| 298 | mc_read_map_entries(dev, &mc_values[0]); |
| 299 | mc_report_map_entries(dev, &mc_values[0]); |
| 300 | |
| 301 | /* |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 302 | * These are the host memory ranges that should be added: |
Aaron Durbin | 6a36004 | 2014-02-13 10:30:42 -0600 | [diff] [blame] | 303 | * - 0 -> 0xa0000: cacheable |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 304 | * - 0xc0000 -> TSEG : cacheable |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 305 | * - TESG -> BGSM: cacheable with standard MTRRs and reserved |
| 306 | * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 307 | * - 4GiB -> TOUUD: cacheable |
| 308 | * |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 309 | * The default SMRAM space is reserved so that the range doesn't |
| 310 | * have to be saved during S3 Resume. Once marked reserved the OS |
| 311 | * cannot use the memory. This is a bit of an odd place to reserve |
| 312 | * the region, but the CPU devices don't have dev_ops->read_resources() |
| 313 | * called on them. |
| 314 | * |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 315 | * The range 0xa0000 -> 0xc0000 does not have any resources |
| 316 | * associated with it to handle legacy VGA memory. If this range |
| 317 | * is not omitted the mtrr code will setup the area as cacheable |
| 318 | * causing VGA access to not work. |
| 319 | * |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 320 | * The TSEG region is mapped as cacheable so that one can perform |
| 321 | * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes |
| 322 | * precedence over the existing MTRRs covering this region. |
| 323 | * |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 324 | * It should be noted that cacheable entry types need to be added in |
| 325 | * order. The reason is that the current MTRR code assumes this and |
| 326 | * falls over itself if it isn't. |
| 327 | * |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 328 | * The resource index starts low and should not meet or exceed |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 329 | * PCI_BASE_ADDRESS_0. |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 330 | */ |
| 331 | index = 0; |
| 332 | |
Aaron Durbin | 6a36004 | 2014-02-13 10:30:42 -0600 | [diff] [blame] | 333 | /* 0 - > 0xa0000 */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 334 | base_k = 0; |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 335 | size_k = (0xa0000 >> 10) - base_k; |
| 336 | ram_resource(dev, index++, base_k, size_k); |
| 337 | |
| 338 | /* 0xc0000 -> TSEG */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 339 | base_k = 0xc0000 >> 10; |
| 340 | size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; |
| 341 | ram_resource(dev, index++, base_k, size_k); |
| 342 | |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 343 | /* TSEG -> BGSM */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 344 | resource = new_resource(dev, index++); |
| 345 | resource->base = mc_values[TSEG_REG]; |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 346 | resource->size = mc_values[BGSM_REG] - resource->base; |
| 347 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
| 348 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 349 | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; |
| 350 | |
| 351 | /* BGSM -> TOLUD */ |
| 352 | resource = new_resource(dev, index++); |
| 353 | resource->base = mc_values[BGSM_REG]; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 354 | resource->size = mc_values[TOLUD_REG] - resource->base; |
| 355 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
| 356 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 357 | IORESOURCE_ASSIGNED; |
| 358 | |
| 359 | /* 4GiB -> TOUUD */ |
| 360 | base_k = 4096 * 1024; /* 4GiB */ |
Aaron Durbin | 27435d3 | 2013-06-03 09:46:56 -0500 | [diff] [blame] | 361 | touud_k = mc_values[TOUUD_REG] >> 10; |
| 362 | size_k = touud_k - base_k; |
| 363 | if (touud_k > base_k) |
Aaron Durbin | 5c66f08 | 2013-01-08 10:10:33 -0600 | [diff] [blame] | 364 | ram_resource(dev, index++, base_k, size_k); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 365 | |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 366 | /* Reserve everything between A segment and 1MB: |
| 367 | * |
| 368 | * 0xa0000 - 0xbffff: legacy VGA |
| 369 | * 0xc0000 - 0xfffff: RAM |
| 370 | */ |
| 371 | mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); |
| 372 | reserved_ram_resource(dev, index++, (0xc0000 >> 10), |
| 373 | (0x100000 - 0xc0000) >> 10); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 374 | #if CONFIG_CHROMEOS_RAMOOPS |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 375 | reserved_ram_resource(dev, index++, |
| 376 | CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 377 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); |
| 378 | #endif |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 379 | } |
| 380 | |
| 381 | static void mc_read_resources(device_t dev) |
| 382 | { |
| 383 | /* Read standard PCI resources. */ |
| 384 | pci_dev_read_resources(dev); |
| 385 | |
| 386 | /* Add all fixed MMIO resources. */ |
| 387 | mc_add_fixed_mmio_resources(dev); |
| 388 | |
| 389 | /* Calculate and add DRAM resources. */ |
| 390 | mc_add_dram_resources(dev); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 391 | } |
| 392 | |
| 393 | static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 394 | { |
| 395 | if (!vendor || !device) { |
| 396 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 397 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 398 | } else { |
| 399 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 400 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 401 | } |
| 402 | } |
| 403 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 404 | static void northbridge_init(struct device *dev) |
| 405 | { |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 406 | u8 bios_reset_cpl, pair; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 407 | |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 408 | /* Enable Power Aware Interrupt Routing */ |
| 409 | pair = MCHBAR8(0x5418); |
| 410 | pair &= ~0x7; /* Clear 2:0 */ |
| 411 | pair |= 0x4; /* Fixed Priority */ |
| 412 | MCHBAR8(0x5418) = pair; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 413 | |
| 414 | /* |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 415 | * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 416 | * that BIOS has initialized memory and power management |
| 417 | */ |
| 418 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 419 | bios_reset_cpl |= 3; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 420 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 421 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 422 | |
| 423 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 424 | mdelay(1); |
| 425 | set_power_limits(28); |
| 426 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 427 | /* Set here before graphics PM init */ |
| 428 | MCHBAR32(0x5500) = 0x00100001; |
| 429 | } |
| 430 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 431 | static struct pci_operations intel_pci_ops = { |
| 432 | .set_subsystem = intel_set_subsystem, |
| 433 | }; |
| 434 | |
| 435 | static struct device_operations mc_ops = { |
| 436 | .read_resources = mc_read_resources, |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 437 | .set_resources = pci_dev_set_resources, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 438 | .enable_resources = pci_dev_enable_resources, |
| 439 | .init = northbridge_init, |
Vladimir Serbinenko | 0a66991 | 2014-10-05 14:34:17 +0200 | [diff] [blame] | 440 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 441 | .scan_bus = 0, |
| 442 | .ops_pci = &intel_pci_ops, |
| 443 | }; |
| 444 | |
Aaron Durbin | c1989c4 | 2012-12-11 17:13:17 -0600 | [diff] [blame] | 445 | static const struct pci_driver mc_driver_hsw_mobile __pci_driver = { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 446 | .ops = &mc_ops, |
| 447 | .vendor = PCI_VENDOR_ID_INTEL, |
Aaron Durbin | 21efd8c | 2013-01-17 09:39:39 -0600 | [diff] [blame] | 448 | .device = PCI_DEVICE_ID_HSW_MOBILE, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 449 | }; |
| 450 | |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 451 | static const struct pci_driver mc_driver_hsw_ult __pci_driver = { |
| 452 | .ops = &mc_ops, |
| 453 | .vendor = PCI_VENDOR_ID_INTEL, |
Aaron Durbin | 21efd8c | 2013-01-17 09:39:39 -0600 | [diff] [blame] | 454 | .device = PCI_DEVICE_ID_HSW_ULT, |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 455 | }; |
| 456 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 457 | static void cpu_bus_init(device_t dev) |
| 458 | { |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 459 | bsp_init_and_start_aps(dev->link_list); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 460 | } |
| 461 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 462 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 9f74462 | 2014-10-31 08:12:34 +1100 | [diff] [blame] | 463 | .read_resources = DEVICE_NOOP, |
| 464 | .set_resources = DEVICE_NOOP, |
| 465 | .enable_resources = DEVICE_NOOP, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 466 | .init = cpu_bus_init, |
| 467 | .scan_bus = 0, |
| 468 | }; |
| 469 | |
| 470 | static void enable_dev(device_t dev) |
| 471 | { |
| 472 | /* Set the operations if it is a special bus type */ |
| 473 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 474 | dev->ops = &pci_domain_ops; |
| 475 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 476 | dev->ops = &cpu_bus_ops; |
| 477 | } |
| 478 | } |
| 479 | |
| 480 | struct chip_operations northbridge_intel_haswell_ops = { |
| 481 | CHIP_NAME("Intel i7 (Haswell) integrated Northbridge") |
| 482 | .enable_dev = enable_dev, |
| 483 | }; |