Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #ifndef __SANDYBRIDGE_MCHBAR_REGS_H__ |
| 18 | #define __SANDYBRIDGE_MCHBAR_REGS_H__ |
| 19 | |
| 20 | /* |
| 21 | * ### IOSAV command queue notes ### |
| 22 | * |
| 23 | * Intel provides a command queue of depth four. |
| 24 | * Every command is configured by using multiple MCHBAR registers. |
| 25 | * On executing the command queue, you have to specify its depth (number of commands). |
| 26 | * |
| 27 | * The macros for these registers can take some integer parameters, within these bounds: |
| 28 | * channel: [0..1] |
| 29 | * index: [0..3] |
| 30 | * lane: [0..8] |
| 31 | * |
| 32 | * Note that these ranges are 'closed': both endpoints are included. |
| 33 | * |
| 34 | * |
| 35 | * |
| 36 | * ### Register description ### |
| 37 | * |
| 38 | * IOSAV_n_SP_CMD_ADDR_ch(channel, index) |
| 39 | * Sub-sequence command addresses. Controls the address, bank address and slotrank signals. |
| 40 | * |
| 41 | * Bitfields: |
| 42 | * [0..15] Row / Column Address. |
| 43 | * [16..18] The result of (10 + [16..18]) is the number of valid row bits. |
| 44 | * Note: Value 1 is not implemented. Not that it really matters, though. |
| 45 | * Value 7 is reserved, as the hardware does not support it. |
| 46 | * [20..22] Bank Address. |
| 47 | * [24..25] Rank select. Let's call it "ranksel", as it is mentioned later. |
| 48 | * |
| 49 | * IOSAV_n_ADDR_UPDATE_ch(channel, index) |
| 50 | * How the address shall be updated after executing the sub-sequence command. |
| 51 | * |
| 52 | * Bitfields: |
| 53 | * [0] Increment CAS/RAS by 1. |
| 54 | * [1] Increment CAS/RAS by 8. |
| 55 | * [2] Increment bank select by 1. |
| 56 | * [3..4] Increment rank select by 1, 2 or 3. |
| 57 | * [5..9] Known as "addr_wrap". Address bits will wrap around the [addr_wrap..0] range. |
| 58 | * [10..11] LFSR update: |
| 59 | * 00: Do not use the LFSR function. |
| 60 | * 01: Undefined, treat as Reserved. |
| 61 | * 10: Apply LFSR on the [addr_wrap..0] bit range. |
| 62 | * 11: Apply LFSR on the [addr_wrap..3] bit range. |
| 63 | * |
| 64 | * [12..15] Update rate. The number of command runs between address updates. For example: |
| 65 | * 0: Update every command run. |
| 66 | * 1: Update every second command run. That is, half of the command rate. |
| 67 | * N: Update after N command runs without updates. |
| 68 | * |
| 69 | * [16..17] LFSR behavior on the deselect cycles (when no sub-seq command is issued): |
| 70 | * 0: No change w.r.t. the last issued command. |
| 71 | * 1: LFSR XORs with address & command (excluding CS), but does not update. |
| 72 | * 2: LFSR XORs with address & command (excluding CS), and updates. |
| 73 | * |
| 74 | * IOSAV_n_SP_CMD_CTRL_ch(channel, index) |
| 75 | * Special command control register. Controls the DRAM command signals. |
| 76 | * |
| 77 | * Bitfields: |
| 78 | * [0] !RAS signal. |
| 79 | * [1] !CAS signal. |
| 80 | * [2] !WE signal. |
| 81 | * [4..7] CKE, per rank and channel. |
| 82 | * [8..11] ODT, per rank and channel. |
| 83 | * [12] Chip Select mode control. |
| 84 | * [13..16] Chip select, per rank and channel. It works as follows: |
| 85 | * |
| 86 | * entity CS_BLOCK is |
| 87 | * port ( |
| 88 | * MODE : in std_logic; -- Mode select at [12] |
| 89 | * RANKSEL : in std_logic_vector(0 to 3); -- Decoded "ranksel" value |
| 90 | * CS_CTL : in std_logic_vector(0 to 3); -- Chip select control at [13..16] |
| 91 | * CS_Q : out std_logic_vector(0 to 3) -- CS signals |
| 92 | * ); |
| 93 | * end entity CS_BLOCK; |
| 94 | * |
| 95 | * architecture RTL of CS_BLOCK is |
| 96 | * begin |
| 97 | * if MODE = '1' then |
| 98 | * CS_Q <= not RANKSEL and CS_CTL; |
| 99 | * else |
| 100 | * CS_Q <= CS_CTL; |
| 101 | * end if; |
| 102 | * end architecture RTL; |
| 103 | * |
| 104 | * [17] Auto Precharge. Only valid when using 10 row bits! |
| 105 | * |
| 106 | * IOSAV_n_SUBSEQ_CTRL_ch(channel, index) |
| 107 | * Sub-sequence parameters. Controls repetititons, delays and data orientation. |
| 108 | * |
| 109 | * Bitfields: |
| 110 | * [0..8] Number of repetitions of the sub-sequence command. |
| 111 | * [10..14] Gap, number of clock-cycles to wait before sending the next command. |
| 112 | * [16..24] Number of clock-cycles to idle between sub-sequence commands. |
| 113 | * [26..27] The direction of the data. |
| 114 | * 00: None, does not handle data |
| 115 | * 01: Read |
| 116 | * 10: Write |
| 117 | * 11: Read & Write |
| 118 | * |
| 119 | * IOSAV_n_ADDRESS_LFSR_ch(channel, index) |
| 120 | * 23-bit LFSR state register. It is written into the LFSR when the sub-sequence is loaded, |
| 121 | * and then read back from the LFSR when the sub-sequence is done. |
| 122 | * |
| 123 | * Bitfields: |
| 124 | * [0..22] LFSR state. |
| 125 | * |
| 126 | * IOSAV_SEQ_CTL_ch(channel) |
| 127 | * Control the sequence level in IOSAV: number of sub-sequences, iterations, maintenance... |
| 128 | * |
| 129 | * Bitfields: |
| 130 | * [0..7] Number of full sequence executions. When this field becomes non-zero, then the |
| 131 | * sequence starts running immediately. This value is decremented after completing |
| 132 | * a full sequence iteration. When it is zero, the sequence is done. No decrement |
| 133 | * is done if this field is set to 0xff. This is the "infinite repeat" mode, and |
| 134 | * it is manually aborted by clearing this field. |
| 135 | * |
| 136 | * [8..16] Number of wait cycles after each sequence iteration. This wait's purpose is to |
| 137 | * allow performing maintenance in infinite loops. When non-zero, RCOMP, refresh |
| 138 | * and ZQXS operations can take place. |
| 139 | * |
| 140 | * [17] Stop-on-error mode: Whether to stop sequence execution when an error occurs. |
| 141 | * [18..19] Number of sub-sequences. The programmed value is the index of the last sub-seq. |
| 142 | * [20] If set, keep refresh disabled until the next sequence execution. |
| 143 | * DANGER: Refresh must be re-enabled within the (9 * tREFI) period! |
| 144 | * |
| 145 | * [22] If set, sequence execution will not prevent refresh. This cannot be set when |
| 146 | * bit [20] is also set, or was set on the previous sequence. This bit exists so |
| 147 | * that the sequence machine can be used as a timer without affecting the memory. |
| 148 | * |
| 149 | * [23] If set, a output pin is asserted on the first detected error. This output can |
| 150 | * be used as a trigger for an oscilloscope or a logic analyzer, which is handy. |
| 151 | * |
| 152 | * IOSAV_DATA_CTL_ch(channel) |
| 153 | * Data-related controls in IOSAV mode. |
| 154 | * |
| 155 | * Bitfields: |
| 156 | * [0..7] WDB (Write Data Buffer) pattern length: [0..7] = (length / 8) - 1; |
| 157 | * [8..15] WDB read pointer. Points at the data used for IOSAV write transactions. |
| 158 | * [16..23] Comparison pointer. Used to compare data from IOSAV read transactions. |
| 159 | * [24] If set, increment pointers only when micro-breakpoint is active. |
| 160 | * |
| 161 | * IOSAV_STATUS_ch(channel) |
| 162 | * State of the IOSAV sequence machine. Should be polled after sending an IOSAV sequence. |
| 163 | * |
| 164 | * Bitfields: |
| 165 | * [0] IDLE: IOSAV is sleeping. |
| 166 | * [1] BUSY: IOSAV is running a sequence. |
| 167 | * [2] DONE: IOSAV has completed a sequence. |
| 168 | * [3] ERROR: IOSAV detected an error and stopped on it, when using Stop-on-error. |
| 169 | * [4] PANIC: The refresh machine issued a Panic Refresh, and IOSAV was aborted. |
| 170 | * [5] RCOMP: RComp failure. Unused, consider Reserved. |
| 171 | * [6] Cleared with a new sequence, and set when done and refresh counter is drained. |
| 172 | * |
| 173 | */ |
| 174 | |
| 175 | /* Indexed register helper macros */ |
| 176 | #define Gz(r, z) ((r) + ((z) << 8)) |
| 177 | #define Ly(r, y) ((r) + ((y) << 2)) |
| 178 | #define Cx(r, x) ((r) + ((x) << 10)) |
| 179 | #define CxLy(r, x, y) ((r) + ((x) << 10) + ((y) << 2)) |
| 180 | #define GzLy(r, z, y) ((r) + ((z) << 8) + ((y) << 2)) |
| 181 | |
| 182 | /* Byte lane training register base addresses */ |
| 183 | #define LANEBASE_B0 0x0000 |
| 184 | #define LANEBASE_B1 0x0200 |
| 185 | #define LANEBASE_B2 0x0400 |
| 186 | #define LANEBASE_B3 0x0600 |
| 187 | #define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */ |
| 188 | #define LANEBASE_B4 0x1000 |
| 189 | #define LANEBASE_B5 0x1200 |
| 190 | #define LANEBASE_B6 0x1400 |
| 191 | #define LANEBASE_B7 0x1600 |
| 192 | |
| 193 | /* Byte lane register offsets */ |
| 194 | #define GDCRTRAININGRESULT(ch, y) GzLy(0x0004, ch, y) /* Test results for PI config */ |
| 195 | #define GDCRTRAININGRESULT1(ch) GDCRTRAININGRESULT(ch, 0) /* 0x0004 */ |
| 196 | #define GDCRTRAININGRESULT2(ch) GDCRTRAININGRESULT(ch, 1) /* 0x0008 */ |
| 197 | #define GDCRRX(ch, rank) GzLy(0x10, ch, rank) /* Time setting for lane Rx */ |
| 198 | #define GDCRTX(ch, rank) GzLy(0x20, ch, rank) /* Time setting for lane Tx */ |
| 199 | |
| 200 | /* Register definitions */ |
| 201 | #define GDCRCLKRANKSUSED_ch(ch) Gz(0x0c00, ch) /* Indicates which rank is populated */ |
| 202 | #define GDCRCLKCOMP_ch(ch) Gz(0x0c04, ch) /* RCOMP result register */ |
| 203 | #define GDCRCKPICODE_ch(ch) Gz(0x0c14, ch) /* PI coding for DDR CLK pins */ |
| 204 | #define GDCRCKLOGICDELAY_ch(ch) Gz(0x0c18, ch) /* Logic delay of 1 QCLK in CLK slice */ |
| 205 | #define GDDLLFUSE_ch(ch) Gz(0x0c20, ch) /* Used for fuse download to the DLLs */ |
| 206 | #define GDCRCLKDEBUGMUXCFG_ch(ch) Gz(0x0c3c, ch) /* Debug MUX control */ |
| 207 | |
| 208 | #define GDCRCMDDEBUGMUXCFG_Cz_S(ch) Gz(0x0e3c, ch) /* Debug MUX control */ |
| 209 | |
| 210 | #define CRCOMPOFST1_ch(ch) Gz(0x1810, ch) /* DQ, CTL and CLK Offset values */ |
| 211 | |
| 212 | #define GDCRTRAININGMOD_ch(ch) Gz(0x3000, ch) /* Data training mode control */ |
| 213 | #define GDCRTRAININGRESULT1_ch(ch) Gz(0x3004, ch) /* Training results according to PI */ |
| 214 | #define GDCRTRAININGRESULT2_ch(ch) Gz(0x3008, ch) |
| 215 | |
| 216 | #define GDCRCTLRANKSUSED_ch(ch) Gz(0x3200, ch) /* Indicates which rank is populated */ |
| 217 | #define GDCRCMDCOMP_ch(ch) Gz(0x3204, ch) /* COMP values register */ |
| 218 | #define GDCRCMDCTLCOMP_ch(ch) Gz(0x3208, ch) /* COMP values register */ |
| 219 | #define GDCRCMDPICODING_ch(ch) Gz(0x320c, ch) /* Command and control PI coding */ |
| 220 | |
| 221 | #define GDCRTRAININGMOD 0x3400 /* Data training mode control register */ |
| 222 | #define GDCRDATACOMP 0x340c /* COMP values register */ |
| 223 | |
| 224 | #define CRCOMPOFST2 0x3714 /* CMD DRV, SComp and Static Leg controls */ |
| 225 | |
| 226 | /* MC per-channel registers */ |
| 227 | #define TC_DBP_ch(ch) Cx(0x4000, ch) /* Timings: BIN */ |
| 228 | #define TC_RAP_ch(ch) Cx(0x4004, ch) /* Timings: Regular access */ |
| 229 | #define TC_RWP_ch(ch) Cx(0x4008, ch) /* Timings: Read / Write */ |
| 230 | #define TC_OTHP_ch(ch) Cx(0x400c, ch) /* Timings: Other parameters */ |
| 231 | #define SCHED_SECOND_CBIT_ch(ch) Cx(0x401c, ch) /* More chicken bits */ |
| 232 | #define SCHED_CBIT_ch(ch) Cx(0x4020, ch) /* Chicken bits in scheduler */ |
| 233 | #define SC_ROUNDT_LAT_ch(ch) Cx(0x4024, ch) /* Round-trip latency per rank */ |
| 234 | #define SC_IO_LATENCY_ch(ch) Cx(0x4028, ch) /* IO Latency Configuration */ |
| 235 | #define SCRAMBLING_SEED_1_ch(ch) Cx(0x4034, ch) /* Scrambling seed 1 */ |
| 236 | #define SCRAMBLING_SEED_2_LO_ch(ch) Cx(0x4038, ch) /* Scrambling seed 2 low */ |
| 237 | #define SCRAMBLING_SEED_2_HI_ch(ch) Cx(0x403c, ch) /* Scrambling seed 2 high */ |
| 238 | |
| 239 | /* IOSAV Bytelane Bit-wise error */ |
| 240 | #define IOSAV_By_BW_SERROR_ch(ch, y) CxLy(0x4040, ch, y) |
| 241 | |
| 242 | /* IOSAV Bytelane Bit-wise compare mask */ |
| 243 | #define IOSAV_By_BW_MASK_ch(ch, y) CxLy(0x4080, ch, y) |
| 244 | |
| 245 | /* |
| 246 | * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. |
| 247 | * Different counters for transactions that are issued on the ring agents (core or GT) and |
| 248 | * transactions issued in the SA. |
| 249 | */ |
| 250 | #define SC_PR_CNT_CONFIG_ch(ch) Cx(0x40a8, ch) |
| 251 | #define SC_PCIT_ch(ch) Cx(0x40ac, ch) /* Page-close idle timer setup - 8 bits */ |
| 252 | #define PM_PDWN_CONFIG_ch(ch) Cx(0x40b0, ch) /* Power-down (CKE-off) operation config */ |
| 253 | #define ECC_INJECT_COUNT_ch(ch) Cx(0x40b4, ch) /* ECC error injection count */ |
| 254 | #define ECC_DFT_ch(ch) Cx(0x40b8, ch) /* ECC DFT features (ECC4ANA, error inject) */ |
| 255 | #define SC_WR_ADD_DELAY_ch(ch) Cx(0x40d0, ch) /* Extra WR delay to overcome WR-flyby issue */ |
| 256 | |
| 257 | #define IOSAV_By_BW_SERROR_C_ch(ch, y) CxLy(0x4140, ch, y) /* IOSAV Bytelane Bit-wise error */ |
| 258 | |
| 259 | /* IOSAV sub-sequence control registers */ |
| 260 | #define IOSAV_n_SP_CMD_ADDR_ch(ch, y) CxLy(0x4200, ch, y) /* Special command address. */ |
| 261 | #define IOSAV_n_ADDR_UPDATE_ch(ch, y) CxLy(0x4210, ch, y) /* Address update control */ |
| 262 | #define IOSAV_n_SP_CMD_CTRL_ch(ch, y) CxLy(0x4220, ch, y) /* Control of command signals */ |
| 263 | #define IOSAV_n_SUBSEQ_CTRL_ch(ch, y) CxLy(0x4230, ch, y) /* Sub-sequence controls */ |
| 264 | #define IOSAV_n_ADDRESS_LFSR_ch(ch, y) CxLy(0x4240, ch, y) /* 23-bit LFSR state value */ |
| 265 | |
| 266 | #define PM_THML_STAT_ch(ch) Cx(0x4280, ch) /* Thermal status of each rank */ |
| 267 | #define IOSAV_SEQ_CTL_ch(ch) Cx(0x4284, ch) /* IOSAV sequence level control */ |
| 268 | #define IOSAV_DATA_CTL_ch(ch) Cx(0x4288, ch) /* Data control in IOSAV mode */ |
| 269 | #define IOSAV_STATUS_ch(ch) Cx(0x428c, ch) /* State of the IOSAV sequence machine */ |
| 270 | #define TC_ZQCAL_ch(ch) Cx(0x4290, ch) /* ZQCAL control register */ |
| 271 | #define TC_RFP_ch(ch) Cx(0x4294, ch) /* Refresh Parameters */ |
| 272 | #define TC_RFTP_ch(ch) Cx(0x4298, ch) /* Refresh Timing Parameters */ |
| 273 | #define TC_MR2_SHADOW_ch(ch) Cx(0x429c, ch) /* MR2 shadow - copy of DDR configuration */ |
| 274 | #define MC_INIT_STATE_ch(ch) Cx(0x42a0, ch) /* IOSAV mode control */ |
| 275 | #define TC_SRFTP_ch(ch) Cx(0x42a4, ch) /* Self-refresh timing parameters */ |
| 276 | #define IOSAV_ERROR_ch(ch) Cx(0x42ac, ch) /* Data vector count of the first error */ |
| 277 | #define IOSAV_DC_MASK_ch(ch) Cx(0x42b0, ch) /* IOSAV data check masking */ |
| 278 | |
| 279 | #define IOSAV_By_ERROR_COUNT_ch(ch, y) CxLy(0x4340, ch, y) /* Per-byte 16-bit error count */ |
| 280 | #define IOSAV_G_ERROR_COUNT_ch(ch) Cx(0x4364, ch) /* Global 16-bit error count */ |
| 281 | |
| 282 | /** WARNING: Only applies to Ivy Bridge! */ |
| 283 | #define IOSAV_BYTE_SERROR_ch(ch) Cx(0x4368, ch) /** Byte-Wise Sticky Error */ |
| 284 | #define IOSAV_BYTE_SERROR_C_ch(ch) Cx(0x436c, ch) /** Byte-Wise Sticky Error Clear */ |
| 285 | |
| 286 | #define PM_TRML_M_CONFIG_ch(ch) Cx(0x4380, ch) /* Thermal mode configuration */ |
| 287 | #define PM_CMD_PWR_ch(ch) Cx(0x4384, ch) /* Power contribution of commands */ |
| 288 | #define PM_BW_LIMIT_CONFIG_ch(ch) Cx(0x4388, ch) /* Bandwidth throttling on overtemp */ |
| 289 | #define SC_WDBWM_ch(ch) Cx(0x438c, ch) /* Watermarks and starvation counter */ |
| 290 | |
| 291 | /* MC Channel Broadcast registers */ |
| 292 | #define TC_DBP 0x4c00 /* Timings: BIN */ |
| 293 | #define TC_RAP 0x4c04 /* Timings: Regular access */ |
| 294 | #define TC_RWP 0x4c08 /* Timings: Read / Write */ |
| 295 | #define TC_OTHP 0x4c0c /* Timings: Other parameters */ |
| 296 | #define SCHED_SECOND_CBIT 0x4c1c /* More chicken bits */ |
| 297 | #define SCHED_CBIT 0x4c20 /* Chicken bits in scheduler */ |
| 298 | #define SC_ROUNDT_LAT 0x4c24 /* Round-trip latency per rank */ |
| 299 | #define SC_IO_LATENCY 0x4c28 /* IO Latency Configuration */ |
| 300 | #define SCRAMBLING_SEED_1 0x4c34 /* Scrambling seed 1 */ |
| 301 | #define SCRAMBLING_SEED_2_LO 0x4c38 /* Scrambling seed 2 low */ |
| 302 | #define SCRAMBLING_SEED_2_HI 0x4c3c /* Scrambling seed 2 high */ |
| 303 | |
| 304 | #define IOSAV_By_BW_SERROR(y) Ly(0x4c40, y) /* IOSAV Bytelane Bit-wise error */ |
| 305 | #define IOSAV_By_BW_MASK(y) Ly(0x4c80, y) /* IOSAV Bytelane Bit-wise compare mask */ |
| 306 | |
| 307 | /* |
| 308 | * Defines the number of transactions (non-VC1 RD CAS commands) between two priority ticks. |
| 309 | * Different counters for transactions that are issued on the ring agents (core or GT) and |
| 310 | * transactions issued in the SA. |
| 311 | */ |
| 312 | #define SC_PR_CNT_CONFIG 0x4ca8 |
| 313 | #define SC_PCIT 0x4cac /* Page-close idle timer setup - 8 bits */ |
| 314 | #define PM_PDWN_CONFIG 0x4cb0 /* Power-down (CKE-off) operation config */ |
| 315 | #define ECC_INJECT_COUNT 0x4cb4 /* ECC error injection count */ |
| 316 | #define ECC_DFT 0x4cb8 /* ECC DFT features (ECC4ANA, error inject) */ |
| 317 | #define SC_WR_ADD_DELAY 0x4cd0 /* Extra WR delay to overcome WR-flyby issue */ |
| 318 | |
| 319 | /** Opportunistic reads configuration during write-major-mode (WMM) */ |
| 320 | #define WMM_READ_CONFIG 0x4cd4 /** WARNING: Only exists on IVB! */ |
| 321 | |
| 322 | #define IOSAV_By_BW_SERROR_C(y) Ly(0x4d40, y) /* IOSAV Bytelane Bit-wise error */ |
| 323 | |
| 324 | #define IOSAV_n_SP_CMD_ADDR(n) Ly(0x4e00, n) /* Sub-sequence special command address */ |
| 325 | #define IOSAV_n_ADDR_UPDATE(n) Ly(0x4e10, n) /* Address update after command execution */ |
| 326 | #define IOSAV_n_SP_CMD_CTRL(n) Ly(0x4e20, n) /* Command signals in sub-sequence command */ |
| 327 | #define IOSAV_n_SUBSEQ_CTRL(n) Ly(0x4e30, n) /* Sub-sequence command parameter control */ |
| 328 | #define IOSAV_n_ADDRESS_LFSR(n) Ly(0x4e40, n) /* 23-bit LFSR value of the sequence */ |
| 329 | |
| 330 | #define PM_THML_STAT 0x4e80 /* Thermal status of each rank */ |
| 331 | #define IOSAV_SEQ_CTL 0x4e84 /* IOSAV sequence level control */ |
| 332 | #define IOSAV_DATA_CTL 0x4e88 /* Data control in IOSAV mode */ |
| 333 | #define IOSAV_STATUS 0x4e8c /* State of the IOSAV sequence machine */ |
| 334 | #define TC_ZQCAL 0x4e90 /* ZQCAL control register */ |
| 335 | #define TC_RFP 0x4e94 /* Refresh Parameters */ |
| 336 | #define TC_RFTP 0x4e98 /* Refresh Timing Parameters */ |
| 337 | #define TC_MR2_SHADOW 0x4e9c /* MR2 shadow - copy of DDR configuration */ |
| 338 | #define MC_INIT_STATE 0x4ea0 /* IOSAV mode control */ |
| 339 | #define TC_SRFTP 0x4ea4 /* Self-refresh timing parameters */ |
| 340 | |
| 341 | /** |
| 342 | * Auxiliary register in mcmnts synthesis FUB (Functional Unit Block). Additionally, this |
| 343 | * register is also used to enable IOSAV_n_SP_CMD_ADDR optimization on Ivy Bridge. |
| 344 | */ |
| 345 | #define MCMNTS_SPARE 0x4ea8 /** WARNING: Reserved, use only on IVB! */ |
| 346 | |
| 347 | #define IOSAV_ERROR 0x4eac /* Data vector count of the first error */ |
| 348 | #define IOSAV_DC_MASK 0x4eb0 /* IOSAV data check masking */ |
| 349 | |
| 350 | #define IOSAV_By_ERROR_COUNT(y) Ly(0x4f40, y) /* Per-byte 16-bit error counter */ |
| 351 | #define IOSAV_G_ERROR_COUNT 0x4f64 /* Global 16-bit error counter */ |
| 352 | |
| 353 | /** WARNING: Only applies to Ivy Bridge! */ |
| 354 | #define IOSAV_BYTE_SERROR 0x4f68 /** Byte-Wise Sticky Error */ |
| 355 | #define IOSAV_BYTE_SERROR_C 0x4f6c /** Byte-Wise Sticky Error Clear */ |
| 356 | |
| 357 | #define PM_TRML_M_CONFIG 0x4f80 /* Thermal mode configuration */ |
| 358 | #define PM_CMD_PWR 0x4f84 /* Power contribution of commands */ |
| 359 | #define PM_BW_LIMIT_CONFIG 0x4f88 /* Bandwidth throttling on overtemperature */ |
| 360 | #define SC_WDBWM 0x4f8c /* Watermarks and starvation counter config */ |
| 361 | |
| 362 | /* No, there's no need to get mad about the Memory Address Decoder */ |
| 363 | #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ |
| 364 | #define MAD_DIMM(ch) Ly(0x5004, ch) /* Channel characteristics */ |
| 365 | #define MAD_DIMM_CH0 MAD_DIMM(0) /* Channel 0 is at 0x5004 */ |
| 366 | #define MAD_DIMM_CH1 MAD_DIMM(1) /* Channel 1 is at 0x5008 */ |
| 367 | #define MAD_DIMM_CH2 MAD_DIMM(2) /* Channel 2 is at 0x500c (unused on SNB) */ |
| 368 | |
| 369 | #define MAD_ZR 0x5014 /* Address Decode Zones */ |
| 370 | #define MCDECS_SPARE 0x5018 /* Spare register in mcdecs synthesis FUB */ |
| 371 | #define MCDECS_CBIT 0x501c /* Chicken bits in mcdecs synthesis FUB */ |
| 372 | |
| 373 | #define CHANNEL_HASH 0x5024 /** WARNING: Only exists on IVB! */ |
| 374 | |
| 375 | #define MC_INIT_STATE_G 0x5030 /* High-level behavior in IOSAV mode */ |
| 376 | #define MRC_REVISION 0x5034 /* MRC Revision */ |
| 377 | #define PM_DLL_CONFIG 0x5064 /* Memory Controller I/O DLL config */ |
| 378 | #define RCOMP_TIMER 0x5084 /* RCOMP evaluation timer register */ |
| 379 | |
| 380 | #define MC_LOCK 0x50fc /* Memory Controlller Lock register */ |
| 381 | |
| 382 | #define GFXVTBAR 0x5400 /* Base address for IGD */ |
| 383 | #define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */ |
| 384 | |
| 385 | /* On Ivy Bridge, this is used to enable Power Aware Interrupt Routing */ |
| 386 | #define INTRDIRCTL 0x5418 /* Interrupt Redirection Control */ |
| 387 | |
| 388 | /* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ |
| 389 | #define PAVP_MSG 0x5500 |
| 390 | |
| 391 | #define MEM_TRML_ESTIMATION_CONFIG 0x5880 |
| 392 | #define MEM_TRML_THRESHOLDS_CONFIG 0x5888 |
| 393 | #define MEM_TRML_INTERRUPT 0x58a8 |
| 394 | |
| 395 | /* Some power MSRs are also represented in MCHBAR */ |
| 396 | #define MCH_PKG_POWER_LIMIT_LO 0x59a0 /* Turbo Power Limit 1 parameters */ |
| 397 | #define MCH_PKG_POWER_LIMIT_HI 0x59a4 /* Turbo Power Limit 2 parameters */ |
| 398 | |
| 399 | #define SSKPD 0x5d10 /* 64-bit scratchpad register */ |
| 400 | #define SSKPD_HI 0x5d14 |
| 401 | #define BIOS_RESET_CPL 0x5da8 /* 8-bit */ |
| 402 | |
| 403 | /* PCODE will sample SAPM-related registers at the end of Phase 4. */ |
| 404 | #define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */ |
| 405 | #define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ |
| 406 | #define SAPMCTL 0x5f00 /* Bit 3 enables DDR EPG (C7i) on IVB */ |
| 407 | #define M_COMP 0x5f08 /* Memory COMP control */ |
| 408 | #define SAPMTIMERS 0x5f10 /* SAPM timers in 10ns (100 MHz) units */ |
| 409 | |
| 410 | /* WARNING: Only applies to Sandy Bridge! */ |
| 411 | #define BANDTIMERS_SNB 0x5f18 /* MPLL and PPLL time to do self-banding */ |
| 412 | |
| 413 | /** WARNING: Only applies to Ivy Bridge! */ |
| 414 | #define SAPMTIMERS2_IVB 0x5f18 /** Extra latency for DDRIO EPG exit (C7i) */ |
| 415 | #define BANDTIMERS_IVB 0x5f20 /** MPLL and PPLL time to do self-banding */ |
| 416 | |
| 417 | /* Finalize registers. The names come from Haswell, as the finalize sequence is the same. */ |
| 418 | #define HDAUDRID 0x6008 |
| 419 | #define UMAGFXCTL 0x6020 |
| 420 | #define VDMBDFBARKVM 0x6030 |
| 421 | #define VDMBDFBARPAVP 0x6034 |
| 422 | #define VTDTRKLCK 0x63fc |
| 423 | #define REQLIM 0x6800 |
| 424 | #define DMIVCLIM 0x7000 |
| 425 | #define PEGCTL 0x7010 /* Bit 0 is PCIPWRGAT (clock gate all PEG controllers) */ |
| 426 | #define CRDTCTL3 0x740c /* Minimum completion credits for PCIe/DMI */ |
| 427 | #define CRDTCTL4 0x7410 /* Read Return Tracker credits */ |
| 428 | #define CRDTLCK 0x77fc |
| 429 | |
| 430 | #endif /* __SANDYBRIDGE_MCHBAR_REGS_H__ */ |