Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Patrick Georgi | 5b2a2d0 | 2018-09-26 20:46:04 +0200 | [diff] [blame] | 4 | * Copyright (C) 2012 Google LLC |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 5 | * Copyright (C) 2013 Vladimir Serbinenko. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #define __SIMPLE_DEVICE__ |
| 18 | |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 19 | #include <arch/cpu.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 20 | #include <device/pci_ops.h> |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 21 | #include <cbmem.h> |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 22 | #include <console/console.h> |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 23 | #include <cpu/intel/romstage.h> |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 24 | #include <cpu/x86/mtrr.h> |
| 25 | #include <program_loading.h> |
Arthur Heymans | 97c7c6b | 2018-05-15 16:45:21 +0200 | [diff] [blame] | 26 | #include <cpu/intel/smm/gen1/smi.h> |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 27 | #include "nehalem.h" |
| 28 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 29 | static uintptr_t smm_region_start(void) |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 30 | { |
| 31 | /* Base of TSEG is top of usable DRAM */ |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 32 | uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); |
| 33 | return tom; |
| 34 | } |
| 35 | |
Arthur Heymans | 97c7c6b | 2018-05-15 16:45:21 +0200 | [diff] [blame] | 36 | u32 northbridge_get_tseg_base(void) |
| 37 | { |
Arthur Heymans | 23fbd05 | 2019-05-28 17:38:17 +0200 | [diff] [blame] | 38 | return (u32)smm_region_start(); |
Arthur Heymans | 97c7c6b | 2018-05-15 16:45:21 +0200 | [diff] [blame] | 39 | } |
| 40 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 41 | void *cbmem_top(void) |
| 42 | { |
| 43 | return (void *) smm_region_start(); |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 44 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 45 | |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 46 | #define ROMSTAGE_RAM_STACK_SIZE 0x5000 |
| 47 | |
Arthur Heymans | 02b13fd | 2018-06-03 12:26:58 +0200 | [diff] [blame] | 48 | /* platform_enter_postcar() determines the stack to use after |
| 49 | * cache-as-ram is torn down as well as the MTRR settings to use, |
| 50 | * and continues execution in postcar stage. */ |
| 51 | void platform_enter_postcar(void) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 52 | { |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 53 | struct postcar_frame pcf; |
| 54 | uintptr_t top_of_ram; |
| 55 | |
| 56 | if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) |
| 57 | die("Unable to initialize postcar frame.\n"); |
| 58 | |
| 59 | /* Cache the ROM as WP just below 4GiB. */ |
Nico Huber | 089b908 | 2018-05-27 14:37:32 +0200 | [diff] [blame] | 60 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 61 | |
| 62 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 63 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 64 | |
| 65 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 66 | * above top of the ram. This satisfies MTRR alignment requirement |
| 67 | * with different TSEG size configurations. |
| 68 | */ |
| 69 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); |
| 70 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); |
| 71 | postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); |
| 72 | |
Arthur Heymans | 02b13fd | 2018-06-03 12:26:58 +0200 | [diff] [blame] | 73 | run_postcar_phase(&pcf); |
| 74 | |
| 75 | /* We do not return here. */ |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 76 | } |