blob: 6242147fd0fac9080cb1bdd19c474b71beaa0d7b [file] [log] [blame]
Stefan Reinauerb89a7612012-03-30 01:01:51 +02001## This file is part of the coreboot project.
2##
3## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
4##
5## This program is free software; you can redistribute it and/or modify
6## it under the terms of the GNU General Public License as published by
7## the Free Software Foundation; version 2 of the License.
8##
9## This program is distributed in the hope that it will be useful,
10## but WITHOUT ANY WARRANTY; without even the implied warranty of
11## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12## GNU General Public License for more details.
13##
14## You should have received a copy of the GNU General Public License
15## along with this program; if not, write to the Free Software
16## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17##
18
19config CHROMEOS
20 bool
21 default n
22 select TPM
23 select CACHE_ROM
24 help
Stefan Reinauer9aea04a2012-03-30 12:01:06 -070025 Enable ChromeOS specific features like the GPIO sub table in
26 the coreboot table. NOTE: Enabling this option on an unsupported
27 board will most likely break your build.
Stefan Reinauerb89a7612012-03-30 01:01:51 +020028
Stefan Reinauerf17789c2012-04-03 11:22:15 -070029menu "ChromeOS"
30 depends on CHROMEOS
31
Stefan Reinauer9aea04a2012-03-30 12:01:06 -070032config VBNV_OFFSET
33 hex
34 default 0x26
35 help
36 CMOS offset for VbNv data. This value must match cmos.layout
37 in the mainboard directory, minus 14 bytes for the RTC.
Stefan Reinauerb89a7612012-03-30 01:01:51 +020038
Stefan Reinauer9aea04a2012-03-30 12:01:06 -070039config VBNV_SIZE
40 hex
41 default 0x10
42 help
43 CMOS storage size for VbNv data. This value must match cmos.layout
44 in the mainboard directory.
Stefan Reinauerb89a7612012-03-30 01:01:51 +020045
Stefan Reinauer9aea04a2012-03-30 12:01:06 -070046config CHROMEOS_RAMOOPS
47 bool "Reserve space for Chrome OS ramoops"
48 default y
49
50config CHROMEOS_RAMOOPS_RAM_START
51 hex "Physical address of preserved RAM"
52 default 0x00f00000
53 depends on CHROMEOS_RAMOOPS
54
55config CHROMEOS_RAMOOPS_RAM_SIZE
56 hex "Size of preserved RAM"
57 default 0x00100000
58 depends on CHROMEOS_RAMOOPS
Stefan Reinauerf17789c2012-04-03 11:22:15 -070059
Stefan Reinauer357bb2d2012-08-09 13:44:38 -070060config FLASHMAP_OFFSET
Duncan Laurie87abeff2012-08-14 16:32:30 -070061 hex "Flash Map Offset"
Stefan Reinauer357bb2d2012-08-09 13:44:38 -070062 default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
Duncan Laurie87abeff2012-08-14 16:32:30 -070063 default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
Stefan Reinauer357bb2d2012-08-09 13:44:38 -070064 help
65 Offset of flash map in firmware image
66
Stefan Reinauerf17789c2012-04-03 11:22:15 -070067endmenu
Stefan Reinauerc7fe2802012-09-19 11:10:15 -070068
69config NO_TPM_RESUME
70 bool
71 default n
72 depends on CHROMEOS
73 help
74 On some boards the TPM stays powered up in S3. On those
75 boards, booting Windows will break if the TPM resume command
76 is sent during an S3 resume.