Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2019 Vlado Cibic <vladocb@protonmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame] | 16 | #include <bootblock_common.h> |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 17 | #include <device/pnp_ops.h> |
| 18 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 19 | #include <southbridge/intel/bd82x6x/pch.h> |
| 20 | |
| 21 | #include <superio/nuvoton/common/nuvoton.h> |
| 22 | #include <superio/nuvoton/nct6779d/nct6779d.h> |
| 23 | |
| 24 | #include <option.h> |
| 25 | |
| 26 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 27 | #include <northbridge/intel/sandybridge/raminit.h> |
| 28 | #include <northbridge/intel/sandybridge/pei_data.h> |
| 29 | |
| 30 | #define GLOBAL_DEV PNP_DEV(0x2e, 0) |
| 31 | #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2) |
| 32 | |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 33 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 34 | /* {enable, current, oc_pin} */ |
| 35 | { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */ |
| 36 | { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */ |
| 37 | { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */ |
| 38 | { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */ |
| 39 | { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */ |
| 40 | { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */ |
| 41 | { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */ |
| 42 | { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */ |
| 43 | { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */ |
| 44 | { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */ |
| 45 | { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */ |
| 46 | { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */ |
Elyes HAOUAS | b7da27c | 2020-01-11 19:21:07 +0100 | [diff] [blame] | 47 | { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */ |
| 48 | { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */ |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 49 | }; |
| 50 | |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame] | 51 | void bootblock_mainboard_early_init(void) |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 52 | { |
| 53 | /* Setup COM/UART */ |
| 54 | nuvoton_pnp_enter_conf_state(GLOBAL_DEV); |
| 55 | |
| 56 | /* TODO / FIXME: Setup Multifuncion/SIO pins for COM */ |
| 57 | |
| 58 | pnp_set_logical_device(SERIAL_DEV); |
| 59 | nuvoton_pnp_exit_conf_state(GLOBAL_DEV); |
| 60 | nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 61 | } |
| 62 | |
| 63 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 64 | { |
| 65 | read_spd(&spd[0], 0x50, id_only); |
| 66 | read_spd(&spd[1], 0x51, id_only); |
| 67 | read_spd(&spd[2], 0x52, id_only); |
| 68 | read_spd(&spd[3], 0x53, id_only); |
| 69 | } |
| 70 | |
| 71 | int mainboard_should_reset_usb(int s3resume) |
| 72 | { |
| 73 | return !s3resume; |
| 74 | } |
| 75 | |
| 76 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
| 77 | { |
| 78 | /* |
| 79 | * USB3 mode: |
| 80 | * 0 = Disable: work always as USB 2.0(ehci) |
| 81 | * 1 = Enable: work always as USB 3.0(xhci) |
| 82 | * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver |
| 83 | * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver |
| 84 | * and reboots, it will keep the USB3.0 speed |
| 85 | */ |
| 86 | int usb3_mode = 1; |
| 87 | get_option(&usb3_mode, "usb3_mode"); |
| 88 | usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */ |
| 89 | |
| 90 | /* Load USB3 pre-OS xHCI driver */ |
| 91 | int usb3_drv = 1; |
| 92 | get_option(&usb3_drv, "usb3_drv"); |
| 93 | usb3_drv &= 0x1; /* ensure it's 0/1 only */ |
| 94 | |
| 95 | /* Use USB3 xHCI streams */ |
| 96 | int usb3_streams = 1; |
| 97 | get_option(&usb3_streams, "usb3_streams"); |
| 98 | usb3_streams &= 0x1; /* ensure it's 0/1 only */ |
| 99 | |
| 100 | struct pei_data pd = { |
| 101 | .pei_version = PEI_VERSION, |
| 102 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 103 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
| 104 | .epbar = DEFAULT_EPBAR, |
| 105 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 106 | .smbusbar = SMBUS_IO_BASE, |
| 107 | .wdbbar = 0x4000000, |
| 108 | .wdbsize = 0x1000, |
| 109 | .hpet_address = CONFIG_HPET_ADDRESS, |
| 110 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
| 111 | .pmbase = DEFAULT_PMBASE, |
| 112 | .gpiobase = DEFAULT_GPIOBASE, |
| 113 | .thermalbase = 0xfed08000, |
| 114 | .system_type = 1, /* 0=Mobile, 1=Desktop/Server */ |
| 115 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 116 | .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ |
| 117 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 118 | .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */ |
| 119 | .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ |
| 120 | .dimm_channel0_disabled = 0, /* Both DIMM enabled */ |
| 121 | .dimm_channel1_disabled = 0, /* Both DIMM enabled */ |
| 122 | .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */ |
| 123 | .usb_port_config = { |
| 124 | /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ |
| 125 | { 1, 0, 0x0080 }, /* USB3 front internal header */ |
| 126 | { 1, 0, 0x0080 }, /* USB3 front internal header */ |
| 127 | { 1, 1, 0x0080 }, /* USB3 ETH top connector */ |
| 128 | { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ |
| 129 | { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ |
| 130 | { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ |
| 131 | { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ |
| 132 | { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ |
| 133 | { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ |
| 134 | { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ |
| 135 | { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */ |
| 136 | { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */ |
| 137 | { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */ |
| 138 | { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */ |
| 139 | }, |
| 140 | .usb3 = { |
| 141 | /* 0=Disable; 1=Enable (start at USB3 speed) |
| 142 | * 2=Auto (start as USB2 speed until OS loads) |
| 143 | * 3=Smart Auto (like Auto but keep speed on reboot) |
| 144 | */ |
| 145 | usb3_mode, |
| 146 | /* 4 bit switch mask. 0=not switchable, 1=switchable |
| 147 | * Means once it's loaded the OS, it can swap ports |
| 148 | * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf |
| 149 | */ |
| 150 | 0xf, |
| 151 | usb3_drv, /* 1=Load xHCI pre-OS drv */ |
| 152 | /* 0=Don't use xHCI streams for better compatibility |
| 153 | * 1=use xHCI streams for better speed |
| 154 | */ |
| 155 | usb3_streams |
| 156 | }, |
| 157 | /* ASUS P8Z77-M Pro manual says 1.35v DIMMs are supported */ |
| 158 | .ddr3lv_support = 1, |
| 159 | /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it, |
Elyes HAOUAS | b7da27c | 2020-01-11 19:21:07 +0100 | [diff] [blame] | 160 | * but might cause some system instability ! |
Vlado Cibic | 2bf6a30 | 2019-06-09 06:53:50 +0000 | [diff] [blame] | 161 | */ |
| 162 | .pcie_init = 1, |
| 163 | /* Command Rate. 0=Auto; 1=1N; 2=2N. |
| 164 | * Leave it always at Auto for compatibility & stability |
| 165 | */ |
| 166 | .nmode = 0, |
| 167 | /* DDR refresh rate. 0=Auto based on DRAM's temperature; |
| 168 | * 1=Normal rate for speed; 2=Double rate for stability |
| 169 | */ |
| 170 | .ddr_refresh_rate_config = 0 |
| 171 | }; |
| 172 | |
| 173 | /* copy the data to output PEI */ |
| 174 | *pei_data = pd; |
| 175 | } |