blob: 530fdfafd903d9d4b335fc62838d445909fcf9c0 [file] [log] [blame]
Damien Zammit43a1f782015-08-19 15:16:59 +10001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <arch/ioapic.h>
19
20Name(_HID,EISAID("PNP0A08")) // PCIe
21Name(_CID,EISAID("PNP0A03")) // PCI
22
23Name(_ADR, 0)
24Name(_BBN, 0)
25
26Device (MCHC)
27{
28 Name(_ADR, 0x00000000) // 0:0.0
29
30 OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
31 Field (MCHP, DWordAcc, NoLock, Preserve)
32 {
33 Offset (0x40), // EPBAR
34 EPEN, 1, // Enable
35 , 11, //
36 EPBR, 24, // EPBAR
37
38 Offset (0x48), // MCHBAR
39 MHEN, 1, // Enable
40 , 13, //
41 MHBR, 22, // MCHBAR
42
43 Offset (0x60), // PCIe BAR
44 PXEN, 1, // Enable
45 PXSZ, 2, // BAR size
46 , 23, //
47 PXBR, 10, // PCIe BAR
48
49 Offset (0x68), // DMIBAR
50 DMEN, 1, // Enable
51 , 11, //
52 DMBR, 24, // DMIBAR
53
54 // ...
55
56 Offset (0x90), // PAM0
57 , 4,
58 PM0H, 2,
59 , 2,
60 Offset (0x91), // PAM1
61 PM1L, 2,
62 , 2,
63 PM1H, 2,
64 , 2,
65 Offset (0x92), // PAM2
66 PM2L, 2,
67 , 2,
68 PM2H, 2,
69 , 2,
70 Offset (0x93), // PAM3
71 PM3L, 2,
72 , 2,
73 PM3H, 2,
74 , 2,
75 Offset (0x94), // PAM4
76 PM4L, 2,
77 , 2,
78 PM4H, 2,
79 , 2,
80 Offset (0x95), // PAM5
81 PM5L, 2,
82 , 2,
83 PM5H, 2,
84 , 2,
85 Offset (0x96), // PAM6
86 PM6L, 2,
87 , 2,
88 PM6H, 2,
89 , 2,
90
91 Offset (0xa0), // Top of Used Memory
92 TOM, 8,
93
94 Offset (0xb0), // Top of Low Used Memory
95 , 4,
96 TLUD, 12,
97 }
98
99}
100
101Name (MCRS, ResourceTemplate()
102{
103 // Bus Numbers
104 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
105 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
106
107 // IO Region 0
108 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
109 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
110
111 // PCI Config Space
112 Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
113
114 // IO Region 1
115 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
116 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
117
118 // VGA memory (0xa0000-0xbffff)
119 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
120 Cacheable, ReadWrite,
121 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
122 0x00020000,,, ASEG)
123
124 // OPROM reserved (0xc0000-0xc3fff)
125 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
126 Cacheable, ReadWrite,
127 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
128 0x00004000,,, OPR0)
129
130 // OPROM reserved (0xc4000-0xc7fff)
131 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
132 Cacheable, ReadWrite,
133 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
134 0x00004000,,, OPR1)
135
136 // OPROM reserved (0xc8000-0xcbfff)
137 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
138 Cacheable, ReadWrite,
139 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
140 0x00004000,,, OPR2)
141
142 // OPROM reserved (0xcc000-0xcffff)
143 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
144 Cacheable, ReadWrite,
145 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
146 0x00004000,,, OPR3)
147
148 // OPROM reserved (0xd0000-0xd3fff)
149 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
150 Cacheable, ReadWrite,
151 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
152 0x00004000,,, OPR4)
153
154 // OPROM reserved (0xd4000-0xd7fff)
155 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
156 Cacheable, ReadWrite,
157 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
158 0x00004000,,, OPR5)
159
160 // OPROM reserved (0xd8000-0xdbfff)
161 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
162 Cacheable, ReadWrite,
163 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
164 0x00004000,,, OPR6)
165
166 // OPROM reserved (0xdc000-0xdffff)
167 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
168 Cacheable, ReadWrite,
169 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
170 0x00004000,,, OPR7)
171
172 // BIOS Extension (0xe0000-0xe3fff)
173 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
174 Cacheable, ReadWrite,
175 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
176 0x00004000,,, ESG0)
177
178 // BIOS Extension (0xe4000-0xe7fff)
179 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
180 Cacheable, ReadWrite,
181 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
182 0x00004000,,, ESG1)
183
184 // BIOS Extension (0xe8000-0xebfff)
185 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
186 Cacheable, ReadWrite,
187 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
188 0x00004000,,, ESG2)
189
190 // BIOS Extension (0xec000-0xeffff)
191 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
192 Cacheable, ReadWrite,
193 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
194 0x00004000,,, ESG3)
195
196 // System BIOS (0xf0000-0xfffff)
197 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
198 Cacheable, ReadWrite,
199 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
200 0x00010000,,, FSEG)
201
202 // PCI Memory Region (Top of memory-0xfebfffff)
203 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
204 Cacheable, ReadWrite,
205 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
206 IO_APIC_ADDR,,, PM01)
207
208 // TPM Area (0xfed40000-0xfed44fff)
209 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
210 Cacheable, ReadWrite,
211 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
212 0x00005000,,, TPMR)
213})
214
215// Current Resource Settings
216
217Method (_CRS, 0, Serialized)
218{
219 // Find PCI resource area in MCRS
220 CreateDwordField(MCRS, ^PM01._MIN, PMIN)
221 CreateDwordField(MCRS, ^PM01._MAX, PMAX)
222 CreateDwordField(MCRS, ^PM01._LEN, PLEN)
223
224 // Fix up PCI memory region:
225 // Enter actual TOLUD. The TOLUD register contains bits 20-31 of
226 // the top of memory address.
227 ShiftLeft (^MCHC.TLUD, 20, PMIN)
228 Add(Subtract(PMAX, PMIN), 1, PLEN)
229
230 Return (MCRS)
231}
232
233/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
234#include "acpi/x4x_pci_irqs.asl"