blob: c3139a99ddca813feeb4d12b3bfadbeca306fc4c [file] [log] [blame]
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013, 2014 Vladimir Serbinenko
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 or (at your option)
9 * any later version of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +020015 */
16
17#include <arch/io.h>
18#include <console/console.h>
19#include <delay.h>
20#include <device/device.h>
21#include <string.h>
22
23#include <drivers/intel/gma/edid.h>
24#include <drivers/intel/gma/i915.h>
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +020025#include "gma.h"
26#include "chip.h"
Iru Cai8e7928a2015-10-18 23:40:34 +080027#include "sandybridge.h"
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +020028#include <pc80/vga.h>
29#include <pc80/vga_io.h>
30#include <device/pci_def.h>
31#include <device/pci_rom.h>
32
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080033static void train_link(u8 *mmio)
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +020034{
35 /* Clear interrupts. */
36 write32(mmio + DEIIR, 0xffffffff);
37
38 write32(mmio + 0xf000c, 0x2040);
39 write32(mmio + 0xf000c, 0x2050);
40 write32(mmio + 0x60100, 0x44000);
41 write32(mmio + 0xf000c, 0x22050);
42
43 mdelay(1);
44
45 write32(mmio + 0x000f0018, 0x0000008ff);
46 write32(mmio + 0x000f1018, 0x0000008ff);
47
48 write32(mmio + 0x000f000c, 0x001a2050);
49 write32(mmio + 0x00060100, 0x001c4000);
50
51 write32(mmio + 0x00060100, 0x801c4000);
52 write32(mmio + 0x000f000c, 0x801a2050);
53
54 write32(mmio + 0x00060100, 0x801c4000);
55 write32(mmio + 0x000f000c, 0x801a2050);
56 mdelay(1);
57
58 read32(mmio + 0x000f0014); // = 0x00000100
59 write32(mmio + 0x000f0014, 0x00000100);
60 write32(mmio + 0x00060100, 0x901c4000);
61 write32(mmio + 0x000f000c, 0x801a2150);
62 mdelay(1);
63 read32(mmio + 0x000f0014); // = 0x00000600
64}
65
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080066static void power_port(u8 *mmio)
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +020067{
68 read32(mmio + 0x000e1100); // = 0x00000000
69 write32(mmio + 0x000e1100, 0x00000000);
70 write32(mmio + 0x000e1100, 0x00010000);
71 read32(mmio + 0x000e1100); // = 0x00010000
72 read32(mmio + 0x000e1100); // = 0x00010000
73 read32(mmio + 0x000e1100); // = 0x00000000
74 write32(mmio + 0x000e1100, 0x00000000);
75 read32(mmio + 0x000e1100); // = 0x00000000
76 read32(mmio + 0x000e4200); // = 0x0000001c
77 write32(mmio + 0x000e4210, 0x8004003e);
78 write32(mmio + 0x000e4214, 0x80060002);
79 write32(mmio + 0x000e4218, 0x01000000);
80 read32(mmio + 0x000e4210); // = 0x5144003e
81 write32(mmio + 0x000e4210, 0x5344003e);
82 read32(mmio + 0x000e4210); // = 0x0144003e
83 write32(mmio + 0x000e4210, 0x8074003e);
84 read32(mmio + 0x000e4210); // = 0x5144003e
85 read32(mmio + 0x000e4210); // = 0x5144003e
86 write32(mmio + 0x000e4210, 0x5344003e);
87 read32(mmio + 0x000e4210); // = 0x0144003e
88 write32(mmio + 0x000e4210, 0x8074003e);
89 read32(mmio + 0x000e4210); // = 0x5144003e
90 read32(mmio + 0x000e4210); // = 0x5144003e
91 write32(mmio + 0x000e4210, 0x5344003e);
92 read32(mmio + 0x000e4210); // = 0x0144003e
93 write32(mmio + 0x000e4210, 0x8074003e);
94 read32(mmio + 0x000e4210); // = 0x5144003e
95 read32(mmio + 0x000e4210); // = 0x5144003e
96 write32(mmio + 0x000e4210, 0x5344003e);
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +020097 write32(mmio + 0x000c4030, 0x00001000);
98 read32(mmio + 0x000c4000); // = 0x00000000
99 write32(mmio + 0x000c4030, 0x00001000);
100 read32(mmio + 0x000e1150); // = 0x0000001c
101 write32(mmio + 0x000e1150, 0x0000089c);
102 write32(mmio + 0x000fcc00, 0x01986f00);
103 write32(mmio + 0x000fcc0c, 0x01986f00);
104 write32(mmio + 0x000fcc18, 0x01986f00);
105 write32(mmio + 0x000fcc24, 0x01986f00);
106 read32(mmio + 0x000c4000); // = 0x00000000
107 read32(mmio + 0x000e1180); // = 0x40000002
108}
109
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200110int i915lightup_sandy(const struct i915_gpu_controller_info *info,
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800111 u32 physbase, u16 piobase, u8 *mmio, u32 lfb)
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200112{
113 int i;
114 u8 edid_data[128];
115 struct edid edid;
Alexandru Gagniucc2418552015-09-02 09:00:45 -0700116 struct edid_mode *mode;
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200117 u32 hactive, vactive, right_border, bottom_border;
118 int hpolarity, vpolarity;
119 u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
120 u32 candp1, candn;
121 u32 best_delta = 0xffffffff;
122 u32 target_frequency;
123 u32 pixel_p1 = 1;
124 u32 pixel_n = 1;
125 u32 pixel_m1 = 1;
126 u32 pixel_m2 = 1;
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200127 u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000;
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200128 u32 data_m1;
129 u32 data_n1 = 0x00800000;
130 u32 link_m1;
131 u32 link_n1 = 0x00080000;
132
Alexandru Gagniuc96470942015-09-07 03:06:31 -0700133 if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
134 return 0;
135
Iru Cai8e7928a2015-10-18 23:40:34 +0800136 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
137 return i915lightup_ivy(info, physbase, piobase, mmio, lfb);
138 }
139
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200140 write32(mmio + 0x00070080, 0x00000000);
141 write32(mmio + DSPCNTR(0), 0x00000000);
142 write32(mmio + 0x00071180, 0x00000000);
143 write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE);
144 write32(mmio + 0x0007019c, 0x00000000);
145 write32(mmio + 0x0007119c, 0x00000000);
146 write32(mmio + 0x000ec008, 0x2c010000);
147 write32(mmio + 0x000ec020, 0x2c010000);
148 write32(mmio + 0x000ec038, 0x2c010000);
149 write32(mmio + 0x000ec050, 0x2c010000);
150 write32(mmio + 0x000ec408, 0x2c010000);
151 write32(mmio + 0x000ec420, 0x2c010000);
152 write32(mmio + 0x000ec438, 0x2c010000);
153 write32(mmio + 0x000ec450, 0x2c010000);
154 vga_gr_write(0x18, 0);
155 write32(mmio + 0x00042004, 0x02000000);
156 write32(mmio + 0x000fd034, 0x8421ffe0);
157
158 /* Setup GTT. */
159 for (i = 0; i < 0x2000; i++)
160 {
161 outl((i << 2) | 1, piobase);
162 outl(physbase + (i << 12) + 1, piobase + 4);
163 }
164
165 vga_misc_write(0x67);
166
167 const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
168 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
169 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
170 0xff
171 };
172 vga_cr_write(0x11, 0);
173
174 for (i = 0; i <= 0x18; i++)
175 vga_cr_write(i, cr[i]);
176
177 power_port(mmio);
178
Arthur Heymans7141ff32016-10-10 17:49:00 +0200179 intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data,
180 sizeof(edid_data));
Alexandru Gagniucc2418552015-09-02 09:00:45 -0700181 decode_edid(edid_data, sizeof(edid_data), &edid);
182 mode = &edid.mode;
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200183
184 /* Disable screen memory to prevent garbage from appearing. */
185 vga_sr_write(1, vga_sr_read(1) | 0x20);
186
187 hactive = edid.x_resolution;
188 vactive = edid.y_resolution;
Alexandru Gagniucc2418552015-09-02 09:00:45 -0700189 right_border = mode->hborder;
190 bottom_border = mode->vborder;
191 hpolarity = (mode->phsync == '-');
192 vpolarity = (mode->pvsync == '-');
193 vsync = mode->vspw;
194 hsync = mode->hspw;
195 vblank = mode->vbl;
196 hblank = mode->hbl;
197 hfront_porch = mode->hso;
198 vfront_porch = mode->vso;
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200199
Vladimir Serbinenko551cff02015-10-10 23:58:08 +0200200 target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
Alexandru Gagniucc2418552015-09-02 09:00:45 -0700201 : (2 * mode->pixel_clock);
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200202
Nico Huber6d8266b2017-05-20 16:46:01 +0200203 if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
Alexandru Gagniuc96470942015-09-07 03:06:31 -0700204 vga_sr_write(1, 1);
205 vga_sr_write(0x2, 0xf);
206 vga_sr_write(0x3, 0x0);
207 vga_sr_write(0x4, 0xe);
208 vga_gr_write(0, 0x0);
209 vga_gr_write(1, 0x0);
210 vga_gr_write(2, 0x0);
211 vga_gr_write(3, 0x0);
212 vga_gr_write(4, 0x0);
213 vga_gr_write(5, 0x0);
214 vga_gr_write(6, 0x5);
215 vga_gr_write(7, 0xf);
216 vga_gr_write(0x10, 0x1);
217 vga_gr_write(0x11, 0);
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200218
Alexandru Gagniuc96470942015-09-07 03:06:31 -0700219 edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200220
Alexandru Gagniuc96470942015-09-07 03:06:31 -0700221 write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
222 write32(mmio + DSPADDR(0), 0);
223 write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
224 write32(mmio + DSPSURF(0), 0);
225 for (i = 0; i < 0x100; i++)
226 write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
227 } else {
228 vga_textmode_init();
229 }
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200230
231 /* Find suitable divisors. */
232 for (candp1 = 1; candp1 <= 8; candp1++) {
233 for (candn = 5; candn <= 10; candn++) {
234 u32 cur_frequency;
235 u32 m; /* 77 - 131. */
236 u32 denom; /* 35 - 560. */
237 u32 current_delta;
238
239 denom = candn * candp1 * 7;
Martin Roth128c1042016-11-18 09:29:03 -0700240 /* Doesn't overflow for up to
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200241 5000000 kHz = 5 GHz. */
242 m = (target_frequency * denom + 60000) / 120000;
243
244 if (m < 77 || m > 131)
245 continue;
246
247 cur_frequency = (120000 * m) / denom;
248 if (target_frequency > cur_frequency)
249 current_delta = target_frequency - cur_frequency;
250 else
251 current_delta = cur_frequency - target_frequency;
252
253
254 if (best_delta > current_delta) {
255 best_delta = current_delta;
256 pixel_n = candn;
257 pixel_p1 = candp1;
258 pixel_m2 = ((m + 3) % 5) + 7;
259 pixel_m1 = (m - pixel_m2) / 5;
260 }
261 }
262 }
263
264 if (best_delta == 0xffffffff) {
265 printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
266 return 0;
267 }
268
Alexandru Gagniucc2418552015-09-02 09:00:45 -0700269 link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
270 data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
Vladimir Serbinenkoc48f5ef2015-10-11 02:05:55 +0200271 / (link_frequency * 8 * 4);
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200272
273 printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
274 hactive, vactive);
275 printk(BIOS_DEBUG, "Borders %d x %d\n",
276 right_border, bottom_border);
277 printk(BIOS_DEBUG, "Blank %d x %d\n",
278 hblank, vblank);
279 printk(BIOS_DEBUG, "Sync %d x %d\n",
280 hsync, vsync);
281 printk(BIOS_DEBUG, "Front porch %d x %d\n",
282 hfront_porch, vfront_porch);
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200283 printk(BIOS_DEBUG, (info->use_spread_spectrum_clock
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200284 ? "Spread spectrum clock\n" : "DREF clock\n"));
285 printk(BIOS_DEBUG,
Vladimir Serbinenko551cff02015-10-10 23:58:08 +0200286 mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200287 printk(BIOS_DEBUG, "Polarities %d, %d\n",
288 hpolarity, vpolarity);
289 printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
290 data_m1, data_n1);
291 printk(BIOS_DEBUG, "Link frequency %d kHz\n",
292 link_frequency);
293 printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n",
294 link_m1, link_n1);
295 printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
296 pixel_n, pixel_m1, pixel_m2, pixel_p1);
297 printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
298 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
299 / (pixel_p1 * 7));
300
301 write32(mmio + PCH_LVDS,
302 (hpolarity << 20) | (vpolarity << 21)
Vladimir Serbinenko551cff02015-10-10 23:58:08 +0200303 | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200304 | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
305 | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
306 | LVDS_DETECTED);
307 write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200308 write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200309 ? 0x1002 : 0x400));
310 mdelay(1);
311 write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
312 | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
313 write32(mmio + _PCH_FP0(0),
314 ((pixel_n - 2) << 16)
315 | ((pixel_m1 - 2) << 8) | pixel_m2);
316 write32(mmio + PCH_DPLL_SEL, 8);
317 write32(mmio + _PCH_DPLL(0),
318 DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
Vladimir Serbinenko551cff02015-10-10 23:58:08 +0200319 | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200320 : DPLLB_LVDS_P2_CLOCK_DIV_14)
321 | (0x10000 << (pixel_p1 - 1))
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200322 | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200323 | (0x1 << (pixel_p1 - 1)));
324 mdelay(1);
325 write32(mmio + _PCH_DPLL(0),
326 DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
Vladimir Serbinenko551cff02015-10-10 23:58:08 +0200327 | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200328 : DPLLB_LVDS_P2_CLOCK_DIV_14)
329 | (0x10000 << (pixel_p1 - 1))
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200330 | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200331 | (0x1 << (pixel_p1 - 1)));
332 /* Re-lock the registers. */
333 write32(mmio + PCH_PP_CONTROL,
334 (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
335
336 write32(mmio + PCH_LVDS,
337 (hpolarity << 20) | (vpolarity << 21)
Vladimir Serbinenko551cff02015-10-10 23:58:08 +0200338 | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200339 | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
340 | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
341 | LVDS_DETECTED);
342
343 write32(mmio + HTOTAL(0),
344 ((hactive + right_border + hblank - 1) << 16)
345 | (hactive - 1));
346 write32(mmio + HBLANK(0),
347 ((hactive + right_border + hblank - 1) << 16)
348 | (hactive + right_border - 1));
349 write32(mmio + HSYNC(0),
350 ((hactive + right_border + hfront_porch + hsync - 1) << 16)
351 | (hactive + right_border + hfront_porch - 1));
352
353 write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
354 | (vactive - 1));
355 write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
356 | (vactive + bottom_border - 1));
357 write32(mmio + VSYNC(0),
358 (vactive + bottom_border + vfront_porch + vsync - 1)
359 | (vactive + bottom_border + vfront_porch - 1));
360
361 write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
362
363 write32(mmio + PF_WIN_POS(0), 0);
Nico Huber6d8266b2017-05-20 16:46:01 +0200364 if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
Alexandru Gagniuc96470942015-09-07 03:06:31 -0700365 write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
366 write32(mmio + PF_CTL(0),0);
367 write32(mmio + PF_WIN_SZ(0), 0);
368 } else {
369 write32(mmio + PIPESRC(0), (639 << 16) | 399);
370 write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
371 write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
372 }
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200373
374 mdelay(1);
375
376 write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
377 write32(mmio + PIPE_DATA_N1(0), data_n1);
378 write32(mmio + PIPE_LINK_M1(0), link_m1);
379 write32(mmio + PIPE_LINK_N1(0), link_n1);
380
381 write32(mmio + 0x000f000c, 0x00002040);
382 mdelay(1);
383 write32(mmio + 0x000f000c, 0x00002050);
384 write32(mmio + 0x00060100, 0x00044000);
385 mdelay(1);
386 write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
387 write32(mmio + 0x000f000c, 0x00022050);
388 write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
389 write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
390
Nico Huber6d8266b2017-05-20 16:46:01 +0200391 if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
Alexandru Gagniuc96470942015-09-07 03:06:31 -0700392 write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
393 else
394 write32(mmio + CPU_VGACNTRL, 0x20298e);
395
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200396 train_link(mmio);
397
Nico Huber6d8266b2017-05-20 16:46:01 +0200398 if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
Alexandru Gagniuc96470942015-09-07 03:06:31 -0700399 write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
400 mdelay(1);
401 }
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200402
403 write32(mmio + TRANS_HTOTAL(0),
404 ((hactive + right_border + hblank - 1) << 16)
405 | (hactive - 1));
406 write32(mmio + TRANS_HBLANK(0),
407 ((hactive + right_border + hblank - 1) << 16)
408 | (hactive + right_border - 1));
409 write32(mmio + TRANS_HSYNC(0),
410 ((hactive + right_border + hfront_porch + hsync - 1) << 16)
411 | (hactive + right_border + hfront_porch - 1));
412
413 write32(mmio + TRANS_VTOTAL(0),
414 ((vactive + bottom_border + vblank - 1) << 16)
415 | (vactive - 1));
416 write32(mmio + TRANS_VBLANK(0),
417 ((vactive + bottom_border + vblank - 1) << 16)
418 | (vactive + bottom_border - 1));
419 write32(mmio + TRANS_VSYNC(0),
420 (vactive + bottom_border + vfront_porch + vsync - 1)
421 | (vactive + bottom_border + vfront_porch - 1));
422
423 write32(mmio + 0x00060100, 0xb01c4000);
424 write32(mmio + 0x000f000c, 0x801a2350);
425 mdelay(1);
Alexandru Gagniuc96470942015-09-07 03:06:31 -0700426
Nico Huber6d8266b2017-05-20 16:46:01 +0200427 if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
Alexandru Gagniuc96470942015-09-07 03:06:31 -0700428 write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
429 | TRANS_STATE_MASK);
430 else
431 write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC);
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200432
433 write32(mmio + PCH_LVDS,
434 LVDS_PORT_ENABLE
435 | (hpolarity << 20) | (vpolarity << 21)
Vladimir Serbinenko551cff02015-10-10 23:58:08 +0200436 | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200437 | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
438 | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
439 | LVDS_DETECTED);
440
441 write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
442 write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
443 mdelay(1);
444 write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
445 | PANEL_POWER_ON | PANEL_POWER_RESET);
446
447 printk (BIOS_DEBUG, "waiting for panel powerup\n");
448 while (1) {
449 u32 reg32;
450 reg32 = read32(mmio + PCH_PP_STATUS);
451 if (((reg32 >> 28) & 3) == 0)
452 break;
453 }
454 printk (BIOS_DEBUG, "panel powered up\n");
455
456 write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
457
458 /* Enable screen memory. */
459 vga_sr_write(1, vga_sr_read(1) & ~0x20);
460
461 /* Clear interrupts. */
462 write32(mmio + DEIIR, 0xffffffff);
463 write32(mmio + SDEIIR, 0xffffffff);
464
Nico Huber6d8266b2017-05-20 16:46:01 +0200465 if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
Alexandru Gagniuc96470942015-09-07 03:06:31 -0700466 memset ((void *) lfb, 0, edid.x_resolution
467 * edid.y_resolution * 4);
468 set_vbe_mode_info_valid(&edid, lfb);
469 }
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200470
471 /* Linux relies on VBT for panel info. */
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200472 generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
Arthur Heymansd3284a62016-09-25 22:48:00 +0200473 "$VBT SNB/IVB-MOBILE");
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200474
475 return 1;
476}