blob: 7be98d7a2f1c5e1b018f2654c627e74cbc84dcbb [file] [log] [blame]
Yinghai Luc65bd562007-02-01 00:10:05 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Yinghai Luc65bd562007-02-01 00:10:05 +00003 *
4 * Copyright (C) 2004 Tyan Computer
5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
6 * Copyright (C) 2006,2007 AMD
7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
Yinghai Luc65bd562007-02-01 00:10:05 +000018 */
19
Kyösti Mälkki8db31a82016-12-05 06:33:32 +020020#define __SIMPLE_DEVICE__
21
Yinghai Luc65bd562007-02-01 00:10:05 +000022#include <arch/io.h>
Stefan Reinauerf8b19232010-04-07 00:38:09 +000023#include <reset.h>
Yinghai Luc65bd562007-02-01 00:10:05 +000024
Yinghai Luc65bd562007-02-01 00:10:05 +000025#include "../../../northbridge/amd/amdk8/reset_test.c"
26
Julius Werner01f9aa52017-05-18 16:03:26 -070027void do_hard_reset(void)
Yinghai Luc65bd562007-02-01 00:10:05 +000028{
29 set_bios_reset();
30 /* Try rebooting through port 0xcf9 */
31 /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
32 outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
33 outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
34}