blob: 7c43feac98f8580eab1f1a1b76004188a08b14d3 [file] [log] [blame]
Yinghai Luc65bd562007-02-01 00:10:05 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Yinghai Luc65bd562007-02-01 00:10:05 +00003 *
4 * Copyright (C) 2004 Tyan Computer
5 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
6 * Copyright (C) 2006,2007 AMD
7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
Yinghai Luc65bd562007-02-01 00:10:05 +000018 */
19
20#include <console/console.h>
Yinghai Luc65bd562007-02-01 00:10:05 +000021#include <arch/io.h>
Yinghai Luc65bd562007-02-01 00:10:05 +000022#include <device/device.h>
23#include <device/pci.h>
24#include <device/pci_ids.h>
25#include <device/pci_ops.h>
26#include "mcp55.h"
27
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000028static u32 final_reg;
Yinghai Luc65bd562007-02-01 00:10:05 +000029
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000030static device_t find_lpc_dev(device_t dev, unsigned devfn)
Yinghai Luc65bd562007-02-01 00:10:05 +000031{
Yinghai Luc65bd562007-02-01 00:10:05 +000032 device_t lpc_dev;
33
34 lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
35
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000036 if (!lpc_dev)
37 return lpc_dev;
Yinghai Luc65bd562007-02-01 00:10:05 +000038
39 if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || (
40 (lpc_dev->device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) ||
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000041 (lpc_dev->device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)))
42 {
43 u32 id;
44 id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
45 if ((id < (PCI_VENDOR_ID_NVIDIA
46 | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) ||
47 (id > (PCI_VENDOR_ID_NVIDIA
48 | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16))))
49 {
50 lpc_dev = 0;
51 }
Yinghai Luc65bd562007-02-01 00:10:05 +000052 }
53
54 return lpc_dev;
55}
56
57void mcp55_enable(device_t dev)
58{
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000059 device_t lpc_dev = 0, sm_dev = 0;
60 unsigned index = 0, index2 = 0;
61 u32 reg_old, reg;
62 u8 byte;
63 unsigned deviceid, vendorid, devfn;
Yinghai Luc65bd562007-02-01 00:10:05 +000064 struct southbridge_nvidia_mcp55_config *conf;
65 conf = dev->chip_info;
66 int i;
67
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000068 if (dev->device == 0x0000) {
Yinghai Luc65bd562007-02-01 00:10:05 +000069 vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000070 deviceid = (vendorid >> 16) & 0xffff;
Yinghai Luc65bd562007-02-01 00:10:05 +000071 } else {
Yinghai Luc65bd562007-02-01 00:10:05 +000072 deviceid = dev->device;
73 }
74
Stefan Reinauer2b34db82009-02-28 20:10:20 +000075 devfn = (dev->path.pci.devfn) & ~7;
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000076 switch (deviceid) {
77 case PCI_DEVICE_ID_NVIDIA_MCP55_HT:
78 return;
79 case PCI_DEVICE_ID_NVIDIA_MCP55_SM2: //?
80 index = 16;
81 break;
82 case PCI_DEVICE_ID_NVIDIA_MCP55_USB:
83 devfn -= (1 << 3);
84 index = 8;
85 break;
86 case PCI_DEVICE_ID_NVIDIA_MCP55_USB2:
87 devfn -= (1 << 3);
88 index = 20;
89 break;
90 case PCI_DEVICE_ID_NVIDIA_MCP55_NIC: // two
91 case PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE: // two
92 devfn -= (7 << 3);
93 index = 10;
94 for (i = 0; i < 2; i++) {
95 lpc_dev = find_lpc_dev(dev, devfn - (i << 3));
96 if (!lpc_dev)
97 continue;
98 index -= i;
99 devfn -= (i << 3);
Yinghai Luc65bd562007-02-01 00:10:05 +0000100 break;
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000101 }
102 break;
103 case PCI_DEVICE_ID_NVIDIA_MCP55_AZA:
104 devfn -= (5 << 3);
105 index = 11;
106 break;
107 case PCI_DEVICE_ID_NVIDIA_MCP55_IDE:
108 devfn -= (3 << 3);
109 index = 14;
110 break;
111 case PCI_DEVICE_ID_NVIDIA_MCP55_SATA0: // three
112 case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: // three
113 devfn -= (4 << 3);
114 index = 22;
115 i = (dev->path.pci.devfn) & 7;
116 if (i > 0)
117 index -= (i + 3);
118 break;
119 case PCI_DEVICE_ID_NVIDIA_MCP55_PCI:
120 devfn -= (5 << 3);
121 index = 15;
122 break;
123 case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A:
124 devfn -= (0x9 << 3); // to LPC
125 index2 = 9;
126 break;
127 case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C: // two
128 devfn -= (0xa << 3); // to LPC
129 index2 = 8;
130 for (i = 0; i < 2; i++) {
131 lpc_dev = find_lpc_dev(dev, devfn - (i << 3));
132 if (!lpc_dev)
133 continue;
134 index2 -= i;
135 devfn -= (i << 3);
Yinghai Luc65bd562007-02-01 00:10:05 +0000136 break;
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000137 }
138 break;
139 case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D:
140 devfn -= (0xc << 3); // to LPC
141 index2 = 6;
142 break;
143 case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E:
144 devfn -= (0xd << 3); // to LPC
145 index2 = 5;
146 break;
147 case PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F:
148 devfn -= (0xe << 3); // to LPC
149 index2 = 4;
150 break;
151 default:
152 index = 0;
Yinghai Luc65bd562007-02-01 00:10:05 +0000153 }
154
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000155 if (!lpc_dev)
Yinghai Luc65bd562007-02-01 00:10:05 +0000156 lpc_dev = find_lpc_dev(dev, devfn);
157
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000158 if (!lpc_dev)
159 return;
Yinghai Luc65bd562007-02-01 00:10:05 +0000160
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000161 if (index2 != 0) {
Yinghai Luc65bd562007-02-01 00:10:05 +0000162 sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000163 if (!sm_dev)
164 return;
165 if (sm_dev) {
166 reg_old = reg = pci_read_config32(sm_dev, 0xe4);
167 if (!dev->enabled)
168 reg |= (1<<index2); /* Disable it. */
169 if (reg != reg_old)
Yinghai Luc65bd562007-02-01 00:10:05 +0000170 pci_write_config32(sm_dev, 0xe4, reg);
Yinghai Luc65bd562007-02-01 00:10:05 +0000171 }
Yinghai Luc65bd562007-02-01 00:10:05 +0000172 index2 = 0;
173 return;
174 }
175
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000176 if (index == 0) { // for LPC
177 /* Expose IOAPIC base. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000178 byte = pci_read_config8(lpc_dev, 0x74);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000179 byte |= (1 << 1); /* Expose the BAR. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000180 pci_write_config8(dev, 0x74, byte);
181
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000182 /* Expose trap base. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000183 byte = pci_read_config8(lpc_dev, 0xdd);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000184 byte |= (1 << 0) | (1 << 3); /* Expose BAR and enable write. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000185 pci_write_config8(dev, 0xdd, byte);
186
187 return;
Yinghai Luc65bd562007-02-01 00:10:05 +0000188 }
189
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000190 if (index == 16) {
Yinghai Luc65bd562007-02-01 00:10:05 +0000191 sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000192 if (!sm_dev)
193 return;
Yinghai Luc65bd562007-02-01 00:10:05 +0000194
195 final_reg = pci_read_config32(sm_dev, 0xe8);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000196 final_reg &= ~((1 << 16) | (1 << 8) | (1 << 20) | (1 << 14)
197 | (1 << 22) | (1 << 18) | (1 << 17) | (1 << 15)
198 | (1 << 11) | (1 << 10) | (1 << 9));
199 pci_write_config32(sm_dev, 0xe8, final_reg); /* Enable all at first. */
200
Yinghai Luc65bd562007-02-01 00:10:05 +0000201 }
202
203 if (!dev->enabled) {
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000204 final_reg |= (1 << index); /* Disable it. */
205 /*
Martin Rothe9c1b212014-12-09 13:49:34 -0700206 * The reason for using final_reg is that if func 1 is disabled,
207 * then func 2 will become func 1.
208 * Because of this, we need loop through disabling them all at
209 * the same time.
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000210 */
Yinghai Luc65bd562007-02-01 00:10:05 +0000211 }
212
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000213 /* NIC1 is the final, we need update final reg to 0xe8. */
214 if (index == 9) {
Yinghai Luc65bd562007-02-01 00:10:05 +0000215 sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000216 if (!sm_dev)
217 return;
Yinghai Luc65bd562007-02-01 00:10:05 +0000218 reg_old = pci_read_config32(sm_dev, 0xe8);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000219 if (final_reg != reg_old)
Yinghai Luc65bd562007-02-01 00:10:05 +0000220 pci_write_config32(sm_dev, 0xe8, final_reg);
Yinghai Luc65bd562007-02-01 00:10:05 +0000221 }
Yinghai Luc65bd562007-02-01 00:10:05 +0000222}
223
Jonathan Kollaschdca8b1b2010-10-29 20:40:06 +0000224static void mcp55_set_subsystem(device_t dev, unsigned vendor, unsigned device)
225{
226 pci_write_config32(dev, 0x40,
227 ((device & 0xffff) << 16) | (vendor & 0xffff));
228}
229
230struct pci_operations mcp55_pci_ops = {
231 .set_subsystem = mcp55_set_subsystem,
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000232};
Jonathan Kollaschdca8b1b2010-10-29 20:40:06 +0000233
Yinghai Luc65bd562007-02-01 00:10:05 +0000234struct chip_operations southbridge_nvidia_mcp55_ops = {
Uwe Hermann8a202132007-02-19 19:11:20 +0000235 CHIP_NAME("NVIDIA MCP55 Southbridge")
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000236 .enable_dev = mcp55_enable,
Yinghai Luc65bd562007-02-01 00:10:05 +0000237};