blob: 8019a8ef21337b581ee996329d807b4c22391a3d [file] [log] [blame]
Yinghai Luc65bd562007-02-01 00:10:05 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Yinghai Luc65bd562007-02-01 00:10:05 +00003 *
4 * Copyright (C) 2006 AMD
5 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Yinghai Luc65bd562007-02-01 00:10:05 +000016 */
17
Stefan Reinauerd55e26f2010-04-25 13:54:30 +000018#ifdef UNUSED_CODE
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000019int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val);
Myles Watsonad894c52010-04-30 17:11:03 +000020
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000021static int set_ht_link_mcp55(u8 ht_c_num)
Yinghai Luc65bd562007-02-01 00:10:05 +000022{
23 unsigned vendorid = 0x10de;
24 unsigned val = 0x01610109;
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000025 /* NVIDIA MCP55 hardcode, hardware can not set it automatically. */
Yinghai Luc65bd562007-02-01 00:10:05 +000026 return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
27}
28
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000029static void setup_ss_table(unsigned index, unsigned where, unsigned control,
30 const unsigned int *register_values, int max)
Yinghai Luc65bd562007-02-01 00:10:05 +000031{
32 int i;
Yinghai Luc65bd562007-02-01 00:10:05 +000033 unsigned val;
34
35 val = inl(control);
36 val &= 0xfffffffe;
37 outl(val, control);
38
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000039 outl(0, index); /* Index */
40 for (i = 0; i < max; i++) {
Yinghai Luc65bd562007-02-01 00:10:05 +000041 unsigned long reg;
42 reg = register_values[i];
43 outl(reg, where);
44 }
45
46 val = inl(control);
47 val |= 1;
48 outl(val, control);
Yinghai Luc65bd562007-02-01 00:10:05 +000049}
Stefan Reinauerd55e26f2010-04-25 13:54:30 +000050#endif
Yinghai Luc65bd562007-02-01 00:10:05 +000051
52/* SIZE 0x100 */
53#define ANACTRL_IO_BASE 0x2800
54#define ANACTRL_REG_POS 0x68
55
56/* SIZE 0x100 */
57#define SYSCTRL_IO_BASE 0x2400
58#define SYSCTRL_REG_POS 0x64
59
60/* SIZE 0x100 */
61#define ACPICTRL_IO_BASE 0x2000
62#define ACPICTRL_REG_POS 0x60
63
64/*
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000065 * 16 1 1 1 1 8 :0
66 * 16 0 4 0 0 8 :1
67 * 16 0 4 2 2 4 :2
68 * 4 4 4 4 4 8 :3
69 * 8 8 4 0 0 8 :4
70 * 8 0 4 4 4 8 :5
Yinghai Luc65bd562007-02-01 00:10:05 +000071*/
72
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000073#define MCP55_CHIP_REV 3
Yinghai Luc65bd562007-02-01 00:10:05 +000074
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000075static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn,
76 unsigned *devn, unsigned *io_base)
Yinghai Luc65bd562007-02-01 00:10:05 +000077{
78
79 static const unsigned int ctrl_devport_conf[] = {
80 PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
81 PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
82 PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE,
83 };
84
85 int j;
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000086 for (j = 0; j < mcp55_num; j++ ) {
Yinghai Luc65bd562007-02-01 00:10:05 +000087 setup_resource_map_offset(ctrl_devport_conf,
Carl-Daniel Hailfinger2ee67792008-10-01 12:52:52 +000088 ARRAY_SIZE(ctrl_devport_conf),
Yinghai Luc65bd562007-02-01 00:10:05 +000089 PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
90 }
91}
92
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +000093static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn,
94 unsigned *devn, unsigned *io_base)
Yinghai Luc65bd562007-02-01 00:10:05 +000095{
Yinghai Luc65bd562007-02-01 00:10:05 +000096 static const unsigned int ctrl_devport_conf_clear[] = {
97 PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
98 PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
99 PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0,
100 };
101
102 int j;
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000103 for (j = 0; j < mcp55_num; j++ ) {
Yinghai Luc65bd562007-02-01 00:10:05 +0000104 setup_resource_map_offset(ctrl_devport_conf_clear,
Carl-Daniel Hailfinger2ee67792008-10-01 12:52:52 +0000105 ARRAY_SIZE(ctrl_devport_conf_clear),
Yinghai Luc65bd562007-02-01 00:10:05 +0000106 PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
107 }
Yinghai Luc65bd562007-02-01 00:10:05 +0000108}
Yinghai Luc65bd562007-02-01 00:10:05 +0000109
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000110static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx,
111 unsigned anactrl_io_base, unsigned pci_e_x)
Yinghai Luc65bd562007-02-01 00:10:05 +0000112{
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000113 u32 tgio_ctrl, pll_ctrl, dword;
Yinghai Luc65bd562007-02-01 00:10:05 +0000114 int i;
Antonello Dettori8126daf2016-09-03 10:45:33 +0200115 pci_devfn_t dev;
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000116
117 dev = PCI_DEV(busnx, devnx + 1, 1);
118
Yinghai Luc65bd562007-02-01 00:10:05 +0000119 dword = pci_read_config32(dev, 0xe4);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000120 dword |= 0x3f0; /* Disable it at first. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000121 pci_write_config32(dev, 0xe4, dword);
122
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000123 for (i = 0; i < 3; i++) {
Yinghai Luc65bd562007-02-01 00:10:05 +0000124 tgio_ctrl = inl(anactrl_io_base + 0xcc);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000125 tgio_ctrl &= ~(3 << 9);
126 tgio_ctrl |= (i << 9);
Yinghai Luc65bd562007-02-01 00:10:05 +0000127 outl(tgio_ctrl, anactrl_io_base + 0xcc);
128 pll_ctrl = inl(anactrl_io_base + 0x30);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000129 pll_ctrl |= (1 << 31);
Yinghai Luc65bd562007-02-01 00:10:05 +0000130 outl(pll_ctrl, anactrl_io_base + 0x30);
131 do {
132 pll_ctrl = inl(anactrl_io_base + 0x30);
133 } while (!(pll_ctrl & 1));
134 }
135 tgio_ctrl = inl(anactrl_io_base + 0xcc);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000136 tgio_ctrl &= ~((7 << 4) | (1 << 8));
137 tgio_ctrl |= (pci_e_x << 4) | (1 << 8);
Yinghai Luc65bd562007-02-01 00:10:05 +0000138 outl(tgio_ctrl, anactrl_io_base + 0xcc);
139
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000140 udelay(100); /* Wait 100us. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000141
142 dword = pci_read_config32(dev, 0xe4);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000143 dword &= ~(0x3f0); /* Enable. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000144 pci_write_config32(dev, 0xe4, dword);
145
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000146 mdelay(100); /* Need to wait 100ms. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000147}
148
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000149static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
150 unsigned *devn, unsigned *io_base,
151 unsigned *pci_e_x)
Yinghai Luc65bd562007-02-01 00:10:05 +0000152{
Yinghai Luc65bd562007-02-01 00:10:05 +0000153 static const unsigned int ctrl_conf_1[] = {
154 RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
155 RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000,
156 RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200,
157 RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002,
158
159 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230,
160 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222,
161 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000,
162 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000,
163 RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000,
164 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
165 RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200,
166 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
167 RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400,
168 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
169 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000,
170 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010,
171 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500,
172 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000,
173 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000,
174 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00,
175 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000,
176
177 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE,
178 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002,
179 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011,
180 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923,
181 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000,
182 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F,
183 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000,
184
185 RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE,
186 RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084,
187 RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
188
189 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001,
190 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002,
191 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
192
193 RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE,
194 RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF,
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000195 RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000196
197 RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE,
198 RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000199 RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000200 };
201
202 static const unsigned int ctrl_conf_1_1[] = {
203 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE,
204 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003,
205 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001,
206 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000,
207 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100,
208 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000,
209 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A,
210 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000,
211 RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
212 };
213
Yinghai Luc65bd562007-02-01 00:10:05 +0000214 static const unsigned int ctrl_conf_mcp55_only[] = {
215 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE,
216 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
217 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000,
218 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000,
219
220 RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE,
221 RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
222
223 RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE,
224
225 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE,
226 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000,
227 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000,
228 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00,
229 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000,
230 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570,
231 RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
232
233 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104,
234 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000,
235 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000,
236 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005,
237 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000,
238 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
239 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
240 RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
Jonathan A. Kollaschacba73a2015-07-20 09:51:34 -0500241#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
242 /*
243 * Avoid crash (complete with severe memory corruption!) during initial CAR boot
244 * in mcp55_early_setup_x() on Fam10h systems by not touching 0x78.
245 * Interestingly once the system is fully booted into Linux this can be set, but
246 * not before! Apparently something isn't initialized but the amount of effort
247 * required to fix this is non-negligible and of unknown real-world benefit
248 */
249#else
Arne Georg Gleditsche7a5b762010-09-13 15:11:35 +0000250 RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
Jonathan A. Kollaschacba73a2015-07-20 09:51:34 -0500251#endif
Uwe Hermannf845e022007-09-25 01:31:35 +0000252
Martin Roth1858d6a2017-06-24 21:30:42 -0600253#if IS_ENABLED(CONFIG_MCP55_USE_AZA)
Yinghai Luc65bd562007-02-01 00:10:05 +0000254 RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
255
Yinghai Luc65bd562007-02-01 00:10:05 +0000256#endif
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000257
Yinghai Luc65bd562007-02-01 00:10:05 +0000258#ifdef MCP55_MB_SETUP
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000259 /* Play a while with GPIO in MCP55. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000260 MCP55_MB_SETUP
261#endif
262
Martin Roth1858d6a2017-06-24 21:30:42 -0600263#if IS_ENABLED(CONFIG_MCP55_USE_AZA)
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000264 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3 << 2), (2 << 2),
265 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3 << 2), (2 << 2),
266 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3 << 2), (2 << 2),
Yinghai Luc65bd562007-02-01 00:10:05 +0000267#endif
Yinghai Luc65bd562007-02-01 00:10:05 +0000268 };
269
270 static const unsigned int ctrl_conf_master_only[] = {
Yinghai Luc65bd562007-02-01 00:10:05 +0000271 RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000,
272
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000273 /* Master MCP55???? YHLU */
274 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3 << 2), (0 << 2),
Yinghai Luc65bd562007-02-01 00:10:05 +0000275 };
276
277 static const unsigned int ctrl_conf_2[] = {
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000278 /* I didn't put PCI-E related stuff here. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000279
280 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
281 RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000,
282
283 RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000,
284
285 RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
286
Martin Roth1858d6a2017-06-24 21:30:42 -0600287#if IS_ENABLED(CONFIG_MCP55_USE_NIC)
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000288 RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20),
Yinghai Luc65bd562007-02-01 00:10:05 +0000289
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000290 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
291 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
Yinghai Luc65bd562007-02-01 00:10:05 +0000292#endif
Yinghai Luc65bd562007-02-01 00:10:05 +0000293 };
294
Yinghai Luc65bd562007-02-01 00:10:05 +0000295 int j, i;
296
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000297 for (j = 0; j < mcp55_num; j++) {
298 mcp55_early_pcie_setup(busn[j], devn[j],
299 io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
Yinghai Luc65bd562007-02-01 00:10:05 +0000300
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000301 setup_resource_map_x_offset(ctrl_conf_1,
302 ARRAY_SIZE(ctrl_conf_1),
Yinghai Luc65bd562007-02-01 00:10:05 +0000303 PCI_DEV(busn[j], devn[j], 0), io_base[j]);
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000304
305 for (i = 0; i < 3; i++) { /* Three SATA */
306 setup_resource_map_x_offset(ctrl_conf_1_1,
307 ARRAY_SIZE(ctrl_conf_1_1),
Yinghai Luc65bd562007-02-01 00:10:05 +0000308 PCI_DEV(busn[j], devn[j], i), io_base[j]);
309 }
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000310
311 if (busn[j] == 0) {
312 setup_resource_map_x_offset(ctrl_conf_mcp55_only,
313 ARRAY_SIZE(ctrl_conf_mcp55_only),
Yinghai Luc65bd562007-02-01 00:10:05 +0000314 PCI_DEV(busn[j], devn[j], 0), io_base[j]);
315 }
316
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000317 if ((busn[j] == 0) && (mcp55_num>1)) {
318 setup_resource_map_x_offset(ctrl_conf_master_only,
319 ARRAY_SIZE(ctrl_conf_master_only),
Yinghai Luc65bd562007-02-01 00:10:05 +0000320 PCI_DEV(busn[j], devn[j], 0), io_base[j]);
321 }
322
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000323 setup_resource_map_x_offset(ctrl_conf_2,
324 ARRAY_SIZE(ctrl_conf_2),
Yinghai Luc65bd562007-02-01 00:10:05 +0000325 PCI_DEV(busn[j], devn[j], 0), io_base[j]);
Yinghai Luc65bd562007-02-01 00:10:05 +0000326 }
327
Yinghai Luc65bd562007-02-01 00:10:05 +0000328}
329
330#ifndef HT_CHAIN_NUM_MAX
331
332#define HT_CHAIN_NUM_MAX 4
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000333#define HT_CHAIN_BUSN_D 0x40
Yinghai Luc65bd562007-02-01 00:10:05 +0000334#define HT_CHAIN_IOBASE_D 0x4000
335
336#endif
337
338static int mcp55_early_setup_x(void)
339{
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000340 /* Find out how many MCP55 we have. */
Scott Duplichan45057d22010-10-26 05:26:01 +0000341 unsigned busn[HT_CHAIN_NUM_MAX] = {0};
342 unsigned devn[HT_CHAIN_NUM_MAX] = {0};
343 unsigned io_base[HT_CHAIN_NUM_MAX] = {0};
Yinghai Luc65bd562007-02-01 00:10:05 +0000344
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000345 /*
346 * FIXME: May have problem if there is different MCP55 HTX card with
347 * different PCI_E lane allocation. Need to use same trick about
348 * pci1234 to verify node/link connection.
349 */
350 unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {
351 CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1,
352 CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3,
353 };
354 int mcp55_num = 0, ht_c_index;
355 unsigned busnx, devnx;
356
357 /* FIXME: Multi PCI segment handling. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000358
359 /* Any system that only have IO55 without MCP55? */
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000360 for (ht_c_index = 0; ht_c_index < HT_CHAIN_NUM_MAX; ht_c_index++) {
Yinghai Luc65bd562007-02-01 00:10:05 +0000361 busnx = ht_c_index * HT_CHAIN_BUSN_D;
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000362 for (devnx = 0; devnx < 0x20; devnx++) {
363 u32 id;
Antonello Dettori8126daf2016-09-03 10:45:33 +0200364 pci_devfn_t dev;
Yinghai Luc65bd562007-02-01 00:10:05 +0000365 dev = PCI_DEV(busnx, devnx, 0);
366 id = pci_read_config32(dev, PCI_VENDOR_ID);
Elyes HAOUASba28e8d2016-08-31 19:22:16 +0200367 if (id == 0x036910de) {
Yinghai Luc65bd562007-02-01 00:10:05 +0000368 busn[mcp55_num] = busnx;
369 devn[mcp55_num] = devnx;
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000370
371 /* We may have HT chain other than MCP55. */
372 io_base[mcp55_num]
373 = ht_c_index * HT_CHAIN_IOBASE_D;
374
Yinghai Luc65bd562007-02-01 00:10:05 +0000375 mcp55_num++;
Uwe Hermannc7f0c8f2011-01-04 19:51:33 +0000376 if (mcp55_num == CONFIG_MCP55_NUM)
377 goto out;
378 break; /* Only one MCP55 on one chain. */
Yinghai Luc65bd562007-02-01 00:10:05 +0000379 }
380 }
381 }
382
383out:
Stefan Reinauer5ab52dd2015-01-05 13:01:01 -0800384 printk(BIOS_DEBUG, "mcp55_num: %02x\n", mcp55_num);
Yinghai Luc65bd562007-02-01 00:10:05 +0000385
386 mcp55_early_set_port(mcp55_num, busn, devn, io_base);
387 mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x);
388
389 mcp55_early_clear_port(mcp55_num, busn, devn, io_base);
390
Yinghai Luc65bd562007-02-01 00:10:05 +0000391 return 0;
Yinghai Luc65bd562007-02-01 00:10:05 +0000392}